NXP Semiconductors MK20F12 2024.06.02 MK20F12 Freescale Microcontroller CM4 r0p1 little true 4 false 8 32 ADC0 Analog-to-Digital Converter ADC 0x0 0x0 0x70 registers n ADC0 57 INT_ADC0 73 CFG1 ADC configuration register 1 0x8 32 read-write n 0x0 0x0 ADICLK Input clock select 0 2 read-write 00 Bus clock. #00 01 Bus clock divided by 2. #01 10 Alternate clock (ALTCLK). #10 11 Asynchronous clock (ADACK). #11 ADIV Clock divide select 5 2 read-write 00 The divide ratio is 1 and the clock rate is input clock. #00 01 The divide ratio is 2 and the clock rate is (input clock)/2. #01 10 The divide ratio is 4 and the clock rate is (input clock)/4. #10 11 The divide ratio is 8 and the clock rate is (input clock)/8. #11 ADLPC Low-power configuration 7 1 read-write 0 Normal power configuration. #0 1 Low power configuration. The power is reduced at the expense of maximum clock speed. #1 ADLSMP Sample time configuration 4 1 read-write 0 Short sample time. #0 1 Long sample time. #1 MODE Conversion mode selection 2 2 read-write 00 When DIFF=0: It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output. #00 01 When DIFF=0: It is single-ended 12-bit conversion; when DIFF=1, it is differential 13-bit conversion with 2's complement output. #01 10 When DIFF=0: It is single-ended 10-bit conversion; when DIFF=1, it is differential 11-bit conversion with 2's complement output. #10 11 When DIFF=0: It is single-ended 16-bit conversion; when DIFF=1, it is differential 16-bit conversion with 2's complement output . #11 RESERVED no description available 8 24 read-only CFG2 Configuration register 2 0xC 32 read-write n 0x0 0x0 ADACKEN Asynchronous clock output enable 3 1 read-write 0 Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active. #0 1 Asynchronous clock and clock output enabled regardless of the state of the ADC. #1 ADHSC High speed configuration 2 1 read-write 0 Normal conversion sequence selected. #0 1 High speed conversion sequence selected (2 additional ADCK cycles to total conversion time). #1 ADLSTS Long sample time select 0 2 read-write 00 Default longest sample time (20 extra ADCK cycles; 24 ADCK cycles total). #00 01 12 extra ADCK cycles; 16 ADCK cycles total sample time. #01 10 6 extra ADCK cycles; 10 ADCK cycles total sample time. #10 11 2 extra ADCK cycles; 6 ADCK cycles total sample time. #11 MUXSEL ADC Mux select 4 1 read-write 0 ADxxa channels are selected. #0 1 ADxxb channels are selected. #1 RESERVED no description available 5 3 read-only RESERVED no description available 8 24 read-only CLM0 ADC minus-side general calibration value register 0x6C 32 read-write n 0x0 0x0 CLM0 no description available 0 6 read-write RESERVED no description available 6 26 read-only CLM1 ADC minus-side general calibration value register 0x68 32 read-write n 0x0 0x0 CLM1 no description available 0 7 read-write RESERVED no description available 7 25 read-only CLM2 ADC minus-side general calibration value register 0x64 32 read-write n 0x0 0x0 CLM2 no description available 0 8 read-write RESERVED no description available 8 24 read-only CLM3 ADC minus-side general calibration value register 0x60 32 read-write n 0x0 0x0 CLM3 no description available 0 9 read-write RESERVED no description available 9 23 read-only CLM4 ADC minus-side general calibration value register 0x5C 32 read-write n 0x0 0x0 CLM4 no description available 0 10 read-write RESERVED no description available 10 22 read-only CLMD ADC minus-side general calibration value register 0x54 32 read-write n 0x0 0x0 CLMD no description available 0 6 read-write RESERVED no description available 6 26 read-only CLMS ADC minus-side general calibration value register 0x58 32 read-write n 0x0 0x0 CLMS no description available 0 6 read-write RESERVED no description available 6 26 read-only CLP0 ADC plus-side general calibration value register 0x4C 32 read-write n 0x0 0x0 CLP0 no description available 0 6 read-write RESERVED no description available 6 26 read-only CLP1 ADC plus-side general calibration value register 0x48 32 read-write n 0x0 0x0 CLP1 no description available 0 7 read-write RESERVED no description available 7 25 read-only CLP2 ADC plus-side general calibration value register 0x44 32 read-write n 0x0 0x0 CLP2 no description available 0 8 read-write RESERVED no description available 8 24 read-only CLP3 ADC plus-side general calibration value register 0x40 32 read-write n 0x0 0x0 CLP3 no description available 0 9 read-write RESERVED no description available 9 23 read-only CLP4 ADC plus-side general calibration value register 0x3C 32 read-write n 0x0 0x0 CLP4 no description available 0 10 read-write RESERVED no description available 10 22 read-only CLPD ADC plus-side general calibration value register 0x34 32 read-write n 0x0 0x0 CLPD no description available 0 6 read-write RESERVED no description available 6 26 read-only CLPS ADC plus-side general calibration value register 0x38 32 read-write n 0x0 0x0 CLPS no description available 0 6 read-write RESERVED no description available 6 26 read-only CV1 Compare value registers 0x30 32 read-write n 0x0 0x0 CV Compare value 0 16 read-write RESERVED no description available 16 16 read-only CV2 Compare value registers 0x4C 32 read-write n 0x0 0x0 CV Compare value 0 16 read-write RESERVED no description available 16 16 read-only MG ADC minus-side gain register 0x30 32 read-write n 0x0 0x0 MG Minus-side gain 0 16 read-write RESERVED no description available 16 16 read-only OFS ADC offset correction register 0x28 32 read-write n 0x0 0x0 OFS Offset error correction value 0 16 read-write RESERVED no description available 16 16 read-only PG ADC plus-side gain register 0x2C 32 read-write n 0x0 0x0 PG Plus-side gain 0 16 read-write RESERVED no description available 16 16 read-only PGA ADC PGA register 0x50 32 read-write n 0x0 0x0 PGACHPb PGA chopping control 21 1 read-write 0 Chopping enabled. #0 1 Chopping disabled. #1 PGAEN PGA enable 23 1 read-write 0 PGA disabled. #0 1 PGA enabled. #1 PGAG PGA gain setting 16 4 read-write 0000 1 #0000 0001 2 #0001 0010 4 #0010 0011 8 #0011 0100 16 #0100 0101 32 #0101 0110 64 #0110 0111 Reserved #0111 1000 Reserved #1000 1001 Reserved #1001 1010 Reserved #1010 1011 Reserved #1011 1100 Reserved #1100 1101 Reserved #1101 1110 Reserved #1110 1111 Reserved #1111 PGALPb PGA low-power mode control 20 1 read-write 0 PGA runs in low power mode. #0 1 PGA runs in normal power mode. #1 PGAOFSM PGA Offset Measurement 14 1 read-write 0 PGA runs in normal operation. #0 1 PGA runs in offset measurement mode. #1 RESERVED no description available 0 14 read-only RESERVED no description available 15 1 read-only RESERVED no description available 22 1 read-only RESERVED no description available 24 8 read-only RA ADC data result register 0x20 32 read-only n 0x0 0x0 D Data result 0 16 read-only RESERVED no description available 16 16 read-only RB ADC data result register 0x34 32 read-only n 0x0 0x0 D Data result 0 16 read-only RESERVED no description available 16 16 read-only SC1A ADC status and control registers 1 0x0 32 read-write n 0x0 0x0 ADCH Input channel select 0 5 read-write 00000 When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. #00000 00001 When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. #00001 00010 When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. #00010 00011 When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. #00011 00100 When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved. #00100 00101 When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved. #00101 00110 When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. #00110 00111 When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. #00111 01000 When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved. #01000 01001 When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved. #01001 01010 When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. #01010 01011 When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. #01011 01100 When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. #01100 01101 When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. #01101 01110 When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. #01110 01111 When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved. #01111 10000 When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved. #10000 10001 When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved. #10001 10010 When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved. #10010 10011 When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved. #10011 10100 When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved. #10100 10101 When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved. #10101 10110 When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved. #10110 10111 When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. #10111 11000 Reserved. #11000 11001 Reserved. #11001 11010 When DIFF=0, Temp sensor (single-ended) is selected as input; when DIFF=1, Temp sensor (differential) is selected as input. #11010 11011 When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input. #11011 11100 Reserved. #11100 11101 When DIFF=0, VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by the REFSEL bits in the SC2 register. #11101 11110 When DIFF=0, VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by the REFSEL bits in the SC2 register. #11110 11111 Module disabled. #11111 AIEN Interrupt enable 6 1 read-write 0 Conversion complete interrupt disabled. #0 1 Conversion complete interrupt enabled. #1 COCO Conversion complete flag 7 1 read-only 0 Conversion not completed. #0 1 Conversion completed. #1 DIFF Differential mode enable 5 1 read-write 0 Single-ended conversions and input channels are selected. #0 1 Differential conversions and input channels are selected. #1 RESERVED no description available 8 24 read-only SC1B ADC status and control registers 1 0x4 32 read-write n 0x0 0x0 ADCH Input channel select 0 5 read-write 00000 When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. #00000 00001 When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. #00001 00010 When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. #00010 00011 When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. #00011 00100 When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved. #00100 00101 When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved. #00101 00110 When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. #00110 00111 When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. #00111 01000 When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved. #01000 01001 When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved. #01001 01010 When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. #01010 01011 When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. #01011 01100 When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. #01100 01101 When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. #01101 01110 When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. #01110 01111 When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved. #01111 10000 When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved. #10000 10001 When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved. #10001 10010 When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved. #10010 10011 When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved. #10011 10100 When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved. #10100 10101 When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved. #10101 10110 When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved. #10110 10111 When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. #10111 11000 Reserved. #11000 11001 Reserved. #11001 11010 When DIFF=0, Temp sensor (single-ended) is selected as input; when DIFF=1, Temp sensor (differential) is selected as input. #11010 11011 When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input. #11011 11100 Reserved. #11100 11101 When DIFF=0, VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by the REFSEL bits in the SC2 register. #11101 11110 When DIFF=0, VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by the REFSEL bits in the SC2 register. #11110 11111 Module disabled. #11111 AIEN Interrupt enable 6 1 read-write 0 Conversion complete interrupt disabled. #0 1 Conversion complete interrupt enabled. #1 COCO Conversion complete flag 7 1 read-only 0 Conversion not completed. #0 1 Conversion completed. #1 DIFF Differential mode enable 5 1 read-write 0 Single-ended conversions and input channels are selected. #0 1 Differential conversions and input channels are selected. #1 RESERVED no description available 8 24 read-only SC2 Status and control register 2 0x20 32 read-write n 0x0 0x0 ACFE Compare function enable 5 1 read-write 0 Compare function disabled. #0 1 Compare function enabled. #1 ACFGT Compare function greater than enable 4 1 read-write 0 Configures less than threshold, outside range not inclusive and inside range not inclusive functionality based on the values placed in the CV1 and CV2 registers. #0 1 Configures greater than or equal to threshold, outside range inclusive and inside range inclusive functionality based on the values placed in the CV1 and CV2 registers. #1 ACREN Compare function range enable 3 1 read-write 0 Range function disabled. Only the compare value 1 register (CV1) is compared. #0 1 Range function enabled. Both compare value registers (CV1 and CV2) are compared. #1 ADACT Conversion active 7 1 read-only 0 Conversion not in progress. #0 1 Conversion in progress. #1 ADTRG Conversion trigger select 6 1 read-write 0 Software trigger selected. #0 1 Hardware trigger selected. #1 DMAEN DMA enable 2 1 read-write 0 DMA is disabled. #0 1 DMA is enabled and will assert the ADC DMA request during a ADC conversion complete event noted by the assertion of any of the ADC COCO flags. #1 REFSEL Voltage reference selection 0 2 read-write 00 Default voltage reference pin pair (external pins VREFH and VREFL) #00 01 Alternate reference pair (VALTH and VALTL). This pair may be additional external pins or internal sources depending on MCU configuration. Consult the Chip Configuration information for details specific to this MCU. #01 10 Reserved #10 11 Reserved #11 RESERVED no description available 8 24 read-only SC3 Status and control register 3 0x24 32 read-write n 0x0 0x0 ADCO Continuous conversion enable 3 1 read-write 0 One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. #0 1 Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. #1 AVGE Hardware average enable 2 1 read-write 0 Hardware average function disabled. #0 1 Hardware average function enabled. #1 AVGS Hardware average select 0 2 read-write 00 4 samples averaged. #00 01 8 samples averaged. #01 10 16 samples averaged. #10 11 32 samples averaged. #11 CAL Calibration 7 1 read-write CALF Calibration failed flag 6 1 read-only 0 Calibration completed normally. #0 1 Calibration failed. ADC accuracy specifications are not guaranteed. #1 RESERVED no description available 4 2 read-only RESERVED no description available 8 24 read-only ADC1 Analog-to-Digital Converter ADC 0x0 0x0 0x70 registers n ADC1 58 INT_ADC1 74 CFG1 ADC configuration register 1 0x8 32 read-write n 0x0 0x0 ADICLK Input clock select 0 2 read-write 00 Bus clock. #00 01 Bus clock divided by 2. #01 10 Alternate clock (ALTCLK). #10 11 Asynchronous clock (ADACK). #11 ADIV Clock divide select 5 2 read-write 00 The divide ratio is 1 and the clock rate is input clock. #00 01 The divide ratio is 2 and the clock rate is (input clock)/2. #01 10 The divide ratio is 4 and the clock rate is (input clock)/4. #10 11 The divide ratio is 8 and the clock rate is (input clock)/8. #11 ADLPC Low-power configuration 7 1 read-write 0 Normal power configuration. #0 1 Low power configuration. The power is reduced at the expense of maximum clock speed. #1 ADLSMP Sample time configuration 4 1 read-write 0 Short sample time. #0 1 Long sample time. #1 MODE Conversion mode selection 2 2 read-write 00 When DIFF=0: It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output. #00 01 When DIFF=0: It is single-ended 12-bit conversion; when DIFF=1, it is differential 13-bit conversion with 2's complement output. #01 10 When DIFF=0: It is single-ended 10-bit conversion; when DIFF=1, it is differential 11-bit conversion with 2's complement output. #10 11 When DIFF=0: It is single-ended 16-bit conversion; when DIFF=1, it is differential 16-bit conversion with 2's complement output . #11 RESERVED no description available 8 24 read-only CFG2 Configuration register 2 0xC 32 read-write n 0x0 0x0 ADACKEN Asynchronous clock output enable 3 1 read-write 0 Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active. #0 1 Asynchronous clock and clock output enabled regardless of the state of the ADC. #1 ADHSC High speed configuration 2 1 read-write 0 Normal conversion sequence selected. #0 1 High speed conversion sequence selected (2 additional ADCK cycles to total conversion time). #1 ADLSTS Long sample time select 0 2 read-write 00 Default longest sample time (20 extra ADCK cycles; 24 ADCK cycles total). #00 01 12 extra ADCK cycles; 16 ADCK cycles total sample time. #01 10 6 extra ADCK cycles; 10 ADCK cycles total sample time. #10 11 2 extra ADCK cycles; 6 ADCK cycles total sample time. #11 MUXSEL ADC Mux select 4 1 read-write 0 ADxxa channels are selected. #0 1 ADxxb channels are selected. #1 RESERVED no description available 5 3 read-only RESERVED no description available 8 24 read-only CLM0 ADC minus-side general calibration value register 0x6C 32 read-write n 0x0 0x0 CLM0 no description available 0 6 read-write RESERVED no description available 6 26 read-only CLM1 ADC minus-side general calibration value register 0x68 32 read-write n 0x0 0x0 CLM1 no description available 0 7 read-write RESERVED no description available 7 25 read-only CLM2 ADC minus-side general calibration value register 0x64 32 read-write n 0x0 0x0 CLM2 no description available 0 8 read-write RESERVED no description available 8 24 read-only CLM3 ADC minus-side general calibration value register 0x60 32 read-write n 0x0 0x0 CLM3 no description available 0 9 read-write RESERVED no description available 9 23 read-only CLM4 ADC minus-side general calibration value register 0x5C 32 read-write n 0x0 0x0 CLM4 no description available 0 10 read-write RESERVED no description available 10 22 read-only CLMD ADC minus-side general calibration value register 0x54 32 read-write n 0x0 0x0 CLMD no description available 0 6 read-write RESERVED no description available 6 26 read-only CLMS ADC minus-side general calibration value register 0x58 32 read-write n 0x0 0x0 CLMS no description available 0 6 read-write RESERVED no description available 6 26 read-only CLP0 ADC plus-side general calibration value register 0x4C 32 read-write n 0x0 0x0 CLP0 no description available 0 6 read-write RESERVED no description available 6 26 read-only CLP1 ADC plus-side general calibration value register 0x48 32 read-write n 0x0 0x0 CLP1 no description available 0 7 read-write RESERVED no description available 7 25 read-only CLP2 ADC plus-side general calibration value register 0x44 32 read-write n 0x0 0x0 CLP2 no description available 0 8 read-write RESERVED no description available 8 24 read-only CLP3 ADC plus-side general calibration value register 0x40 32 read-write n 0x0 0x0 CLP3 no description available 0 9 read-write RESERVED no description available 9 23 read-only CLP4 ADC plus-side general calibration value register 0x3C 32 read-write n 0x0 0x0 CLP4 no description available 0 10 read-write RESERVED no description available 10 22 read-only CLPD ADC plus-side general calibration value register 0x34 32 read-write n 0x0 0x0 CLPD no description available 0 6 read-write RESERVED no description available 6 26 read-only CLPS ADC plus-side general calibration value register 0x38 32 read-write n 0x0 0x0 CLPS no description available 0 6 read-write RESERVED no description available 6 26 read-only CV1 Compare value registers 0x30 32 read-write n 0x0 0x0 CV Compare value 0 16 read-write RESERVED no description available 16 16 read-only CV2 Compare value registers 0x4C 32 read-write n 0x0 0x0 CV Compare value 0 16 read-write RESERVED no description available 16 16 read-only MG ADC minus-side gain register 0x30 32 read-write n 0x0 0x0 MG Minus-side gain 0 16 read-write RESERVED no description available 16 16 read-only OFS ADC offset correction register 0x28 32 read-write n 0x0 0x0 OFS Offset error correction value 0 16 read-write RESERVED no description available 16 16 read-only PG ADC plus-side gain register 0x2C 32 read-write n 0x0 0x0 PG Plus-side gain 0 16 read-write RESERVED no description available 16 16 read-only PGA ADC PGA register 0x50 32 read-write n 0x0 0x0 PGACHPb PGA chopping control 21 1 read-write 0 Chopping enabled. #0 1 Chopping disabled. #1 PGAEN PGA enable 23 1 read-write 0 PGA disabled. #0 1 PGA enabled. #1 PGAG PGA gain setting 16 4 read-write 0000 1 #0000 0001 2 #0001 0010 4 #0010 0011 8 #0011 0100 16 #0100 0101 32 #0101 0110 64 #0110 0111 Reserved #0111 1000 Reserved #1000 1001 Reserved #1001 1010 Reserved #1010 1011 Reserved #1011 1100 Reserved #1100 1101 Reserved #1101 1110 Reserved #1110 1111 Reserved #1111 PGALPb PGA low-power mode control 20 1 read-write 0 PGA runs in low power mode. #0 1 PGA runs in normal power mode. #1 PGAOFSM PGA Offset Measurement 14 1 read-write 0 PGA runs in normal operation. #0 1 PGA runs in offset measurement mode. #1 RESERVED no description available 0 14 read-only RESERVED no description available 15 1 read-only RESERVED no description available 22 1 read-only RESERVED no description available 24 8 read-only RA ADC data result register 0x20 32 read-only n 0x0 0x0 D Data result 0 16 read-only RESERVED no description available 16 16 read-only RB ADC data result register 0x34 32 read-only n 0x0 0x0 D Data result 0 16 read-only RESERVED no description available 16 16 read-only SC1A ADC status and control registers 1 0x0 32 read-write n 0x0 0x0 ADCH Input channel select 0 5 read-write 00000 When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. #00000 00001 When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. #00001 00010 When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. #00010 00011 When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. #00011 00100 When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved. #00100 00101 When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved. #00101 00110 When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. #00110 00111 When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. #00111 01000 When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved. #01000 01001 When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved. #01001 01010 When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. #01010 01011 When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. #01011 01100 When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. #01100 01101 When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. #01101 01110 When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. #01110 01111 When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved. #01111 10000 When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved. #10000 10001 When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved. #10001 10010 When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved. #10010 10011 When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved. #10011 10100 When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved. #10100 10101 When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved. #10101 10110 When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved. #10110 10111 When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. #10111 11000 Reserved. #11000 11001 Reserved. #11001 11010 When DIFF=0, Temp sensor (single-ended) is selected as input; when DIFF=1, Temp sensor (differential) is selected as input. #11010 11011 When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input. #11011 11100 Reserved. #11100 11101 When DIFF=0, VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by the REFSEL bits in the SC2 register. #11101 11110 When DIFF=0, VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by the REFSEL bits in the SC2 register. #11110 11111 Module disabled. #11111 AIEN Interrupt enable 6 1 read-write 0 Conversion complete interrupt disabled. #0 1 Conversion complete interrupt enabled. #1 COCO Conversion complete flag 7 1 read-only 0 Conversion not completed. #0 1 Conversion completed. #1 DIFF Differential mode enable 5 1 read-write 0 Single-ended conversions and input channels are selected. #0 1 Differential conversions and input channels are selected. #1 RESERVED no description available 8 24 read-only SC1B ADC status and control registers 1 0x4 32 read-write n 0x0 0x0 ADCH Input channel select 0 5 read-write 00000 When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. #00000 00001 When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. #00001 00010 When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. #00010 00011 When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. #00011 00100 When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved. #00100 00101 When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved. #00101 00110 When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. #00110 00111 When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. #00111 01000 When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved. #01000 01001 When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved. #01001 01010 When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. #01010 01011 When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. #01011 01100 When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. #01100 01101 When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. #01101 01110 When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. #01110 01111 When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved. #01111 10000 When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved. #10000 10001 When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved. #10001 10010 When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved. #10010 10011 When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved. #10011 10100 When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved. #10100 10101 When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved. #10101 10110 When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved. #10110 10111 When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. #10111 11000 Reserved. #11000 11001 Reserved. #11001 11010 When DIFF=0, Temp sensor (single-ended) is selected as input; when DIFF=1, Temp sensor (differential) is selected as input. #11010 11011 When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input. #11011 11100 Reserved. #11100 11101 When DIFF=0, VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by the REFSEL bits in the SC2 register. #11101 11110 When DIFF=0, VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by the REFSEL bits in the SC2 register. #11110 11111 Module disabled. #11111 AIEN Interrupt enable 6 1 read-write 0 Conversion complete interrupt disabled. #0 1 Conversion complete interrupt enabled. #1 COCO Conversion complete flag 7 1 read-only 0 Conversion not completed. #0 1 Conversion completed. #1 DIFF Differential mode enable 5 1 read-write 0 Single-ended conversions and input channels are selected. #0 1 Differential conversions and input channels are selected. #1 RESERVED no description available 8 24 read-only SC2 Status and control register 2 0x20 32 read-write n 0x0 0x0 ACFE Compare function enable 5 1 read-write 0 Compare function disabled. #0 1 Compare function enabled. #1 ACFGT Compare function greater than enable 4 1 read-write 0 Configures less than threshold, outside range not inclusive and inside range not inclusive functionality based on the values placed in the CV1 and CV2 registers. #0 1 Configures greater than or equal to threshold, outside range inclusive and inside range inclusive functionality based on the values placed in the CV1 and CV2 registers. #1 ACREN Compare function range enable 3 1 read-write 0 Range function disabled. Only the compare value 1 register (CV1) is compared. #0 1 Range function enabled. Both compare value registers (CV1 and CV2) are compared. #1 ADACT Conversion active 7 1 read-only 0 Conversion not in progress. #0 1 Conversion in progress. #1 ADTRG Conversion trigger select 6 1 read-write 0 Software trigger selected. #0 1 Hardware trigger selected. #1 DMAEN DMA enable 2 1 read-write 0 DMA is disabled. #0 1 DMA is enabled and will assert the ADC DMA request during a ADC conversion complete event noted by the assertion of any of the ADC COCO flags. #1 REFSEL Voltage reference selection 0 2 read-write 00 Default voltage reference pin pair (external pins VREFH and VREFL) #00 01 Alternate reference pair (VALTH and VALTL). This pair may be additional external pins or internal sources depending on MCU configuration. Consult the Chip Configuration information for details specific to this MCU. #01 10 Reserved #10 11 Reserved #11 RESERVED no description available 8 24 read-only SC3 Status and control register 3 0x24 32 read-write n 0x0 0x0 ADCO Continuous conversion enable 3 1 read-write 0 One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. #0 1 Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. #1 AVGE Hardware average enable 2 1 read-write 0 Hardware average function disabled. #0 1 Hardware average function enabled. #1 AVGS Hardware average select 0 2 read-write 00 4 samples averaged. #00 01 8 samples averaged. #01 10 16 samples averaged. #10 11 32 samples averaged. #11 CAL Calibration 7 1 read-write CALF Calibration failed flag 6 1 read-only 0 Calibration completed normally. #0 1 Calibration failed. ADC accuracy specifications are not guaranteed. #1 RESERVED no description available 4 2 read-only RESERVED no description available 8 24 read-only ADC2 Analog-to-Digital Converter ADC 0x0 0x0 0x70 registers n ADC2 102 INT_ADC2 118 CFG1 ADC configuration register 1 0x8 32 read-write n 0x0 0x0 ADICLK Input clock select 0 2 read-write 00 Bus clock. #00 01 Bus clock divided by 2. #01 10 Alternate clock (ALTCLK). #10 11 Asynchronous clock (ADACK). #11 ADIV Clock divide select 5 2 read-write 00 The divide ratio is 1 and the clock rate is input clock. #00 01 The divide ratio is 2 and the clock rate is (input clock)/2. #01 10 The divide ratio is 4 and the clock rate is (input clock)/4. #10 11 The divide ratio is 8 and the clock rate is (input clock)/8. #11 ADLPC Low-power configuration 7 1 read-write 0 Normal power configuration. #0 1 Low power configuration. The power is reduced at the expense of maximum clock speed. #1 ADLSMP Sample time configuration 4 1 read-write 0 Short sample time. #0 1 Long sample time. #1 MODE Conversion mode selection 2 2 read-write 00 When DIFF=0: It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output. #00 01 When DIFF=0: It is single-ended 12-bit conversion; when DIFF=1, it is differential 13-bit conversion with 2's complement output. #01 10 When DIFF=0: It is single-ended 10-bit conversion; when DIFF=1, it is differential 11-bit conversion with 2's complement output. #10 11 When DIFF=0: It is single-ended 16-bit conversion; when DIFF=1, it is differential 16-bit conversion with 2's complement output . #11 RESERVED no description available 8 24 read-only CFG2 Configuration register 2 0xC 32 read-write n 0x0 0x0 ADACKEN Asynchronous clock output enable 3 1 read-write 0 Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active. #0 1 Asynchronous clock and clock output enabled regardless of the state of the ADC. #1 ADHSC High speed configuration 2 1 read-write 0 Normal conversion sequence selected. #0 1 High speed conversion sequence selected (2 additional ADCK cycles to total conversion time). #1 ADLSTS Long sample time select 0 2 read-write 00 Default longest sample time (20 extra ADCK cycles; 24 ADCK cycles total). #00 01 12 extra ADCK cycles; 16 ADCK cycles total sample time. #01 10 6 extra ADCK cycles; 10 ADCK cycles total sample time. #10 11 2 extra ADCK cycles; 6 ADCK cycles total sample time. #11 MUXSEL ADC Mux select 4 1 read-write 0 ADxxa channels are selected. #0 1 ADxxb channels are selected. #1 RESERVED no description available 5 3 read-only RESERVED no description available 8 24 read-only CLM0 ADC minus-side general calibration value register 0x6C 32 read-write n 0x0 0x0 CLM0 no description available 0 6 read-write RESERVED no description available 6 26 read-only CLM1 ADC minus-side general calibration value register 0x68 32 read-write n 0x0 0x0 CLM1 no description available 0 7 read-write RESERVED no description available 7 25 read-only CLM2 ADC minus-side general calibration value register 0x64 32 read-write n 0x0 0x0 CLM2 no description available 0 8 read-write RESERVED no description available 8 24 read-only CLM3 ADC minus-side general calibration value register 0x60 32 read-write n 0x0 0x0 CLM3 no description available 0 9 read-write RESERVED no description available 9 23 read-only CLM4 ADC minus-side general calibration value register 0x5C 32 read-write n 0x0 0x0 CLM4 no description available 0 10 read-write RESERVED no description available 10 22 read-only CLMD ADC minus-side general calibration value register 0x54 32 read-write n 0x0 0x0 CLMD no description available 0 6 read-write RESERVED no description available 6 26 read-only CLMS ADC minus-side general calibration value register 0x58 32 read-write n 0x0 0x0 CLMS no description available 0 6 read-write RESERVED no description available 6 26 read-only CLP0 ADC plus-side general calibration value register 0x4C 32 read-write n 0x0 0x0 CLP0 no description available 0 6 read-write RESERVED no description available 6 26 read-only CLP1 ADC plus-side general calibration value register 0x48 32 read-write n 0x0 0x0 CLP1 no description available 0 7 read-write RESERVED no description available 7 25 read-only CLP2 ADC plus-side general calibration value register 0x44 32 read-write n 0x0 0x0 CLP2 no description available 0 8 read-write RESERVED no description available 8 24 read-only CLP3 ADC plus-side general calibration value register 0x40 32 read-write n 0x0 0x0 CLP3 no description available 0 9 read-write RESERVED no description available 9 23 read-only CLP4 ADC plus-side general calibration value register 0x3C 32 read-write n 0x0 0x0 CLP4 no description available 0 10 read-write RESERVED no description available 10 22 read-only CLPD ADC plus-side general calibration value register 0x34 32 read-write n 0x0 0x0 CLPD no description available 0 6 read-write RESERVED no description available 6 26 read-only CLPS ADC plus-side general calibration value register 0x38 32 read-write n 0x0 0x0 CLPS no description available 0 6 read-write RESERVED no description available 6 26 read-only CV1 Compare value registers 0x30 32 read-write n 0x0 0x0 CV Compare value 0 16 read-write RESERVED no description available 16 16 read-only CV2 Compare value registers 0x4C 32 read-write n 0x0 0x0 CV Compare value 0 16 read-write RESERVED no description available 16 16 read-only MG ADC minus-side gain register 0x30 32 read-write n 0x0 0x0 MG Minus-side gain 0 16 read-write RESERVED no description available 16 16 read-only OFS ADC offset correction register 0x28 32 read-write n 0x0 0x0 OFS Offset error correction value 0 16 read-write RESERVED no description available 16 16 read-only PG ADC plus-side gain register 0x2C 32 read-write n 0x0 0x0 PG Plus-side gain 0 16 read-write RESERVED no description available 16 16 read-only PGA ADC PGA register 0x50 32 read-write n 0x0 0x0 PGACHPb PGA chopping control 21 1 read-write 0 Chopping enabled. #0 1 Chopping disabled. #1 PGAEN PGA enable 23 1 read-write 0 PGA disabled. #0 1 PGA enabled. #1 PGAG PGA gain setting 16 4 read-write 0000 1 #0000 0001 2 #0001 0010 4 #0010 0011 8 #0011 0100 16 #0100 0101 32 #0101 0110 64 #0110 0111 Reserved #0111 1000 Reserved #1000 1001 Reserved #1001 1010 Reserved #1010 1011 Reserved #1011 1100 Reserved #1100 1101 Reserved #1101 1110 Reserved #1110 1111 Reserved #1111 PGALPb PGA low-power mode control 20 1 read-write 0 PGA runs in low power mode. #0 1 PGA runs in normal power mode. #1 PGAOFSM PGA Offset Measurement 14 1 read-write 0 PGA runs in normal operation. #0 1 PGA runs in offset measurement mode. #1 RESERVED no description available 0 14 read-only RESERVED no description available 15 1 read-only RESERVED no description available 22 1 read-only RESERVED no description available 24 8 read-only RA ADC data result register 0x20 32 read-only n 0x0 0x0 D Data result 0 16 read-only RESERVED no description available 16 16 read-only RB ADC data result register 0x34 32 read-only n 0x0 0x0 D Data result 0 16 read-only RESERVED no description available 16 16 read-only SC1A ADC status and control registers 1 0x0 32 read-write n 0x0 0x0 ADCH Input channel select 0 5 read-write 00000 When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. #00000 00001 When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. #00001 00010 When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. #00010 00011 When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. #00011 00100 When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved. #00100 00101 When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved. #00101 00110 When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. #00110 00111 When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. #00111 01000 When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved. #01000 01001 When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved. #01001 01010 When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. #01010 01011 When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. #01011 01100 When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. #01100 01101 When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. #01101 01110 When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. #01110 01111 When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved. #01111 10000 When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved. #10000 10001 When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved. #10001 10010 When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved. #10010 10011 When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved. #10011 10100 When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved. #10100 10101 When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved. #10101 10110 When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved. #10110 10111 When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. #10111 11000 Reserved. #11000 11001 Reserved. #11001 11010 When DIFF=0, Temp sensor (single-ended) is selected as input; when DIFF=1, Temp sensor (differential) is selected as input. #11010 11011 When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input. #11011 11100 Reserved. #11100 11101 When DIFF=0, VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by the REFSEL bits in the SC2 register. #11101 11110 When DIFF=0, VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by the REFSEL bits in the SC2 register. #11110 11111 Module disabled. #11111 AIEN Interrupt enable 6 1 read-write 0 Conversion complete interrupt disabled. #0 1 Conversion complete interrupt enabled. #1 COCO Conversion complete flag 7 1 read-only 0 Conversion not completed. #0 1 Conversion completed. #1 DIFF Differential mode enable 5 1 read-write 0 Single-ended conversions and input channels are selected. #0 1 Differential conversions and input channels are selected. #1 RESERVED no description available 8 24 read-only SC1B ADC status and control registers 1 0x4 32 read-write n 0x0 0x0 ADCH Input channel select 0 5 read-write 00000 When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. #00000 00001 When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. #00001 00010 When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. #00010 00011 When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. #00011 00100 When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved. #00100 00101 When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved. #00101 00110 When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. #00110 00111 When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. #00111 01000 When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved. #01000 01001 When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved. #01001 01010 When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. #01010 01011 When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. #01011 01100 When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. #01100 01101 When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. #01101 01110 When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. #01110 01111 When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved. #01111 10000 When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved. #10000 10001 When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved. #10001 10010 When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved. #10010 10011 When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved. #10011 10100 When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved. #10100 10101 When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved. #10101 10110 When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved. #10110 10111 When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. #10111 11000 Reserved. #11000 11001 Reserved. #11001 11010 When DIFF=0, Temp sensor (single-ended) is selected as input; when DIFF=1, Temp sensor (differential) is selected as input. #11010 11011 When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input. #11011 11100 Reserved. #11100 11101 When DIFF=0, VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by the REFSEL bits in the SC2 register. #11101 11110 When DIFF=0, VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by the REFSEL bits in the SC2 register. #11110 11111 Module disabled. #11111 AIEN Interrupt enable 6 1 read-write 0 Conversion complete interrupt disabled. #0 1 Conversion complete interrupt enabled. #1 COCO Conversion complete flag 7 1 read-only 0 Conversion not completed. #0 1 Conversion completed. #1 DIFF Differential mode enable 5 1 read-write 0 Single-ended conversions and input channels are selected. #0 1 Differential conversions and input channels are selected. #1 RESERVED no description available 8 24 read-only SC2 Status and control register 2 0x20 32 read-write n 0x0 0x0 ACFE Compare function enable 5 1 read-write 0 Compare function disabled. #0 1 Compare function enabled. #1 ACFGT Compare function greater than enable 4 1 read-write 0 Configures less than threshold, outside range not inclusive and inside range not inclusive functionality based on the values placed in the CV1 and CV2 registers. #0 1 Configures greater than or equal to threshold, outside range inclusive and inside range inclusive functionality based on the values placed in the CV1 and CV2 registers. #1 ACREN Compare function range enable 3 1 read-write 0 Range function disabled. Only the compare value 1 register (CV1) is compared. #0 1 Range function enabled. Both compare value registers (CV1 and CV2) are compared. #1 ADACT Conversion active 7 1 read-only 0 Conversion not in progress. #0 1 Conversion in progress. #1 ADTRG Conversion trigger select 6 1 read-write 0 Software trigger selected. #0 1 Hardware trigger selected. #1 DMAEN DMA enable 2 1 read-write 0 DMA is disabled. #0 1 DMA is enabled and will assert the ADC DMA request during a ADC conversion complete event noted by the assertion of any of the ADC COCO flags. #1 REFSEL Voltage reference selection 0 2 read-write 00 Default voltage reference pin pair (external pins VREFH and VREFL) #00 01 Alternate reference pair (VALTH and VALTL). This pair may be additional external pins or internal sources depending on MCU configuration. Consult the Chip Configuration information for details specific to this MCU. #01 10 Reserved #10 11 Reserved #11 RESERVED no description available 8 24 read-only SC3 Status and control register 3 0x24 32 read-write n 0x0 0x0 ADCO Continuous conversion enable 3 1 read-write 0 One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. #0 1 Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. #1 AVGE Hardware average enable 2 1 read-write 0 Hardware average function disabled. #0 1 Hardware average function enabled. #1 AVGS Hardware average select 0 2 read-write 00 4 samples averaged. #00 01 8 samples averaged. #01 10 16 samples averaged. #10 11 32 samples averaged. #11 CAL Calibration 7 1 read-write CALF Calibration failed flag 6 1 read-only 0 Calibration completed normally. #0 1 Calibration failed. ADC accuracy specifications are not guaranteed. #1 RESERVED no description available 4 2 read-only RESERVED no description available 8 24 read-only ADC3 Analog-to-Digital Converter ADC 0x0 0x0 0x70 registers n ADC3 103 INT_ADC3 119 CFG1 ADC configuration register 1 0x8 32 read-write n 0x0 0x0 ADICLK Input clock select 0 2 read-write 00 Bus clock. #00 01 Bus clock divided by 2. #01 10 Alternate clock (ALTCLK). #10 11 Asynchronous clock (ADACK). #11 ADIV Clock divide select 5 2 read-write 00 The divide ratio is 1 and the clock rate is input clock. #00 01 The divide ratio is 2 and the clock rate is (input clock)/2. #01 10 The divide ratio is 4 and the clock rate is (input clock)/4. #10 11 The divide ratio is 8 and the clock rate is (input clock)/8. #11 ADLPC Low-power configuration 7 1 read-write 0 Normal power configuration. #0 1 Low power configuration. The power is reduced at the expense of maximum clock speed. #1 ADLSMP Sample time configuration 4 1 read-write 0 Short sample time. #0 1 Long sample time. #1 MODE Conversion mode selection 2 2 read-write 00 When DIFF=0: It is single-ended 8-bit conversion; when DIFF=1, it is differential 9-bit conversion with 2's complement output. #00 01 When DIFF=0: It is single-ended 12-bit conversion; when DIFF=1, it is differential 13-bit conversion with 2's complement output. #01 10 When DIFF=0: It is single-ended 10-bit conversion; when DIFF=1, it is differential 11-bit conversion with 2's complement output. #10 11 When DIFF=0: It is single-ended 16-bit conversion; when DIFF=1, it is differential 16-bit conversion with 2's complement output . #11 RESERVED no description available 8 24 read-only CFG2 Configuration register 2 0xC 32 read-write n 0x0 0x0 ADACKEN Asynchronous clock output enable 3 1 read-write 0 Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active. #0 1 Asynchronous clock and clock output enabled regardless of the state of the ADC. #1 ADHSC High speed configuration 2 1 read-write 0 Normal conversion sequence selected. #0 1 High speed conversion sequence selected (2 additional ADCK cycles to total conversion time). #1 ADLSTS Long sample time select 0 2 read-write 00 Default longest sample time (20 extra ADCK cycles; 24 ADCK cycles total). #00 01 12 extra ADCK cycles; 16 ADCK cycles total sample time. #01 10 6 extra ADCK cycles; 10 ADCK cycles total sample time. #10 11 2 extra ADCK cycles; 6 ADCK cycles total sample time. #11 MUXSEL ADC Mux select 4 1 read-write 0 ADxxa channels are selected. #0 1 ADxxb channels are selected. #1 RESERVED no description available 5 3 read-only RESERVED no description available 8 24 read-only CLM0 ADC minus-side general calibration value register 0x6C 32 read-write n 0x0 0x0 CLM0 no description available 0 6 read-write RESERVED no description available 6 26 read-only CLM1 ADC minus-side general calibration value register 0x68 32 read-write n 0x0 0x0 CLM1 no description available 0 7 read-write RESERVED no description available 7 25 read-only CLM2 ADC minus-side general calibration value register 0x64 32 read-write n 0x0 0x0 CLM2 no description available 0 8 read-write RESERVED no description available 8 24 read-only CLM3 ADC minus-side general calibration value register 0x60 32 read-write n 0x0 0x0 CLM3 no description available 0 9 read-write RESERVED no description available 9 23 read-only CLM4 ADC minus-side general calibration value register 0x5C 32 read-write n 0x0 0x0 CLM4 no description available 0 10 read-write RESERVED no description available 10 22 read-only CLMD ADC minus-side general calibration value register 0x54 32 read-write n 0x0 0x0 CLMD no description available 0 6 read-write RESERVED no description available 6 26 read-only CLMS ADC minus-side general calibration value register 0x58 32 read-write n 0x0 0x0 CLMS no description available 0 6 read-write RESERVED no description available 6 26 read-only CLP0 ADC plus-side general calibration value register 0x4C 32 read-write n 0x0 0x0 CLP0 no description available 0 6 read-write RESERVED no description available 6 26 read-only CLP1 ADC plus-side general calibration value register 0x48 32 read-write n 0x0 0x0 CLP1 no description available 0 7 read-write RESERVED no description available 7 25 read-only CLP2 ADC plus-side general calibration value register 0x44 32 read-write n 0x0 0x0 CLP2 no description available 0 8 read-write RESERVED no description available 8 24 read-only CLP3 ADC plus-side general calibration value register 0x40 32 read-write n 0x0 0x0 CLP3 no description available 0 9 read-write RESERVED no description available 9 23 read-only CLP4 ADC plus-side general calibration value register 0x3C 32 read-write n 0x0 0x0 CLP4 no description available 0 10 read-write RESERVED no description available 10 22 read-only CLPD ADC plus-side general calibration value register 0x34 32 read-write n 0x0 0x0 CLPD no description available 0 6 read-write RESERVED no description available 6 26 read-only CLPS ADC plus-side general calibration value register 0x38 32 read-write n 0x0 0x0 CLPS no description available 0 6 read-write RESERVED no description available 6 26 read-only CV1 Compare value registers 0x30 32 read-write n 0x0 0x0 CV Compare value 0 16 read-write RESERVED no description available 16 16 read-only CV2 Compare value registers 0x4C 32 read-write n 0x0 0x0 CV Compare value 0 16 read-write RESERVED no description available 16 16 read-only MG ADC minus-side gain register 0x30 32 read-write n 0x0 0x0 MG Minus-side gain 0 16 read-write RESERVED no description available 16 16 read-only OFS ADC offset correction register 0x28 32 read-write n 0x0 0x0 OFS Offset error correction value 0 16 read-write RESERVED no description available 16 16 read-only PG ADC plus-side gain register 0x2C 32 read-write n 0x0 0x0 PG Plus-side gain 0 16 read-write RESERVED no description available 16 16 read-only PGA ADC PGA register 0x50 32 read-write n 0x0 0x0 PGACHPb PGA chopping control 21 1 read-write 0 Chopping enabled. #0 1 Chopping disabled. #1 PGAEN PGA enable 23 1 read-write 0 PGA disabled. #0 1 PGA enabled. #1 PGAG PGA gain setting 16 4 read-write 0000 1 #0000 0001 2 #0001 0010 4 #0010 0011 8 #0011 0100 16 #0100 0101 32 #0101 0110 64 #0110 0111 Reserved #0111 1000 Reserved #1000 1001 Reserved #1001 1010 Reserved #1010 1011 Reserved #1011 1100 Reserved #1100 1101 Reserved #1101 1110 Reserved #1110 1111 Reserved #1111 PGALPb PGA low-power mode control 20 1 read-write 0 PGA runs in low power mode. #0 1 PGA runs in normal power mode. #1 PGAOFSM PGA Offset Measurement 14 1 read-write 0 PGA runs in normal operation. #0 1 PGA runs in offset measurement mode. #1 RESERVED no description available 0 14 read-only RESERVED no description available 15 1 read-only RESERVED no description available 22 1 read-only RESERVED no description available 24 8 read-only RA ADC data result register 0x20 32 read-only n 0x0 0x0 D Data result 0 16 read-only RESERVED no description available 16 16 read-only RB ADC data result register 0x34 32 read-only n 0x0 0x0 D Data result 0 16 read-only RESERVED no description available 16 16 read-only SC1A ADC status and control registers 1 0x0 32 read-write n 0x0 0x0 ADCH Input channel select 0 5 read-write 00000 When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. #00000 00001 When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. #00001 00010 When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. #00010 00011 When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. #00011 00100 When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved. #00100 00101 When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved. #00101 00110 When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. #00110 00111 When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. #00111 01000 When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved. #01000 01001 When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved. #01001 01010 When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. #01010 01011 When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. #01011 01100 When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. #01100 01101 When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. #01101 01110 When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. #01110 01111 When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved. #01111 10000 When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved. #10000 10001 When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved. #10001 10010 When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved. #10010 10011 When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved. #10011 10100 When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved. #10100 10101 When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved. #10101 10110 When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved. #10110 10111 When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. #10111 11000 Reserved. #11000 11001 Reserved. #11001 11010 When DIFF=0, Temp sensor (single-ended) is selected as input; when DIFF=1, Temp sensor (differential) is selected as input. #11010 11011 When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input. #11011 11100 Reserved. #11100 11101 When DIFF=0, VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by the REFSEL bits in the SC2 register. #11101 11110 When DIFF=0, VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by the REFSEL bits in the SC2 register. #11110 11111 Module disabled. #11111 AIEN Interrupt enable 6 1 read-write 0 Conversion complete interrupt disabled. #0 1 Conversion complete interrupt enabled. #1 COCO Conversion complete flag 7 1 read-only 0 Conversion not completed. #0 1 Conversion completed. #1 DIFF Differential mode enable 5 1 read-write 0 Single-ended conversions and input channels are selected. #0 1 Differential conversions and input channels are selected. #1 RESERVED no description available 8 24 read-only SC1B ADC status and control registers 1 0x4 32 read-write n 0x0 0x0 ADCH Input channel select 0 5 read-write 00000 When DIFF=0, DADP0 is selected as input; when DIFF=1, DAD0 is selected as input. #00000 00001 When DIFF=0, DADP1 is selected as input; when DIFF=1, DAD1 is selected as input. #00001 00010 When DIFF=0, DADP2 is selected as input; when DIFF=1, DAD2 is selected as input. #00010 00011 When DIFF=0, DADP3 is selected as input; when DIFF=1, DAD3 is selected as input. #00011 00100 When DIFF=0, AD4 is selected as input; when DIFF=1, it is reserved. #00100 00101 When DIFF=0, AD5 is selected as input; when DIFF=1, it is reserved. #00101 00110 When DIFF=0, AD6 is selected as input; when DIFF=1, it is reserved. #00110 00111 When DIFF=0, AD7 is selected as input; when DIFF=1, it is reserved. #00111 01000 When DIFF=0, AD8 is selected as input; when DIFF=1, it is reserved. #01000 01001 When DIFF=0, AD9 is selected as input; when DIFF=1, it is reserved. #01001 01010 When DIFF=0, AD10 is selected as input; when DIFF=1, it is reserved. #01010 01011 When DIFF=0, AD11 is selected as input; when DIFF=1, it is reserved. #01011 01100 When DIFF=0, AD12 is selected as input; when DIFF=1, it is reserved. #01100 01101 When DIFF=0, AD13 is selected as input; when DIFF=1, it is reserved. #01101 01110 When DIFF=0, AD14 is selected as input; when DIFF=1, it is reserved. #01110 01111 When DIFF=0, AD15 is selected as input; when DIFF=1, it is reserved. #01111 10000 When DIFF=0, AD16 is selected as input; when DIFF=1, it is reserved. #10000 10001 When DIFF=0, AD17 is selected as input; when DIFF=1, it is reserved. #10001 10010 When DIFF=0, AD18 is selected as input; when DIFF=1, it is reserved. #10010 10011 When DIFF=0, AD19 is selected as input; when DIFF=1, it is reserved. #10011 10100 When DIFF=0, AD20 is selected as input; when DIFF=1, it is reserved. #10100 10101 When DIFF=0, AD21 is selected as input; when DIFF=1, it is reserved. #10101 10110 When DIFF=0, AD22 is selected as input; when DIFF=1, it is reserved. #10110 10111 When DIFF=0, AD23 is selected as input; when DIFF=1, it is reserved. #10111 11000 Reserved. #11000 11001 Reserved. #11001 11010 When DIFF=0, Temp sensor (single-ended) is selected as input; when DIFF=1, Temp sensor (differential) is selected as input. #11010 11011 When DIFF=0, Bandgap (single-ended) is selected as input; when DIFF=1, Bandgap (differential) is selected as input. #11011 11100 Reserved. #11100 11101 When DIFF=0, VREFSH is selected as input; when DIFF=1, -VREFSH (differential) is selected as input. Voltage reference selected is determined by the REFSEL bits in the SC2 register. #11101 11110 When DIFF=0, VREFSL is selected as input; when DIFF=1, it is reserved. Voltage reference selected is determined by the REFSEL bits in the SC2 register. #11110 11111 Module disabled. #11111 AIEN Interrupt enable 6 1 read-write 0 Conversion complete interrupt disabled. #0 1 Conversion complete interrupt enabled. #1 COCO Conversion complete flag 7 1 read-only 0 Conversion not completed. #0 1 Conversion completed. #1 DIFF Differential mode enable 5 1 read-write 0 Single-ended conversions and input channels are selected. #0 1 Differential conversions and input channels are selected. #1 RESERVED no description available 8 24 read-only SC2 Status and control register 2 0x20 32 read-write n 0x0 0x0 ACFE Compare function enable 5 1 read-write 0 Compare function disabled. #0 1 Compare function enabled. #1 ACFGT Compare function greater than enable 4 1 read-write 0 Configures less than threshold, outside range not inclusive and inside range not inclusive functionality based on the values placed in the CV1 and CV2 registers. #0 1 Configures greater than or equal to threshold, outside range inclusive and inside range inclusive functionality based on the values placed in the CV1 and CV2 registers. #1 ACREN Compare function range enable 3 1 read-write 0 Range function disabled. Only the compare value 1 register (CV1) is compared. #0 1 Range function enabled. Both compare value registers (CV1 and CV2) are compared. #1 ADACT Conversion active 7 1 read-only 0 Conversion not in progress. #0 1 Conversion in progress. #1 ADTRG Conversion trigger select 6 1 read-write 0 Software trigger selected. #0 1 Hardware trigger selected. #1 DMAEN DMA enable 2 1 read-write 0 DMA is disabled. #0 1 DMA is enabled and will assert the ADC DMA request during a ADC conversion complete event noted by the assertion of any of the ADC COCO flags. #1 REFSEL Voltage reference selection 0 2 read-write 00 Default voltage reference pin pair (external pins VREFH and VREFL) #00 01 Alternate reference pair (VALTH and VALTL). This pair may be additional external pins or internal sources depending on MCU configuration. Consult the Chip Configuration information for details specific to this MCU. #01 10 Reserved #10 11 Reserved #11 RESERVED no description available 8 24 read-only SC3 Status and control register 3 0x24 32 read-write n 0x0 0x0 ADCO Continuous conversion enable 3 1 read-write 0 One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. #0 1 Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion. #1 AVGE Hardware average enable 2 1 read-write 0 Hardware average function disabled. #0 1 Hardware average function enabled. #1 AVGS Hardware average select 0 2 read-write 00 4 samples averaged. #00 01 8 samples averaged. #01 10 16 samples averaged. #10 11 32 samples averaged. #11 CAL Calibration 7 1 read-write CALF Calibration failed flag 6 1 read-only 0 Calibration completed normally. #0 1 Calibration failed. ADC accuracy specifications are not guaranteed. #1 RESERVED no description available 4 2 read-only RESERVED no description available 8 24 read-only AIPS0 AIPS-Lite Bridge AIPS 0x0 0x0 0x70 registers n MPRA Master Privilege Register A 0x0 32 read-write n 0x0 0x0 MPL0 Master privilege level 28 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MPL1 Master privilege level 24 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MPL2 Master privilege level 20 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MPL3 Master privilege level 16 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MPL4 Master privilege level 12 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MPL5 Master privilege level 8 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MPL6 Master privilege level 4 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MPL7 Master privilege level 0 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MTR0 Master trusted for read 30 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTR1 Master trusted for read 26 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTR2 Master trusted for read 22 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTR3 Master trusted for read 18 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTR4 Master trusted for read 14 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTR5 Master trusted for read 10 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTR6 Master trusted for read 6 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTR7 Master trusted for read 2 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTW0 Master trusted for writes 29 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTW1 Master trusted for writes 25 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTW2 Master trusted for writes 21 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTW3 Master trusted for writes 17 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTW4 Master trusted for writes 13 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTW5 Master trusted for writes 9 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTW6 Master trusted for writes 5 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTW7 Master trusted for writes 1 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only PACRA Peripheral Access Control Register 0x20 32 read-write n 0x0 0x0 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRB Peripheral Access Control Register 0x24 32 read-write n 0x0 0x0 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRC Peripheral Access Control Register 0x28 32 read-write n 0x0 0x0 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRD Peripheral Access Control Register 0x2C 32 read-write n 0x0 0x0 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRE Peripheral Access Control Register 0x40 32 read-write n 0x0 0x0 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRF Peripheral Access Control Register 0x44 32 read-write n 0x0 0x0 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRG Peripheral Access Control Register 0x48 32 read-write n 0x0 0x0 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRH Peripheral Access Control Register 0x4C 32 read-write n 0x0 0x0 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRI Peripheral Access Control Register 0x50 32 read-write n 0x0 0x0 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRJ Peripheral Access Control Register 0x54 32 read-write n 0x0 0x0 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRK Peripheral Access Control Register 0x58 32 read-write n 0x0 0x0 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRL Peripheral Access Control Register 0x5C 32 read-write n 0x0 0x0 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRM Peripheral Access Control Register 0x60 32 read-write n 0x0 0x0 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRN Peripheral Access Control Register 0x64 32 read-write n 0x0 0x0 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRO Peripheral Access Control Register 0x68 32 read-write n 0x0 0x0 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRP Peripheral Access Control Register 0x6C 32 read-write n 0x0 0x0 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 AIPS1 AIPS-Lite Bridge AIPS 0x0 0x0 0x70 registers n MPRA Master Privilege Register A 0x0 32 read-write n 0x0 0x0 MPL0 Master privilege level 28 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MPL1 Master privilege level 24 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MPL2 Master privilege level 20 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MPL3 Master privilege level 16 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MPL4 Master privilege level 12 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MPL5 Master privilege level 8 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MPL6 Master privilege level 4 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MPL7 Master privilege level 0 1 read-write 0 Accesses from this master are forced to user-mode. #0 1 Accesses from this master are not forced to user-mode. #1 MTR0 Master trusted for read 30 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTR1 Master trusted for read 26 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTR2 Master trusted for read 22 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTR3 Master trusted for read 18 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTR4 Master trusted for read 14 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTR5 Master trusted for read 10 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTR6 Master trusted for read 6 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTR7 Master trusted for read 2 1 read-write 0 This master is not trusted for read accesses. #0 1 This master is trusted for read accesses. #1 MTW0 Master trusted for writes 29 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTW1 Master trusted for writes 25 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTW2 Master trusted for writes 21 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTW3 Master trusted for writes 17 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTW4 Master trusted for writes 13 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTW5 Master trusted for writes 9 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTW6 Master trusted for writes 5 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 MTW7 Master trusted for writes 1 1 read-write 0 This master is not trusted for write accesses. #0 1 This master is trusted for write accesses. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only PACRA Peripheral Access Control Register 0x20 32 read-write n 0x0 0x0 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRB Peripheral Access Control Register 0x24 32 read-write n 0x0 0x0 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRC Peripheral Access Control Register 0x28 32 read-write n 0x0 0x0 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRD Peripheral Access Control Register 0x2C 32 read-write n 0x0 0x0 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRE Peripheral Access Control Register 0x40 32 read-write n 0x0 0x0 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRF Peripheral Access Control Register 0x44 32 read-write n 0x0 0x0 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRG Peripheral Access Control Register 0x48 32 read-write n 0x0 0x0 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRH Peripheral Access Control Register 0x4C 32 read-write n 0x0 0x0 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRI Peripheral Access Control Register 0x50 32 read-write n 0x0 0x0 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRJ Peripheral Access Control Register 0x54 32 read-write n 0x0 0x0 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRK Peripheral Access Control Register 0x58 32 read-write n 0x0 0x0 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRL Peripheral Access Control Register 0x5C 32 read-write n 0x0 0x0 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRM Peripheral Access Control Register 0x60 32 read-write n 0x0 0x0 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRN Peripheral Access Control Register 0x64 32 read-write n 0x0 0x0 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRO Peripheral Access Control Register 0x68 32 read-write n 0x0 0x0 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 PACRP Peripheral Access Control Register 0x6C 32 read-write n 0x0 0x0 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only SP0 Supervisor protect 30 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP1 Supervisor protect 26 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP2 Supervisor protect 22 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP3 Supervisor protect 18 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP4 Supervisor protect 14 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP5 Supervisor protect 10 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP6 Supervisor protect 6 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 SP7 Supervisor protect 2 1 read-write 0 This peripheral does not require supervisor privilege level for accesses. #0 1 This peripheral requires supervisor privilege level for accesses. #1 TP0 Trusted protect 28 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP1 Trusted protect 24 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP2 Trusted protect 20 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP3 Trusted protect 16 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP4 Trusted protect 12 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP5 Trusted protect 8 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP6 Trusted protect 4 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 TP7 Trusted protect 0 1 read-write 0 Accesses from an untrusted master are allowed. #0 1 Accesses from an untrusted master are not allowed. #1 WP0 Write protect 29 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP1 Write protect 25 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP2 Write protect 21 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP3 Write protect 17 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP4 Write protect 13 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP5 Write protect 9 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP6 Write protect 5 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 WP7 Write protect 1 1 read-write 0 This peripheral allows write accesses. #0 1 This peripheral is write protected. #1 AXBS Crossbar switch AXBS 0x0 0x0 0xE04 registers n CRS0 Control Register 0x20 32 read-write n 0x0 0x0 ARB Arbitration Mode 8 2 read-write 00 Fixed priority #00 01 Round-robin, or rotating, priority #01 10 Reserved #10 11 Reserved #11 HLP Halt Low Priority 30 1 read-write 0 The low power mode request has the highest priority for arbitration on this slave port #0 1 The low power mode request has the lowest initial priority for arbitration on this slave port #1 PARK Park 0 3 read-write 000 Park on master port M0 #000 001 Park on master port M1 #001 010 Park on master port M2 #010 011 Park on master port M3 #011 100 Park on master port M4 #100 101 Park on master port M5 #101 110 Park on master port M6 #110 111 Park on master port M7 #111 PCTL Parking Control 4 2 read-write 00 When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field #00 01 When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port #01 10 When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state #10 11 Reserved #11 RESERVED no description available 3 1 read-only RESERVED no description available 6 2 read-only RESERVED no description available 10 20 read-only RO Read Only 31 1 read-write 0 The slave port's registers are writeable #0 1 The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response. #1 CRS1 Control Register 0x130 32 read-write n 0x0 0x0 ARB Arbitration Mode 8 2 read-write 00 Fixed priority #00 01 Round-robin, or rotating, priority #01 10 Reserved #10 11 Reserved #11 HLP Halt Low Priority 30 1 read-write 0 The low power mode request has the highest priority for arbitration on this slave port #0 1 The low power mode request has the lowest initial priority for arbitration on this slave port #1 PARK Park 0 3 read-write 000 Park on master port M0 #000 001 Park on master port M1 #001 010 Park on master port M2 #010 011 Park on master port M3 #011 100 Park on master port M4 #100 101 Park on master port M5 #101 110 Park on master port M6 #110 111 Park on master port M7 #111 PCTL Parking Control 4 2 read-write 00 When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field #00 01 When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port #01 10 When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state #10 11 Reserved #11 RESERVED no description available 3 1 read-only RESERVED no description available 6 2 read-only RESERVED no description available 10 20 read-only RO Read Only 31 1 read-write 0 The slave port's registers are writeable #0 1 The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response. #1 CRS2 Control Register 0x340 32 read-write n 0x0 0x0 ARB Arbitration Mode 8 2 read-write 00 Fixed priority #00 01 Round-robin, or rotating, priority #01 10 Reserved #10 11 Reserved #11 HLP Halt Low Priority 30 1 read-write 0 The low power mode request has the highest priority for arbitration on this slave port #0 1 The low power mode request has the lowest initial priority for arbitration on this slave port #1 PARK Park 0 3 read-write 000 Park on master port M0 #000 001 Park on master port M1 #001 010 Park on master port M2 #010 011 Park on master port M3 #011 100 Park on master port M4 #100 101 Park on master port M5 #101 110 Park on master port M6 #110 111 Park on master port M7 #111 PCTL Parking Control 4 2 read-write 00 When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field #00 01 When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port #01 10 When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state #10 11 Reserved #11 RESERVED no description available 3 1 read-only RESERVED no description available 6 2 read-only RESERVED no description available 10 20 read-only RO Read Only 31 1 read-write 0 The slave port's registers are writeable #0 1 The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response. #1 CRS3 Control Register 0x650 32 read-write n 0x0 0x0 ARB Arbitration Mode 8 2 read-write 00 Fixed priority #00 01 Round-robin, or rotating, priority #01 10 Reserved #10 11 Reserved #11 HLP Halt Low Priority 30 1 read-write 0 The low power mode request has the highest priority for arbitration on this slave port #0 1 The low power mode request has the lowest initial priority for arbitration on this slave port #1 PARK Park 0 3 read-write 000 Park on master port M0 #000 001 Park on master port M1 #001 010 Park on master port M2 #010 011 Park on master port M3 #011 100 Park on master port M4 #100 101 Park on master port M5 #101 110 Park on master port M6 #110 111 Park on master port M7 #111 PCTL Parking Control 4 2 read-write 00 When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field #00 01 When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port #01 10 When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state #10 11 Reserved #11 RESERVED no description available 3 1 read-only RESERVED no description available 6 2 read-only RESERVED no description available 10 20 read-only RO Read Only 31 1 read-write 0 The slave port's registers are writeable #0 1 The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response. #1 CRS4 Control Register 0xA60 32 read-write n 0x0 0x0 ARB Arbitration Mode 8 2 read-write 00 Fixed priority #00 01 Round-robin, or rotating, priority #01 10 Reserved #10 11 Reserved #11 HLP Halt Low Priority 30 1 read-write 0 The low power mode request has the highest priority for arbitration on this slave port #0 1 The low power mode request has the lowest initial priority for arbitration on this slave port #1 PARK Park 0 3 read-write 000 Park on master port M0 #000 001 Park on master port M1 #001 010 Park on master port M2 #010 011 Park on master port M3 #011 100 Park on master port M4 #100 101 Park on master port M5 #101 110 Park on master port M6 #110 111 Park on master port M7 #111 PCTL Parking Control 4 2 read-write 00 When no master makes a request, the arbiter parks the slave port on the master port defined by the PARK field #00 01 When no master makes a request, the arbiter parks the slave port on the last master to be in control of the slave port #01 10 When no master makes a request, the slave port is not parked on a master and the arbiter drives all outputs to a constant safe state #10 11 Reserved #11 RESERVED no description available 3 1 read-only RESERVED no description available 6 2 read-only RESERVED no description available 10 20 read-only RO Read Only 31 1 read-write 0 The slave port's registers are writeable #0 1 The slave port's registers are read-only and cannot be written. Attempted writes have no effect on the registers and result in a bus error response. #1 MGPCR0 Master General Purpose Control Register 0x800 32 read-write n 0x0 0x0 AULB Arbitrates On Undefined Length Bursts 0 3 read-write 000 No arbitration is allowed during an undefined length burst #000 001 Arbitration is allowed at any time during an undefined length burst #001 010 Arbitration is allowed after four beats of an undefined length burst #010 011 Arbitration is allowed after eight beats of an undefined length burst #011 100 Arbitration is allowed after 16 beats of an undefined length burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 RESERVED no description available 3 29 read-only MGPCR1 Master General Purpose Control Register 0x900 32 read-write n 0x0 0x0 AULB Arbitrates On Undefined Length Bursts 0 3 read-write 000 No arbitration is allowed during an undefined length burst #000 001 Arbitration is allowed at any time during an undefined length burst #001 010 Arbitration is allowed after four beats of an undefined length burst #010 011 Arbitration is allowed after eight beats of an undefined length burst #011 100 Arbitration is allowed after 16 beats of an undefined length burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 RESERVED no description available 3 29 read-only MGPCR2 Master General Purpose Control Register 0xA00 32 read-write n 0x0 0x0 AULB Arbitrates On Undefined Length Bursts 0 3 read-write 000 No arbitration is allowed during an undefined length burst #000 001 Arbitration is allowed at any time during an undefined length burst #001 010 Arbitration is allowed after four beats of an undefined length burst #010 011 Arbitration is allowed after eight beats of an undefined length burst #011 100 Arbitration is allowed after 16 beats of an undefined length burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 RESERVED no description available 3 29 read-only MGPCR3 Master General Purpose Control Register 0xB00 32 read-write n 0x0 0x0 AULB Arbitrates On Undefined Length Bursts 0 3 read-write 000 No arbitration is allowed during an undefined length burst #000 001 Arbitration is allowed at any time during an undefined length burst #001 010 Arbitration is allowed after four beats of an undefined length burst #010 011 Arbitration is allowed after eight beats of an undefined length burst #011 100 Arbitration is allowed after 16 beats of an undefined length burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 RESERVED no description available 3 29 read-only MGPCR6 Master General Purpose Control Register 0xE00 32 read-write n 0x0 0x0 AULB Arbitrates On Undefined Length Bursts 0 3 read-write 000 No arbitration is allowed during an undefined length burst #000 001 Arbitration is allowed at any time during an undefined length burst #001 010 Arbitration is allowed after four beats of an undefined length burst #010 011 Arbitration is allowed after eight beats of an undefined length burst #011 100 Arbitration is allowed after 16 beats of an undefined length burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 RESERVED no description available 3 29 read-only PRS0 Priority Registers Slave 0x0 32 read-write n 0x0 0x0 M0 Master 0 Priority. Sets the arbitration priority for this port on the associated slave port. 0 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M1 Master 1 Priority. Sets the arbitration priority for this port on the associated slave port. 4 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M2 Master 2 Priority. Sets the arbitration priority for this port on the associated slave port. 8 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M3 Master 3 Priority. Sets the arbitration priority for this port on the associated slave port. 12 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M4 Master 4 Priority. Sets the arbitration priority for this port on the associated slave port. 16 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M5 Master 5 Priority. Sets the arbitration priority for this port on the associated slave port. 20 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M6 Master 6 Priority. Sets the arbitration priority for this port on the associated slave port. 24 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 28 4 read-only PRS1 Priority Registers Slave 0x100 32 read-write n 0x0 0x0 M0 Master 0 Priority. Sets the arbitration priority for this port on the associated slave port. 0 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M1 Master 1 Priority. Sets the arbitration priority for this port on the associated slave port. 4 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M2 Master 2 Priority. Sets the arbitration priority for this port on the associated slave port. 8 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M3 Master 3 Priority. Sets the arbitration priority for this port on the associated slave port. 12 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M4 Master 4 Priority. Sets the arbitration priority for this port on the associated slave port. 16 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M5 Master 5 Priority. Sets the arbitration priority for this port on the associated slave port. 20 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M6 Master 6 Priority. Sets the arbitration priority for this port on the associated slave port. 24 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 28 4 read-only PRS2 Priority Registers Slave 0x300 32 read-write n 0x0 0x0 M0 Master 0 Priority. Sets the arbitration priority for this port on the associated slave port. 0 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M1 Master 1 Priority. Sets the arbitration priority for this port on the associated slave port. 4 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M2 Master 2 Priority. Sets the arbitration priority for this port on the associated slave port. 8 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M3 Master 3 Priority. Sets the arbitration priority for this port on the associated slave port. 12 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M4 Master 4 Priority. Sets the arbitration priority for this port on the associated slave port. 16 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M5 Master 5 Priority. Sets the arbitration priority for this port on the associated slave port. 20 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M6 Master 6 Priority. Sets the arbitration priority for this port on the associated slave port. 24 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 28 4 read-only PRS3 Priority Registers Slave 0x600 32 read-write n 0x0 0x0 M0 Master 0 Priority. Sets the arbitration priority for this port on the associated slave port. 0 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M1 Master 1 Priority. Sets the arbitration priority for this port on the associated slave port. 4 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M2 Master 2 Priority. Sets the arbitration priority for this port on the associated slave port. 8 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M3 Master 3 Priority. Sets the arbitration priority for this port on the associated slave port. 12 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M4 Master 4 Priority. Sets the arbitration priority for this port on the associated slave port. 16 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M5 Master 5 Priority. Sets the arbitration priority for this port on the associated slave port. 20 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M6 Master 6 Priority. Sets the arbitration priority for this port on the associated slave port. 24 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 28 4 read-only PRS4 Priority Registers Slave 0xA00 32 read-write n 0x0 0x0 M0 Master 0 Priority. Sets the arbitration priority for this port on the associated slave port. 0 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M1 Master 1 Priority. Sets the arbitration priority for this port on the associated slave port. 4 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M2 Master 2 Priority. Sets the arbitration priority for this port on the associated slave port. 8 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M3 Master 3 Priority. Sets the arbitration priority for this port on the associated slave port. 12 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M4 Master 4 Priority. Sets the arbitration priority for this port on the associated slave port. 16 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M5 Master 5 Priority. Sets the arbitration priority for this port on the associated slave port. 20 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 M6 Master 6 Priority. Sets the arbitration priority for this port on the associated slave port. 24 3 read-write 000 This master has level 1, or highest, priority when accessing the slave port. #000 001 This master has level 2 priority when accessing the slave port. #001 010 This master has level 3 priority when accessing the slave port. #010 011 This master has level 4 priority when accessing the slave port. #011 100 This master has level 5 priority when accessing the slave port. #100 101 This master has level 6 priority when accessing the slave port. #101 110 This master has level 7 priority when accessing the slave port. #110 111 This master has level 8, or lowest, priority when accessing the slave port. #111 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 28 4 read-only CAN0 Flex Controller Area Network module CAN 0x0 0x0 0x8C0 registers n CAN0_ORed_Message_buffer 29 CAN0_Bus_Off 30 CAN0_Error 31 CAN0_Tx_Warning 32 CAN0_Rx_Warning 33 CAN0_Wake_Up 34 INT_CAN0_ORed_Message_buffer 45 INT_CAN0_Bus_Off 46 INT_CAN0_Error 47 INT_CAN0_Tx_Warning 48 INT_CAN0_Rx_Warning 49 INT_CAN0_Wake_Up 50 CRCR CRC Register 0x44 32 read-only n 0x0 0x0 MBCRC CRC Mailbox 16 7 read-only RESERVED no description available 15 1 read-only RESERVED no description available 23 9 read-only TXCRC CRC Transmitted 0 15 read-only CS0 Message Buffer 0 CS Register 0x80 32 read-write n 0x0 0x0 CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RESERVED Reserved 23 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS1 Message Buffer 1 CS Register 0x90 32 read-write n 0x0 0x0 CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RESERVED Reserved 23 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS10 Message Buffer 10 CS Register 0x120 32 read-write n 0x0 0x0 CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RESERVED Reserved 23 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS11 Message Buffer 11 CS Register 0x130 32 read-write n 0x0 0x0 CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RESERVED Reserved 23 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS12 Message Buffer 12 CS Register 0x140 32 read-write n 0x0 0x0 CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RESERVED Reserved 23 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS13 Message Buffer 13 CS Register 0x150 32 read-write n 0x0 0x0 CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RESERVED Reserved 23 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS14 Message Buffer 14 CS Register 0x160 32 read-write n 0x0 0x0 CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RESERVED Reserved 23 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS15 Message Buffer 15 CS Register 0x170 32 read-write n 0x0 0x0 CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RESERVED Reserved 23 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS2 Message Buffer 2 CS Register 0xA0 32 read-write n 0x0 0x0 CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RESERVED Reserved 23 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS3 Message Buffer 3 CS Register 0xB0 32 read-write n 0x0 0x0 CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RESERVED Reserved 23 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS4 Message Buffer 4 CS Register 0xC0 32 read-write n 0x0 0x0 CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RESERVED Reserved 23 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS5 Message Buffer 5 CS Register 0xD0 32 read-write n 0x0 0x0 CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RESERVED Reserved 23 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS6 Message Buffer 6 CS Register 0xE0 32 read-write n 0x0 0x0 CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RESERVED Reserved 23 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS7 Message Buffer 7 CS Register 0xF0 32 read-write n 0x0 0x0 CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RESERVED Reserved 23 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS8 Message Buffer 8 CS Register 0x100 32 read-write n 0x0 0x0 CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RESERVED Reserved 23 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS9 Message Buffer 9 CS Register 0x110 32 read-write n 0x0 0x0 CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RESERVED Reserved 23 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CTRL1 Control 1 Register 0x4 32 read-write n 0x0 0x0 BOFFMSK Bus Off Mask 15 1 read-write 0 Bus Off interrupt disabled #0 1 Bus Off interrupt enabled #1 BOFFREC Bus Off Recovery 6 1 read-write 0 Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B #0 1 Automatic recovering from Bus Off state disabled #1 CLKSRC CAN Engine Clock Source 13 1 read-write 0 The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock. #0 1 The CAN engine clock source is the peripheral clock. #1 ERRMSK Error Mask 14 1 read-write 0 Error interrupt disabled #0 1 Error interrupt enabled #1 LBUF Lowest Buffer Transmitted First 4 1 read-write 0 Buffer with highest priority is transmitted first. #0 1 Lowest number buffer is transmitted first. #1 LOM Listen-Only Mode 3 1 read-write 0 Listen-Only Mode is deactivated. #0 1 FlexCAN module operates in Listen-Only Mode. #1 LPB Loop Back Mode 12 1 read-write 0 Loop Back disabled #0 1 Loop Back enabled #1 PRESDIV Prescaler Division Factor 24 8 read-write PROPSEG Propagation Segment 0 3 read-write PSEG1 Phase Segment 1 19 3 read-write PSEG2 Phase Segment 2 16 3 read-write RESERVED no description available 8 2 read-only RJW Resync Jump Width 22 2 read-write RWRNMSK Rx Warning Interrupt Mask 10 1 read-write 0 Rx Warning Interrupt disabled #0 1 Rx Warning Interrupt enabled #1 SMP CAN Bit Sampling 7 1 read-write 0 Just one sample is used to determine the bit value. #0 1 Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples; a majority rule is used. #1 TSYN Timer Sync 5 1 read-write 0 Timer Sync feature disabled #0 1 Timer Sync feature enabled #1 TWRNMSK Tx Warning Interrupt Mask 11 1 read-write 0 Tx Warning Interrupt disabled #0 1 Tx Warning Interrupt enabled #1 CTRL2 Control 2 Register 0x34 32 read-write n 0x0 0x0 EACEN Entire Frame Arbitration Field Comparison Enable for Rx Mailboxes 16 1 read-write 0 Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. #0 1 Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. #1 MRP Mailboxes Reception Priority 18 1 read-write 0 Matching starts from Rx FIFO and continues on Mailboxes. #0 1 Matching starts from Mailboxes and continues on Rx FIFO. #1 RESERVED no description available 0 16 read-only RESERVED no description available 29 2 read-only RESERVED no description available 31 1 write-only RFFN Number of Rx FIFO Filters 24 4 read-write RRS Remote Request Storing 17 1 read-write 0 Remote Response Frame is generated. #0 1 Remote Request Frame is stored. #1 TASD Tx Arbitration Start Delay 19 5 read-write WRMFRZ Write-Access to Memory in Freeze mode 28 1 read-write 0 Maintain the write access restrictions. #0 1 Enable unrestricted write access to FlexCAN memory. #1 ECR Error Counter 0x1C 32 read-write n 0x0 0x0 RESERVED no description available 16 16 read-only RXERRCNT Receive Error Counter 8 8 read-write TXERRCNT Transmit Error Counter 0 8 read-write ESR1 Error and Status 1 Register 0x20 32 read-write n 0x0 0x0 ACKERR Acknowledge Error 13 1 read-only 0 No such occurrence #0 1 An ACK error occurred since last read of this register. #1 BIT0ERR Bit0 Error 14 1 read-only 0 No such occurrence #0 1 At least one bit sent as dominant is received as recessive. #1 BIT1ERR Bit1 Error 15 1 read-only 0 No such occurrence #0 1 At least one bit sent as recessive is received as dominant. #1 BOFFINT 'Bus Off' Interrupt 2 1 read-write 0 No such occurrence #0 1 FlexCAN module entered 'Bus Off' state #1 CRCERR Cyclic Redundancy Check Error 12 1 read-only 0 No such occurrence #0 1 A CRC error occurred since last read of this register. #1 ERRINT Error Interrupt 1 1 read-write 0 No such occurrence #0 1 Indicates setting of any Error Bit in the Error and Status Register #1 FLTCONF Fault Confinement State 4 2 read-only 00 Error Active #00 01 Error Passive #01 1x Bus Off #1x FRMERR Form Error 11 1 read-only 0 No such occurrence #0 1 A Form Error occurred since last read of this register. #1 IDLE no description available 7 1 read-only 0 No such occurrence #0 1 CAN bus is now IDLE. #1 RESERVED no description available 19 13 read-only RWRNINT Rx Warning Interrupt Flag 16 1 read-write 0 No such occurrence #0 1 The Rx error counter transitioned from less than 96 to greater than or equal to 96. #1 RX FlexCAN in Reception 3 1 read-only 0 FlexCAN is not receiving a message. #0 1 FlexCAN is receiving a message. #1 RXWRN Rx Error Warning 8 1 read-only 0 No such occurrence #0 1 RXERRCNT is greater than or equal to 96. #1 STFERR Stuffing Error 10 1 read-only 0 No such occurrence #0 1 A Stuffing Error occurred since last read of this register. #1 SYNCH CAN Synchronization Status 18 1 read-only 0 FlexCAN is not synchronized to the CAN bus. #0 1 FlexCAN is synchronized to the CAN bus. #1 TWRNINT Tx Warning Interrupt Flag 17 1 read-write 0 No such occurrence #0 1 The Tx error counter transitioned from less than 96 to greater than or equal to 96. #1 TX FlexCAN in Transmission 6 1 read-only 0 FlexCAN is not transmitting a message. #0 1 FlexCAN is transmitting a message. #1 TXWRN TX Error Warning 9 1 read-only 0 No such occurrence #0 1 TXERRCNT is greater than or equal to 96. #1 WAKINT Wake-Up Interrupt 0 1 read-write 0 No such occurrence #0 1 Indicates a recessive to dominant transition was received on the CAN bus #1 ESR2 Error and Status 2 Register 0x38 32 read-only n 0x0 0x0 IMB Inactive Mailbox 13 1 read-only 0 If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox. #0 1 If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one. #1 LPTM Lowest Priority Tx Mailbox 16 7 read-only RESERVED no description available 0 13 read-only RESERVED no description available 15 1 read-only RESERVED no description available 23 9 read-only VPS Valid Priority Status 14 1 read-only 0 Contents of IMB and LPTM are invalid. #0 1 Contents of IMB and LPTM are valid. #1 ID0 Message Buffer 0 ID Register 0x84 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID1 Message Buffer 1 ID Register 0x94 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID10 Message Buffer 10 ID Register 0x124 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID11 Message Buffer 11 ID Register 0x134 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID12 Message Buffer 12 ID Register 0x144 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID13 Message Buffer 13 ID Register 0x154 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID14 Message Buffer 14 ID Register 0x164 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID15 Message Buffer 15 ID Register 0x174 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID2 Message Buffer 2 ID Register 0xA4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID3 Message Buffer 3 ID Register 0xB4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID4 Message Buffer 4 ID Register 0xC4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID5 Message Buffer 5 ID Register 0xD4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID6 Message Buffer 6 ID Register 0xE4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID7 Message Buffer 7 ID Register 0xF4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID8 Message Buffer 8 ID Register 0x104 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID9 Message Buffer 9 ID Register 0x114 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write IFLAG1 Interrupt Flags 1 Register 0x30 32 read-write n 0x0 0x0 BUF31TO8I Buffer MBi Interrupt 8 24 read-write 0 The corresponding buffer has no occurrence of successfully completed transmission or reception. #0 1 The corresponding buffer has successfully completed transmission or reception. #1 BUF4TO0I Buffer MBi Interrupt or "reserved" 0 5 read-write 0 The corresponding buffer has no occurrence of successfully completed transmission or reception (when MCR[RFEN]=0). #0 1 The corresponding buffer has successfully completed transmission or reception (when MCR[RFEN]=0). #1 BUF5I Buffer MB5 Interrupt or "Frames available in Rx FIFO" 5 1 read-write 0 No occurrence of MB5 completing transmission/reception (when MCR[RFEN]=0) or of frame(s) available in the Rx FIFO (when MCR[RFEN]=1) #0 1 MB5 completed transmission/reception (when MCR[RFEN]=0) or frame(s) available in the Rx FIFO (when MCR[RFEN]=1) #1 BUF6I Buffer MB6 Interrupt or "Rx FIFO Warning" 6 1 read-write 0 No occurrence of MB6 completing transmission/reception (when MCR[RFEN]=0) or of Rx FIFO almost full (when MCR[RFEN]=1) #0 1 MB6 completed transmission/reception (when MCR[RFEN]=0) or Rx FIFO almost full (when MCR[RFEN]=1) #1 BUF7I Buffer MB7 Interrupt or "Rx FIFO Overflow" 7 1 read-write 0 No occurrence of MB7 completing transmission/reception (when MCR[RFEN]=0) or of Rx FIFO overflow (when MCR[RFEN]=1) #0 1 MB7 completed transmission/reception (when MCR[RFEN]=0) or Rx FIFO overflow (when MCR[RFEN]=1) #1 IFLAG2 Interrupt Flags 2 Register 0x2C 32 read-write n 0x0 0x0 BUFHI Buffer MBi Interrupt 0 32 read-write 0 The corresponding buffer has no occurrence of successfully completed transmission or reception. #0 1 The corresponding buffer has successfully completed transmission or reception. #1 IMASK1 Interrupt Masks 1 Register 0x28 32 read-write n 0x0 0x0 BUFLM Buffer MBi Mask 0 32 read-write 0 The corresponding buffer Interrupt is disabled. #0 1 The corresponding buffer Interrupt is enabled. #1 IMASK2 Interrupt Masks 2 Register 0x24 32 read-write n 0x0 0x0 BUFHM Buffer MBi Mask 0 32 read-write 0 The corresponding buffer Interrupt is disabled. #0 1 The corresponding buffer Interrupt is enabled. #1 MCR Module Configuration Register 0x0 32 read-write n 0x0 0x0 AEN Abort Enable 12 1 read-write 0 Abort disabled #0 1 Abort enabled #1 FRZ Freeze Enable 30 1 read-write 0 Not enabled to enter Freeze Mode #0 1 Enabled to enter Freeze Mode #1 FRZACK Freeze Mode Acknowledge 24 1 read-only 0 FlexCAN not in Freeze Mode, prescaler running #0 1 FlexCAN in Freeze Mode, prescaler stopped #1 HALT Halt FlexCAN 28 1 read-write 0 No Freeze Mode request. #0 1 Enters Freeze Mode if the FRZ bit is asserted. #1 IDAM ID Acceptance Mode 8 2 read-write 00 Format A: One full ID (standard and extended) per ID Filter Table element. #00 01 Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element. #01 10 Format C: Four partial 8-bit Standard IDs per ID Filter Table element. #10 11 Format D: All frames rejected. #11 IRMQ Individual Rx Masking and Queue Enable 16 1 read-write 0 Individual Rx masking and queue feature are disabled. For backward compatibility, the reading of C/S word locks the MB even if it is EMPTY. #0 1 Individual Rx masking and queue feature are enabled. #1 LPMACK Low Power Mode Acknowledge 20 1 read-only 0 FlexCAN is not in a low power mode. #0 1 FlexCAN is in a low power mode. #1 LPRIOEN Local Priority Enable 13 1 read-write 0 Local Priority disabled #0 1 Local Priority enabled #1 MAXMB Number of the Last Message Buffer 0 7 read-write MDIS Module Disable 31 1 read-write 0 Enable the FlexCAN module. #0 1 Disable the FlexCAN module. #1 NOTRDY FlexCAN Not Ready 27 1 read-only 0 FlexCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode. #0 1 FlexCAN module is either in Disable Mode, Stop Mode or Freeze Mode. #1 RESERVED no description available 7 1 read-only RESERVED no description available 10 2 read-only RESERVED no description available 14 2 read-only RESERVED no description available 18 1 read-only RESERVED no description available 19 1 read-only RFEN Rx FIFO Enable 29 1 read-write 0 Rx FIFO not enabled #0 1 Rx FIFO enabled #1 SLFWAK Self Wake Up 22 1 read-write 0 FlexCAN Self Wake Up feature is disabled. #0 1 FlexCAN Self Wake Up feature is enabled. #1 SOFTRST Soft Reset 25 1 read-write 0 No reset request #0 1 Resets the registers affected by soft reset. #1 SRXDIS Self Reception Disable 17 1 read-write 0 Self reception enabled #0 1 Self reception disabled #1 SUPV Supervisor Mode 23 1 read-write 0 FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses. #0 1 FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location. #1 WAKMSK Wake Up Interrupt Mask 26 1 read-write 0 Wake Up Interrupt is disabled. #0 1 Wake Up Interrupt is enabled. #1 WRNEN Warning Interrupt Enable 21 1 read-write 0 TWRNINT and RWRNINT bits are zero, independent of the values in the error counters. #0 1 TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96. #1 RX14MASK Rx 14 Mask Register 0x14 32 read-write n 0x0 0x0 RX14M Rx Buffer 14 Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RX15MASK Rx 15 Mask Register 0x18 32 read-write n 0x0 0x0 RX15M Rx Buffer 15 Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXFGMASK Rx FIFO Global Mask Register 0x48 32 read-write n 0x0 0x0 FGM Rx FIFO Global Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXFIR Rx FIFO Information Register 0x4C 32 read-only n 0x0 0x0 IDHIT Identifier Acceptance Filter Hit Indicator 0 9 read-only RESERVED no description available 9 23 read-only RXIMR0 Rx Individual Mask Registers 0x1100 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR1 Rx Individual Mask Registers 0x1984 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR10 Rx Individual Mask Registers 0x66DC 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR11 Rx Individual Mask Registers 0x6F88 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR12 Rx Individual Mask Registers 0x7838 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR13 Rx Individual Mask Registers 0x80EC 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR14 Rx Individual Mask Registers 0x89A4 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR15 Rx Individual Mask Registers 0x9260 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR2 Rx Individual Mask Registers 0x220C 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR3 Rx Individual Mask Registers 0x2A98 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR4 Rx Individual Mask Registers 0x3328 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR5 Rx Individual Mask Registers 0x3BBC 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR6 Rx Individual Mask Registers 0x4454 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR7 Rx Individual Mask Registers 0x4CF0 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR8 Rx Individual Mask Registers 0x5590 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR9 Rx Individual Mask Registers 0x5E34 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXMGMASK Rx Mailboxes Global Mask Register 0x10 32 read-write n 0x0 0x0 MG Rx Mailboxes Global Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 TIMER Free Running Timer 0x8 32 read-write n 0x0 0x0 RESERVED no description available 16 16 read-only TIMER Timer value 0 16 read-write WORD00 Message Buffer 0 WORD0 Register 0x88 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD01 Message Buffer 1 WORD0 Register 0x98 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD010 Message Buffer 10 WORD0 Register 0x128 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD011 Message Buffer 11 WORD0 Register 0x138 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD012 Message Buffer 12 WORD0 Register 0x148 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD013 Message Buffer 13 WORD0 Register 0x158 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD014 Message Buffer 14 WORD0 Register 0x168 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD015 Message Buffer 15 WORD0 Register 0x178 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD02 Message Buffer 2 WORD0 Register 0xA8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD03 Message Buffer 3 WORD0 Register 0xB8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD04 Message Buffer 4 WORD0 Register 0xC8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD05 Message Buffer 5 WORD0 Register 0xD8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD06 Message Buffer 6 WORD0 Register 0xE8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD07 Message Buffer 7 WORD0 Register 0xF8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD08 Message Buffer 8 WORD0 Register 0x108 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD09 Message Buffer 9 WORD0 Register 0x118 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD10 Message Buffer 0 WORD1 Register 0x8C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD11 Message Buffer 1 WORD1 Register 0x9C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD110 Message Buffer 10 WORD1 Register 0x12C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD111 Message Buffer 11 WORD1 Register 0x13C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD112 Message Buffer 12 WORD1 Register 0x14C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD113 Message Buffer 13 WORD1 Register 0x15C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD114 Message Buffer 14 WORD1 Register 0x16C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD115 Message Buffer 15 WORD1 Register 0x17C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD12 Message Buffer 2 WORD1 Register 0xAC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD13 Message Buffer 3 WORD1 Register 0xBC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD14 Message Buffer 4 WORD1 Register 0xCC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD15 Message Buffer 5 WORD1 Register 0xDC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD16 Message Buffer 6 WORD1 Register 0xEC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD17 Message Buffer 7 WORD1 Register 0xFC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD18 Message Buffer 8 WORD1 Register 0x10C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD19 Message Buffer 9 WORD1 Register 0x11C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write CAN1 Flex Controller Area Network module CAN 0x0 0x0 0x8C0 registers n CAN1_ORed_Message_buffer 37 CAN1_Bus_Off 38 CAN1_Error 39 CAN1_Tx_Warning 40 CAN1_Rx_Warning 41 CAN1_Wake_Up 42 INT_CAN1_ORed_Message_buffer 53 INT_CAN1_Bus_Off 54 INT_CAN1_Error 55 INT_CAN1_Tx_Warning 56 INT_CAN1_Rx_Warning 57 INT_CAN1_Wake_Up 58 CRCR CRC Register 0x44 32 read-only n 0x0 0x0 MBCRC CRC Mailbox 16 7 read-only RESERVED no description available 15 1 read-only RESERVED no description available 23 9 read-only TXCRC CRC Transmitted 0 15 read-only CS0 Message Buffer 0 CS Register 0x80 32 read-write n 0x0 0x0 CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RESERVED Reserved 23 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS1 Message Buffer 1 CS Register 0x90 32 read-write n 0x0 0x0 CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RESERVED Reserved 23 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS10 Message Buffer 10 CS Register 0x120 32 read-write n 0x0 0x0 CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RESERVED Reserved 23 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS11 Message Buffer 11 CS Register 0x130 32 read-write n 0x0 0x0 CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RESERVED Reserved 23 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS12 Message Buffer 12 CS Register 0x140 32 read-write n 0x0 0x0 CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RESERVED Reserved 23 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS13 Message Buffer 13 CS Register 0x150 32 read-write n 0x0 0x0 CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RESERVED Reserved 23 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS14 Message Buffer 14 CS Register 0x160 32 read-write n 0x0 0x0 CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RESERVED Reserved 23 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS15 Message Buffer 15 CS Register 0x170 32 read-write n 0x0 0x0 CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RESERVED Reserved 23 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS2 Message Buffer 2 CS Register 0xA0 32 read-write n 0x0 0x0 CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RESERVED Reserved 23 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS3 Message Buffer 3 CS Register 0xB0 32 read-write n 0x0 0x0 CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RESERVED Reserved 23 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS4 Message Buffer 4 CS Register 0xC0 32 read-write n 0x0 0x0 CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RESERVED Reserved 23 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS5 Message Buffer 5 CS Register 0xD0 32 read-write n 0x0 0x0 CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RESERVED Reserved 23 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS6 Message Buffer 6 CS Register 0xE0 32 read-write n 0x0 0x0 CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RESERVED Reserved 23 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS7 Message Buffer 7 CS Register 0xF0 32 read-write n 0x0 0x0 CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RESERVED Reserved 23 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS8 Message Buffer 8 CS Register 0x100 32 read-write n 0x0 0x0 CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RESERVED Reserved 23 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CS9 Message Buffer 9 CS Register 0x110 32 read-write n 0x0 0x0 CODE Reserved 24 4 read-write DLC Length of the data to be stored/transmitted. 16 4 read-write IDE ID Extended. One/zero for extended/standard format frame. 21 1 read-write RESERVED Reserved 23 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only RTR Remote Transmission Request. One/zero for remote/data frame. 20 1 read-write SRR Substitute Remote Request. Contains a fixed recessive bit. 22 1 read-write TIME_STAMP Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field appears on the CAN bus. 0 16 read-write CTRL1 Control 1 Register 0x4 32 read-write n 0x0 0x0 BOFFMSK Bus Off Mask 15 1 read-write 0 Bus Off interrupt disabled #0 1 Bus Off interrupt enabled #1 BOFFREC Bus Off Recovery 6 1 read-write 0 Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B #0 1 Automatic recovering from Bus Off state disabled #1 CLKSRC CAN Engine Clock Source 13 1 read-write 0 The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock. #0 1 The CAN engine clock source is the peripheral clock. #1 ERRMSK Error Mask 14 1 read-write 0 Error interrupt disabled #0 1 Error interrupt enabled #1 LBUF Lowest Buffer Transmitted First 4 1 read-write 0 Buffer with highest priority is transmitted first. #0 1 Lowest number buffer is transmitted first. #1 LOM Listen-Only Mode 3 1 read-write 0 Listen-Only Mode is deactivated. #0 1 FlexCAN module operates in Listen-Only Mode. #1 LPB Loop Back Mode 12 1 read-write 0 Loop Back disabled #0 1 Loop Back enabled #1 PRESDIV Prescaler Division Factor 24 8 read-write PROPSEG Propagation Segment 0 3 read-write PSEG1 Phase Segment 1 19 3 read-write PSEG2 Phase Segment 2 16 3 read-write RESERVED no description available 8 2 read-only RJW Resync Jump Width 22 2 read-write RWRNMSK Rx Warning Interrupt Mask 10 1 read-write 0 Rx Warning Interrupt disabled #0 1 Rx Warning Interrupt enabled #1 SMP CAN Bit Sampling 7 1 read-write 0 Just one sample is used to determine the bit value. #0 1 Three samples are used to determine the value of the received bit: the regular one (sample point) and 2 preceding samples; a majority rule is used. #1 TSYN Timer Sync 5 1 read-write 0 Timer Sync feature disabled #0 1 Timer Sync feature enabled #1 TWRNMSK Tx Warning Interrupt Mask 11 1 read-write 0 Tx Warning Interrupt disabled #0 1 Tx Warning Interrupt enabled #1 CTRL2 Control 2 Register 0x34 32 read-write n 0x0 0x0 EACEN Entire Frame Arbitration Field Comparison Enable for Rx Mailboxes 16 1 read-write 0 Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits. #0 1 Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within the incoming frame. Mask bits do apply. #1 MRP Mailboxes Reception Priority 18 1 read-write 0 Matching starts from Rx FIFO and continues on Mailboxes. #0 1 Matching starts from Mailboxes and continues on Rx FIFO. #1 RESERVED no description available 0 16 read-only RESERVED no description available 29 2 read-only RESERVED no description available 31 1 write-only RFFN Number of Rx FIFO Filters 24 4 read-write RRS Remote Request Storing 17 1 read-write 0 Remote Response Frame is generated. #0 1 Remote Request Frame is stored. #1 TASD Tx Arbitration Start Delay 19 5 read-write WRMFRZ Write-Access to Memory in Freeze mode 28 1 read-write 0 Maintain the write access restrictions. #0 1 Enable unrestricted write access to FlexCAN memory. #1 ECR Error Counter 0x1C 32 read-write n 0x0 0x0 RESERVED no description available 16 16 read-only RXERRCNT Receive Error Counter 8 8 read-write TXERRCNT Transmit Error Counter 0 8 read-write ESR1 Error and Status 1 Register 0x20 32 read-write n 0x0 0x0 ACKERR Acknowledge Error 13 1 read-only 0 No such occurrence #0 1 An ACK error occurred since last read of this register. #1 BIT0ERR Bit0 Error 14 1 read-only 0 No such occurrence #0 1 At least one bit sent as dominant is received as recessive. #1 BIT1ERR Bit1 Error 15 1 read-only 0 No such occurrence #0 1 At least one bit sent as recessive is received as dominant. #1 BOFFINT 'Bus Off' Interrupt 2 1 read-write 0 No such occurrence #0 1 FlexCAN module entered 'Bus Off' state #1 CRCERR Cyclic Redundancy Check Error 12 1 read-only 0 No such occurrence #0 1 A CRC error occurred since last read of this register. #1 ERRINT Error Interrupt 1 1 read-write 0 No such occurrence #0 1 Indicates setting of any Error Bit in the Error and Status Register #1 FLTCONF Fault Confinement State 4 2 read-only 00 Error Active #00 01 Error Passive #01 1x Bus Off #1x FRMERR Form Error 11 1 read-only 0 No such occurrence #0 1 A Form Error occurred since last read of this register. #1 IDLE no description available 7 1 read-only 0 No such occurrence #0 1 CAN bus is now IDLE. #1 RESERVED no description available 19 13 read-only RWRNINT Rx Warning Interrupt Flag 16 1 read-write 0 No such occurrence #0 1 The Rx error counter transitioned from less than 96 to greater than or equal to 96. #1 RX FlexCAN in Reception 3 1 read-only 0 FlexCAN is not receiving a message. #0 1 FlexCAN is receiving a message. #1 RXWRN Rx Error Warning 8 1 read-only 0 No such occurrence #0 1 RXERRCNT is greater than or equal to 96. #1 STFERR Stuffing Error 10 1 read-only 0 No such occurrence #0 1 A Stuffing Error occurred since last read of this register. #1 SYNCH CAN Synchronization Status 18 1 read-only 0 FlexCAN is not synchronized to the CAN bus. #0 1 FlexCAN is synchronized to the CAN bus. #1 TWRNINT Tx Warning Interrupt Flag 17 1 read-write 0 No such occurrence #0 1 The Tx error counter transitioned from less than 96 to greater than or equal to 96. #1 TX FlexCAN in Transmission 6 1 read-only 0 FlexCAN is not transmitting a message. #0 1 FlexCAN is transmitting a message. #1 TXWRN TX Error Warning 9 1 read-only 0 No such occurrence #0 1 TXERRCNT is greater than or equal to 96. #1 WAKINT Wake-Up Interrupt 0 1 read-write 0 No such occurrence #0 1 Indicates a recessive to dominant transition was received on the CAN bus #1 ESR2 Error and Status 2 Register 0x38 32 read-only n 0x0 0x0 IMB Inactive Mailbox 13 1 read-only 0 If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox. #0 1 If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one. #1 LPTM Lowest Priority Tx Mailbox 16 7 read-only RESERVED no description available 0 13 read-only RESERVED no description available 15 1 read-only RESERVED no description available 23 9 read-only VPS Valid Priority Status 14 1 read-only 0 Contents of IMB and LPTM are invalid. #0 1 Contents of IMB and LPTM are valid. #1 ID0 Message Buffer 0 ID Register 0x84 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID1 Message Buffer 1 ID Register 0x94 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID10 Message Buffer 10 ID Register 0x124 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID11 Message Buffer 11 ID Register 0x134 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID12 Message Buffer 12 ID Register 0x144 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID13 Message Buffer 13 ID Register 0x154 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID14 Message Buffer 14 ID Register 0x164 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID15 Message Buffer 15 ID Register 0x174 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID2 Message Buffer 2 ID Register 0xA4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID3 Message Buffer 3 ID Register 0xB4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID4 Message Buffer 4 ID Register 0xC4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID5 Message Buffer 5 ID Register 0xD4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID6 Message Buffer 6 ID Register 0xE4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID7 Message Buffer 7 ID Register 0xF4 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID8 Message Buffer 8 ID Register 0x104 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write ID9 Message Buffer 9 ID Register 0x114 32 read-write n 0x0 0x0 EXT Contains extended (LOW word) identifier of message buffer. 0 18 read-write PRIO Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular ID to define the transmission priority. 29 3 read-write STD Contains standard/extended (HIGH word) identifier of message buffer. 18 11 read-write IFLAG1 Interrupt Flags 1 Register 0x30 32 read-write n 0x0 0x0 BUF31TO8I Buffer MBi Interrupt 8 24 read-write 0 The corresponding buffer has no occurrence of successfully completed transmission or reception. #0 1 The corresponding buffer has successfully completed transmission or reception. #1 BUF4TO0I Buffer MBi Interrupt or "reserved" 0 5 read-write 0 The corresponding buffer has no occurrence of successfully completed transmission or reception (when MCR[RFEN]=0). #0 1 The corresponding buffer has successfully completed transmission or reception (when MCR[RFEN]=0). #1 BUF5I Buffer MB5 Interrupt or "Frames available in Rx FIFO" 5 1 read-write 0 No occurrence of MB5 completing transmission/reception (when MCR[RFEN]=0) or of frame(s) available in the Rx FIFO (when MCR[RFEN]=1) #0 1 MB5 completed transmission/reception (when MCR[RFEN]=0) or frame(s) available in the Rx FIFO (when MCR[RFEN]=1) #1 BUF6I Buffer MB6 Interrupt or "Rx FIFO Warning" 6 1 read-write 0 No occurrence of MB6 completing transmission/reception (when MCR[RFEN]=0) or of Rx FIFO almost full (when MCR[RFEN]=1) #0 1 MB6 completed transmission/reception (when MCR[RFEN]=0) or Rx FIFO almost full (when MCR[RFEN]=1) #1 BUF7I Buffer MB7 Interrupt or "Rx FIFO Overflow" 7 1 read-write 0 No occurrence of MB7 completing transmission/reception (when MCR[RFEN]=0) or of Rx FIFO overflow (when MCR[RFEN]=1) #0 1 MB7 completed transmission/reception (when MCR[RFEN]=0) or Rx FIFO overflow (when MCR[RFEN]=1) #1 IFLAG2 Interrupt Flags 2 Register 0x2C 32 read-write n 0x0 0x0 BUFHI Buffer MBi Interrupt 0 32 read-write 0 The corresponding buffer has no occurrence of successfully completed transmission or reception. #0 1 The corresponding buffer has successfully completed transmission or reception. #1 IMASK1 Interrupt Masks 1 Register 0x28 32 read-write n 0x0 0x0 BUFLM Buffer MBi Mask 0 32 read-write 0 The corresponding buffer Interrupt is disabled. #0 1 The corresponding buffer Interrupt is enabled. #1 IMASK2 Interrupt Masks 2 Register 0x24 32 read-write n 0x0 0x0 BUFHM Buffer MBi Mask 0 32 read-write 0 The corresponding buffer Interrupt is disabled. #0 1 The corresponding buffer Interrupt is enabled. #1 MCR Module Configuration Register 0x0 32 read-write n 0x0 0x0 AEN Abort Enable 12 1 read-write 0 Abort disabled #0 1 Abort enabled #1 FRZ Freeze Enable 30 1 read-write 0 Not enabled to enter Freeze Mode #0 1 Enabled to enter Freeze Mode #1 FRZACK Freeze Mode Acknowledge 24 1 read-only 0 FlexCAN not in Freeze Mode, prescaler running #0 1 FlexCAN in Freeze Mode, prescaler stopped #1 HALT Halt FlexCAN 28 1 read-write 0 No Freeze Mode request. #0 1 Enters Freeze Mode if the FRZ bit is asserted. #1 IDAM ID Acceptance Mode 8 2 read-write 00 Format A: One full ID (standard and extended) per ID Filter Table element. #00 01 Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element. #01 10 Format C: Four partial 8-bit Standard IDs per ID Filter Table element. #10 11 Format D: All frames rejected. #11 IRMQ Individual Rx Masking and Queue Enable 16 1 read-write 0 Individual Rx masking and queue feature are disabled. For backward compatibility, the reading of C/S word locks the MB even if it is EMPTY. #0 1 Individual Rx masking and queue feature are enabled. #1 LPMACK Low Power Mode Acknowledge 20 1 read-only 0 FlexCAN is not in a low power mode. #0 1 FlexCAN is in a low power mode. #1 LPRIOEN Local Priority Enable 13 1 read-write 0 Local Priority disabled #0 1 Local Priority enabled #1 MAXMB Number of the Last Message Buffer 0 7 read-write MDIS Module Disable 31 1 read-write 0 Enable the FlexCAN module. #0 1 Disable the FlexCAN module. #1 NOTRDY FlexCAN Not Ready 27 1 read-only 0 FlexCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode. #0 1 FlexCAN module is either in Disable Mode, Stop Mode or Freeze Mode. #1 RESERVED no description available 7 1 read-only RESERVED no description available 10 2 read-only RESERVED no description available 14 2 read-only RESERVED no description available 18 1 read-only RESERVED no description available 19 1 read-only RFEN Rx FIFO Enable 29 1 read-write 0 Rx FIFO not enabled #0 1 Rx FIFO enabled #1 SLFWAK Self Wake Up 22 1 read-write 0 FlexCAN Self Wake Up feature is disabled. #0 1 FlexCAN Self Wake Up feature is enabled. #1 SOFTRST Soft Reset 25 1 read-write 0 No reset request #0 1 Resets the registers affected by soft reset. #1 SRXDIS Self Reception Disable 17 1 read-write 0 Self reception enabled #0 1 Self reception disabled #1 SUPV Supervisor Mode 23 1 read-write 0 FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses. #0 1 FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented register location. #1 WAKMSK Wake Up Interrupt Mask 26 1 read-write 0 Wake Up Interrupt is disabled. #0 1 Wake Up Interrupt is enabled. #1 WRNEN Warning Interrupt Enable 21 1 read-write 0 TWRNINT and RWRNINT bits are zero, independent of the values in the error counters. #0 1 TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96. #1 RX14MASK Rx 14 Mask Register 0x14 32 read-write n 0x0 0x0 RX14M Rx Buffer 14 Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RX15MASK Rx 15 Mask Register 0x18 32 read-write n 0x0 0x0 RX15M Rx Buffer 15 Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXFGMASK Rx FIFO Global Mask Register 0x48 32 read-write n 0x0 0x0 FGM Rx FIFO Global Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXFIR Rx FIFO Information Register 0x4C 32 read-only n 0x0 0x0 IDHIT Identifier Acceptance Filter Hit Indicator 0 9 read-only RESERVED no description available 9 23 read-only RXIMR0 Rx Individual Mask Registers 0x1100 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR1 Rx Individual Mask Registers 0x1984 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR10 Rx Individual Mask Registers 0x66DC 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR11 Rx Individual Mask Registers 0x6F88 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR12 Rx Individual Mask Registers 0x7838 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR13 Rx Individual Mask Registers 0x80EC 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR14 Rx Individual Mask Registers 0x89A4 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR15 Rx Individual Mask Registers 0x9260 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR2 Rx Individual Mask Registers 0x220C 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR3 Rx Individual Mask Registers 0x2A98 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR4 Rx Individual Mask Registers 0x3328 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR5 Rx Individual Mask Registers 0x3BBC 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR6 Rx Individual Mask Registers 0x4454 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR7 Rx Individual Mask Registers 0x4CF0 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR8 Rx Individual Mask Registers 0x5590 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXIMR9 Rx Individual Mask Registers 0x5E34 32 read-write n 0x0 0x0 MI Individual Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 RXMGMASK Rx Mailboxes Global Mask Register 0x10 32 read-write n 0x0 0x0 MG Rx Mailboxes Global Mask Bits 0 32 read-write 0 The corresponding bit in the filter is "don't care." #0 1 The corresponding bit in the filter is checked. #1 TIMER Free Running Timer 0x8 32 read-write n 0x0 0x0 RESERVED no description available 16 16 read-only TIMER Timer value 0 16 read-write WORD00 Message Buffer 0 WORD0 Register 0x88 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD01 Message Buffer 1 WORD0 Register 0x98 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD010 Message Buffer 10 WORD0 Register 0x128 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD011 Message Buffer 11 WORD0 Register 0x138 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD012 Message Buffer 12 WORD0 Register 0x148 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD013 Message Buffer 13 WORD0 Register 0x158 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD014 Message Buffer 14 WORD0 Register 0x168 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD015 Message Buffer 15 WORD0 Register 0x178 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD02 Message Buffer 2 WORD0 Register 0xA8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD03 Message Buffer 3 WORD0 Register 0xB8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD04 Message Buffer 4 WORD0 Register 0xC8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD05 Message Buffer 5 WORD0 Register 0xD8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD06 Message Buffer 6 WORD0 Register 0xE8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD07 Message Buffer 7 WORD0 Register 0xF8 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD08 Message Buffer 8 WORD0 Register 0x108 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD09 Message Buffer 9 WORD0 Register 0x118 32 read-write n 0x0 0x0 DATA_BYTE_0 Data byte 0 of Rx/Tx frame. 24 8 read-write DATA_BYTE_1 Data byte 1 of Rx/Tx frame. 16 8 read-write DATA_BYTE_2 Data byte 2 of Rx/Tx frame. 8 8 read-write DATA_BYTE_3 Data byte 3 of Rx/Tx frame. 0 8 read-write WORD10 Message Buffer 0 WORD1 Register 0x8C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD11 Message Buffer 1 WORD1 Register 0x9C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD110 Message Buffer 10 WORD1 Register 0x12C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD111 Message Buffer 11 WORD1 Register 0x13C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD112 Message Buffer 12 WORD1 Register 0x14C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD113 Message Buffer 13 WORD1 Register 0x15C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD114 Message Buffer 14 WORD1 Register 0x16C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD115 Message Buffer 15 WORD1 Register 0x17C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD12 Message Buffer 2 WORD1 Register 0xAC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD13 Message Buffer 3 WORD1 Register 0xBC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD14 Message Buffer 4 WORD1 Register 0xCC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD15 Message Buffer 5 WORD1 Register 0xDC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD16 Message Buffer 6 WORD1 Register 0xEC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD17 Message Buffer 7 WORD1 Register 0xFC 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD18 Message Buffer 8 WORD1 Register 0x10C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write WORD19 Message Buffer 9 WORD1 Register 0x11C 32 read-write n 0x0 0x0 DATA_BYTE_4 Data byte 4 of Rx/Tx frame. 24 8 read-write DATA_BYTE_5 Data byte 5 of Rx/Tx frame. 16 8 read-write DATA_BYTE_6 Data byte 6 of Rx/Tx frame. 8 8 read-write DATA_BYTE_7 Data byte 7 of Rx/Tx frame. 0 8 read-write CMP0 High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) CMP 0x0 0x0 0x6 registers n CMP0 59 INT_CMP0 75 CR0 CMP Control Register 0 0x0 8 read-write n 0x0 0x0 FILTER_CNT Filter Sample Count 4 3 read-write 000 Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA. #000 001 1 consecutive sample must agree (comparator output is simply sampled). #001 010 2 consecutive samples must agree. #010 011 3 consecutive samples must agree. #011 100 4 consecutive samples must agree. #100 101 5 consecutive samples must agree. #101 110 6 consecutive samples must agree. #110 111 7 consecutive samples must agree. #111 HYSTCTR Comparator hard block hysteresis control 0 2 read-write 00 Level 0 #00 01 Level 1 #01 10 Level 2 #10 11 Level 3 #11 RESERVED no description available 2 1 read-only RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only CR1 CMP Control Register 1 0x1 8 read-write n 0x0 0x0 COS Comparator Output Select 2 1 read-write 0 Set CMPO to equal COUT (filtered comparator output). #0 1 Set CMPO to equal COUTA (unfiltered comparator output). #1 EN Comparator Module Enable 0 1 read-write 0 Analog Comparator disabled. #0 1 Analog Comparator enabled. #1 INV Comparator INVERT 3 1 read-write 0 Does not invert the comparator output. #0 1 Inverts the comparator output. #1 OPE Comparator Output Pin Enable 1 1 read-write 0 The comparator output (CMPO) is not available on the associated CMPO output pin. #0 1 The comparator output (CMPO) is available on the associated CMPO output pin. #1 PMODE Power Mode Select 4 1 read-write 0 Low Speed (LS) comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. #0 1 High Speed (HS) comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. #1 RESERVED no description available 5 1 read-only SE Sample Enable 7 1 read-write 0 Sampling mode not selected. #0 1 Sampling mode selected. #1 WE Windowing Enable 6 1 read-write 0 Windowing mode not selected. #0 1 Windowing mode selected. #1 DACCR DAC Control Register 0x4 8 read-write n 0x0 0x0 DACEN DAC Enable 7 1 read-write 0 DAC is disabled. #0 1 DAC is enabled. #1 VOSEL DAC Output Voltage Select 0 6 read-write VRSEL Supply Voltage Reference Source Select 6 1 read-write 0 Vin1 is selected as resistor ladder network supply reference Vin. #0 1 Vin2 is selected as resistor ladder network supply reference Vin. #1 FPR CMP Filter Period Register 0x2 8 read-write n 0x0 0x0 FILT_PER Filter Sample Period 0 8 read-write MUXCR MUX Control Register 0x5 8 read-write n 0x0 0x0 MSEL Minus Input MUX Control 0 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 PSEL Plus Input MUX Control 3 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 RESERVED no description available 6 2 read-only SCR CMP Status and Control Register 0x3 8 read-write n 0x0 0x0 CFF Analog Comparator Flag Falling 1 1 read-write 0 Falling edge on COUT has not been detected. #0 1 Falling edge on COUT has occurred. #1 CFR Analog Comparator Flag Rising 2 1 read-write 0 Rising edge on COUT has not been detected. #0 1 Rising edge on COUT has occurred. #1 COUT Analog Comparator Output 0 1 read-only DMAEN DMA Enable Control 6 1 read-write 0 DMA disabled. #0 1 DMA enabled. #1 IEF Comparator Interrupt Enable Falling 3 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 IER Comparator Interrupt Enable Rising 4 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 RESERVED no description available 5 1 read-only RESERVED no description available 7 1 read-only CMP1 High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) CMP 0x0 0x0 0x6 registers n CMP1 60 INT_CMP1 76 CR0 CMP Control Register 0 0x0 8 read-write n 0x0 0x0 FILTER_CNT Filter Sample Count 4 3 read-write 000 Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA. #000 001 1 consecutive sample must agree (comparator output is simply sampled). #001 010 2 consecutive samples must agree. #010 011 3 consecutive samples must agree. #011 100 4 consecutive samples must agree. #100 101 5 consecutive samples must agree. #101 110 6 consecutive samples must agree. #110 111 7 consecutive samples must agree. #111 HYSTCTR Comparator hard block hysteresis control 0 2 read-write 00 Level 0 #00 01 Level 1 #01 10 Level 2 #10 11 Level 3 #11 RESERVED no description available 2 1 read-only RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only CR1 CMP Control Register 1 0x1 8 read-write n 0x0 0x0 COS Comparator Output Select 2 1 read-write 0 Set CMPO to equal COUT (filtered comparator output). #0 1 Set CMPO to equal COUTA (unfiltered comparator output). #1 EN Comparator Module Enable 0 1 read-write 0 Analog Comparator disabled. #0 1 Analog Comparator enabled. #1 INV Comparator INVERT 3 1 read-write 0 Does not invert the comparator output. #0 1 Inverts the comparator output. #1 OPE Comparator Output Pin Enable 1 1 read-write 0 The comparator output (CMPO) is not available on the associated CMPO output pin. #0 1 The comparator output (CMPO) is available on the associated CMPO output pin. #1 PMODE Power Mode Select 4 1 read-write 0 Low Speed (LS) comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. #0 1 High Speed (HS) comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. #1 RESERVED no description available 5 1 read-only SE Sample Enable 7 1 read-write 0 Sampling mode not selected. #0 1 Sampling mode selected. #1 WE Windowing Enable 6 1 read-write 0 Windowing mode not selected. #0 1 Windowing mode selected. #1 DACCR DAC Control Register 0x4 8 read-write n 0x0 0x0 DACEN DAC Enable 7 1 read-write 0 DAC is disabled. #0 1 DAC is enabled. #1 VOSEL DAC Output Voltage Select 0 6 read-write VRSEL Supply Voltage Reference Source Select 6 1 read-write 0 Vin1 is selected as resistor ladder network supply reference Vin. #0 1 Vin2 is selected as resistor ladder network supply reference Vin. #1 FPR CMP Filter Period Register 0x2 8 read-write n 0x0 0x0 FILT_PER Filter Sample Period 0 8 read-write MUXCR MUX Control Register 0x5 8 read-write n 0x0 0x0 MSEL Minus Input MUX Control 0 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 PSEL Plus Input MUX Control 3 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 RESERVED no description available 6 2 read-only SCR CMP Status and Control Register 0x3 8 read-write n 0x0 0x0 CFF Analog Comparator Flag Falling 1 1 read-write 0 Falling edge on COUT has not been detected. #0 1 Falling edge on COUT has occurred. #1 CFR Analog Comparator Flag Rising 2 1 read-write 0 Rising edge on COUT has not been detected. #0 1 Rising edge on COUT has occurred. #1 COUT Analog Comparator Output 0 1 read-only DMAEN DMA Enable Control 6 1 read-write 0 DMA disabled. #0 1 DMA enabled. #1 IEF Comparator Interrupt Enable Falling 3 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 IER Comparator Interrupt Enable Rising 4 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 RESERVED no description available 5 1 read-only RESERVED no description available 7 1 read-only CMP2 High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) CMP 0x0 0x0 0x6 registers n CMP2 61 INT_CMP2 77 CR0 CMP Control Register 0 0x0 8 read-write n 0x0 0x0 FILTER_CNT Filter Sample Count 4 3 read-write 000 Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA. #000 001 1 consecutive sample must agree (comparator output is simply sampled). #001 010 2 consecutive samples must agree. #010 011 3 consecutive samples must agree. #011 100 4 consecutive samples must agree. #100 101 5 consecutive samples must agree. #101 110 6 consecutive samples must agree. #110 111 7 consecutive samples must agree. #111 HYSTCTR Comparator hard block hysteresis control 0 2 read-write 00 Level 0 #00 01 Level 1 #01 10 Level 2 #10 11 Level 3 #11 RESERVED no description available 2 1 read-only RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only CR1 CMP Control Register 1 0x1 8 read-write n 0x0 0x0 COS Comparator Output Select 2 1 read-write 0 Set CMPO to equal COUT (filtered comparator output). #0 1 Set CMPO to equal COUTA (unfiltered comparator output). #1 EN Comparator Module Enable 0 1 read-write 0 Analog Comparator disabled. #0 1 Analog Comparator enabled. #1 INV Comparator INVERT 3 1 read-write 0 Does not invert the comparator output. #0 1 Inverts the comparator output. #1 OPE Comparator Output Pin Enable 1 1 read-write 0 The comparator output (CMPO) is not available on the associated CMPO output pin. #0 1 The comparator output (CMPO) is available on the associated CMPO output pin. #1 PMODE Power Mode Select 4 1 read-write 0 Low Speed (LS) comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. #0 1 High Speed (HS) comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. #1 RESERVED no description available 5 1 read-only SE Sample Enable 7 1 read-write 0 Sampling mode not selected. #0 1 Sampling mode selected. #1 WE Windowing Enable 6 1 read-write 0 Windowing mode not selected. #0 1 Windowing mode selected. #1 DACCR DAC Control Register 0x4 8 read-write n 0x0 0x0 DACEN DAC Enable 7 1 read-write 0 DAC is disabled. #0 1 DAC is enabled. #1 VOSEL DAC Output Voltage Select 0 6 read-write VRSEL Supply Voltage Reference Source Select 6 1 read-write 0 Vin1 is selected as resistor ladder network supply reference Vin. #0 1 Vin2 is selected as resistor ladder network supply reference Vin. #1 FPR CMP Filter Period Register 0x2 8 read-write n 0x0 0x0 FILT_PER Filter Sample Period 0 8 read-write MUXCR MUX Control Register 0x5 8 read-write n 0x0 0x0 MSEL Minus Input MUX Control 0 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 PSEL Plus Input MUX Control 3 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 RESERVED no description available 6 2 read-only SCR CMP Status and Control Register 0x3 8 read-write n 0x0 0x0 CFF Analog Comparator Flag Falling 1 1 read-write 0 Falling edge on COUT has not been detected. #0 1 Falling edge on COUT has occurred. #1 CFR Analog Comparator Flag Rising 2 1 read-write 0 Rising edge on COUT has not been detected. #0 1 Rising edge on COUT has occurred. #1 COUT Analog Comparator Output 0 1 read-only DMAEN DMA Enable Control 6 1 read-write 0 DMA disabled. #0 1 DMA enabled. #1 IEF Comparator Interrupt Enable Falling 3 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 IER Comparator Interrupt Enable Rising 4 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 RESERVED no description available 5 1 read-only RESERVED no description available 7 1 read-only CMP3 High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX) CMP 0x0 0x0 0x6 registers n CMP3 98 INT_CMP3 114 CR0 CMP Control Register 0 0x0 8 read-write n 0x0 0x0 FILTER_CNT Filter Sample Count 4 3 read-write 000 Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA. #000 001 1 consecutive sample must agree (comparator output is simply sampled). #001 010 2 consecutive samples must agree. #010 011 3 consecutive samples must agree. #011 100 4 consecutive samples must agree. #100 101 5 consecutive samples must agree. #101 110 6 consecutive samples must agree. #110 111 7 consecutive samples must agree. #111 HYSTCTR Comparator hard block hysteresis control 0 2 read-write 00 Level 0 #00 01 Level 1 #01 10 Level 2 #10 11 Level 3 #11 RESERVED no description available 2 1 read-only RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only CR1 CMP Control Register 1 0x1 8 read-write n 0x0 0x0 COS Comparator Output Select 2 1 read-write 0 Set CMPO to equal COUT (filtered comparator output). #0 1 Set CMPO to equal COUTA (unfiltered comparator output). #1 EN Comparator Module Enable 0 1 read-write 0 Analog Comparator disabled. #0 1 Analog Comparator enabled. #1 INV Comparator INVERT 3 1 read-write 0 Does not invert the comparator output. #0 1 Inverts the comparator output. #1 OPE Comparator Output Pin Enable 1 1 read-write 0 The comparator output (CMPO) is not available on the associated CMPO output pin. #0 1 The comparator output (CMPO) is available on the associated CMPO output pin. #1 PMODE Power Mode Select 4 1 read-write 0 Low Speed (LS) comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption. #0 1 High Speed (HS) comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption. #1 RESERVED no description available 5 1 read-only SE Sample Enable 7 1 read-write 0 Sampling mode not selected. #0 1 Sampling mode selected. #1 WE Windowing Enable 6 1 read-write 0 Windowing mode not selected. #0 1 Windowing mode selected. #1 DACCR DAC Control Register 0x4 8 read-write n 0x0 0x0 DACEN DAC Enable 7 1 read-write 0 DAC is disabled. #0 1 DAC is enabled. #1 VOSEL DAC Output Voltage Select 0 6 read-write VRSEL Supply Voltage Reference Source Select 6 1 read-write 0 Vin1 is selected as resistor ladder network supply reference Vin. #0 1 Vin2 is selected as resistor ladder network supply reference Vin. #1 FPR CMP Filter Period Register 0x2 8 read-write n 0x0 0x0 FILT_PER Filter Sample Period 0 8 read-write MUXCR MUX Control Register 0x5 8 read-write n 0x0 0x0 MSEL Minus Input MUX Control 0 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 PSEL Plus Input MUX Control 3 3 read-write 000 IN0 #000 001 IN1 #001 010 IN2 #010 011 IN3 #011 100 IN4 #100 101 IN5 #101 110 IN6 #110 111 IN7 #111 RESERVED no description available 6 2 read-only SCR CMP Status and Control Register 0x3 8 read-write n 0x0 0x0 CFF Analog Comparator Flag Falling 1 1 read-write 0 Falling edge on COUT has not been detected. #0 1 Falling edge on COUT has occurred. #1 CFR Analog Comparator Flag Rising 2 1 read-write 0 Rising edge on COUT has not been detected. #0 1 Rising edge on COUT has occurred. #1 COUT Analog Comparator Output 0 1 read-only DMAEN DMA Enable Control 6 1 read-write 0 DMA disabled. #0 1 DMA enabled. #1 IEF Comparator Interrupt Enable Falling 3 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 IER Comparator Interrupt Enable Rising 4 1 read-write 0 Interrupt disabled. #0 1 Interrupt enabled. #1 RESERVED no description available 5 1 read-only RESERVED no description available 7 1 read-only CMT Carrier Modulator Transmitter CMT 0x0 0x0 0xC registers n CMT 65 INT_CMT 81 CGH1 CMT Carrier Generator High Data Register 1 0x0 8 read-write n 0x0 0x0 PH Primary Carrier High Time Data Value 0 8 read-write CGH2 CMT Carrier Generator High Data Register 2 0x2 8 read-write n 0x0 0x0 SH Secondary Carrier High Time Data Value 0 8 read-write CGL1 CMT Carrier Generator Low Data Register 1 0x1 8 read-write n 0x0 0x0 PL Primary Carrier Low Time Data Value 0 8 read-write CGL2 CMT Carrier Generator Low Data Register 2 0x3 8 read-write n 0x0 0x0 SL Secondary Carrier Low Time Data Value 0 8 read-write CMD1 CMT Modulator Data Register Mark High 0x6 8 read-write n 0x0 0x0 MB no description available 0 8 read-write CMD2 CMT Modulator Data Register Mark Low 0x7 8 read-write n 0x0 0x0 MB no description available 0 8 read-write CMD3 CMT Modulator Data Register Space High 0x8 8 read-write n 0x0 0x0 SB no description available 0 8 read-write CMD4 CMT Modulator Data Register Space Low 0x9 8 read-write n 0x0 0x0 SB no description available 0 8 read-write DMA CMT Direct Memory Access 0xB 8 read-write n 0x0 0x0 DMA DMA Enable 0 1 read-write 0 DMA transfer request and done are disabled #0 1 DMA transfer request and done are enabled #1 RESERVED no description available 1 7 read-only MSC CMT Modulator Status and Control Register 0x5 8 read-write n 0x0 0x0 BASE Baseband Enable 3 1 read-write 0 Baseband mode disabled #0 1 Baseband mode enabled #1 CMTDIV CMT Clock Divide Prescaler 5 2 read-write 00 IF * 1 #00 01 IF * 2 #01 10 IF * 4 #10 11 IF * 8 #11 EOCF End Of Cycle Status Flag 7 1 read-only 0 No end of modulation cycle occurrence since flag last cleared #0 1 End of modulator cycle has occurred #1 EOCIE End of Cycle Interrupt Enable 1 1 read-write 0 CPU interrupt disabled #0 1 CPU interrupt enabled #1 EXSPC Extended Space Enable 4 1 read-write 0 Extended space disabled #0 1 Extended space enabled #1 FSK FSK Mode Select 2 1 read-write 0 CMT operates in Time or Baseband mode #0 1 CMT operates in FSK mode #1 MCGEN Modulator and Carrier Generator Enable 0 1 read-write 0 Modulator and carrier generator disabled #0 1 Modulator and carrier generator enabled #1 OC CMT Output Control Register 0x4 8 read-write n 0x0 0x0 CMTPOL CMT Output Polarity 6 1 read-write 0 CMT_IRO signal is active low #0 1 CMT_IRO signal is active high #1 IROL IRO Latch Control 7 1 read-write IROPEN IRO Pin Enable 5 1 read-write 0 CMT_IRO signal disabled #0 1 CMT_IRO signal enabled as output #1 RESERVED no description available 0 5 read-only PPS CMT Primary Prescaler Register 0xA 8 read-write n 0x0 0x0 PPSDIV Primary Prescaler Divider 0 4 read-write 0000 Bus Clock * 1 #0000 0001 Bus Clock * 2 #0001 0010 Bus Clock * 3 #0010 0011 Bus Clock * 4 #0011 0100 Bus Clock * 5 #0100 0101 Bus Clock * 6 #0101 0110 Bus Clock * 7 #0110 0111 Bus Clock * 8 #0111 1000 Bus Clock * 9 #1000 1001 Bus Clock * 10 #1001 1010 Bus Clock * 11 #1010 1011 Bus Clock * 12 #1011 1100 Bus Clock * 13 #1100 1101 Bus Clock * 14 #1101 1110 Bus Clock * 15 #1110 1111 Bus Clock * 16 #1111 RESERVED no description available 4 4 read-only CRC Cyclic Redundancy Check CRC 0x0 0x0 0xC registers n CRC CRC Data Register CRC 0x0 32 read-write n 0x0 0x0 HL CRC High Lower Byte 16 8 read-write HU CRC High Upper Byte 24 8 read-write LL CRC Low Lower Byte 0 8 read-write LU CRC Low Upper Byte 8 8 read-write CRCH CRC_CRCH register. CRC 0x2 16 read-write n 0x0 0x0 CRCH CRCH stores the high 16 bits of the 16/32 bit CRC 0 16 read-write CRCHL CRC_CRCHL register. CRC 0x2 8 read-write n 0x0 0x0 CRCHL CRCHL stores the third 8 bits of the 32 bit CRC 0 8 read-write CRCHU CRC_CRCHU register. 0x3 8 read-write n 0x0 0x0 CRCHU CRCHU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write CRCL CRC_CRCL register. CRC 0x0 16 read-write n 0x0 0x0 CRCL CRCL stores the lower 16 bits of the 16/32 bit CRC 0 16 read-write CRCLL CRC_CRCLL register. CRC 0x0 8 read-write n 0x0 0x0 CRCLL CRCLL stores the first 8 bits of the 32 bit CRC 0 8 read-write CRCLU CRC_CRCLU register. 0x1 8 read-write n 0x0 0x0 CRCLU CRCLL stores the second 8 bits of the 32 bit CRC 0 8 read-write CTRL CRC Control Register 0x8 32 read-write n 0x0 0x0 FXOR Complement Read of CRC data register 26 1 read-write 0 No XOR on reading. #0 1 Invert or complement the read value of the CRC data register. #1 RESERVED no description available 0 24 read-only RESERVED no description available 27 1 read-only TCRC no description available 24 1 read-write 0 16-bit CRC protocol. #0 1 32-bit CRC protocol. #1 TOT Type of Transpose for Writes 30 2 read-write 00 No transposition. #00 01 Bits in bytes are transposed; bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 TOTR Type of Transpose for Read 28 2 read-write 00 No transposition. #00 01 Bits in bytes are transposed; bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 WAS Write CRC data register as seed 25 1 read-write 0 Writes to the CRC data register are data values. #0 1 Writes to the CRC data register are seed values. #1 CTRLHU CRC_CTRLHU register. 0xB 8 read-write n 0x0 0x0 FXOR no description available 2 1 read-write 0 No XOR on reading. #0 1 Invert or complement the read value of CRC data register. #1 RESERVED no description available 3 1 read-only TCRC no description available 0 1 read-write 0 16-bit CRC protocol. #0 1 32-bit CRC protocol. #1 TOT no description available 6 2 read-write 00 No Transposition. #00 01 Bits in bytes are transposed, bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 TOTR no description available 4 2 read-write 00 No Transposition. #00 01 Bits in bytes are transposed, bytes are not transposed. #01 10 Both bits in bytes and bytes are transposed. #10 11 Only bytes are transposed; no bits in a byte are transposed. #11 WAS no description available 1 1 read-write 0 Writes to CRC data register are data values. #0 1 Writes to CRC data reguster are seed values. #1 GPOLY CRC Polynomial Register CRC 0x4 32 read-write n 0x0 0x0 HIGH High polynominal half-word 16 16 read-write LOW Low polynominal half-word 0 16 read-write GPOLYH CRC_GPOLYH register. CRC 0x6 16 read-write n 0x0 0x0 GPOLYH POLYH stores the high 16 bits of the 16/32 bit CRC polynomial value 0 16 read-write GPOLYHL CRC_GPOLYHL register. CRC 0x6 8 read-write n 0x0 0x0 GPOLYHL POLYHL stores the third 8 bits of the 32 bit CRC 0 8 read-write GPOLYHU CRC_GPOLYHU register. 0x7 8 read-write n 0x0 0x0 GPOLYHU POLYHU stores the fourth 8 bits of the 32 bit CRC 0 8 read-write GPOLYL CRC_GPOLYL register. CRC 0x4 16 read-write n 0x0 0x0 GPOLYL POLYL stores the lower 16 bits of the 16/32 bit CRC polynomial value 0 16 read-write GPOLYLL CRC_GPOLYLL register. CRC 0x4 8 read-write n 0x0 0x0 GPOLYLL POLYLL stores the first 8 bits of the 32 bit CRC 0 8 read-write GPOLYLU CRC_GPOLYLU register. 0x5 8 read-write n 0x0 0x0 GPOLYLU POLYLL stores the second 8 bits of the 32 bit CRC 0 8 read-write DAC0 12-Bit Digital-to-Analog Converter DAC 0x0 0x0 0x24 registers n DAC0 81 INT_DAC0 97 C0 DAC Control Register 0x21 8 read-write n 0x0 0x0 DACBBIEN DAC buffer read pointer bottom flag interrupt enable 0 1 read-write 0 The DAC buffer read pointer bottom flag interrupt is disabled. #0 1 The DAC buffer read pointer bottom flag interrupt is enabled. #1 DACBTIEN DAC buffer read pointer top flag interrupt enable 1 1 read-write 0 The DAC buffer read pointer top flag interrupt is disabled. #0 1 The DAC buffer read pointer top flag interrupt is enabled. #1 DACBWIEN DAC buffer watermark interrupt enable 2 1 read-write 0 The DAC buffer watermark interrupt is disabled. #0 1 The DAC buffer watermark interrupt is enabled. #1 DACEN DAC enable 7 1 read-write 0 The DAC system is disabled. #0 1 The DAC system is enabled. #1 DACRFS DAC Reference Select 6 1 read-write 0 The DAC selets DACREF_1 as the reference voltage. #0 1 The DAC selets DACREF_2 as the reference voltage. #1 DACSWTRG DAC software trigger 4 1 write-only 0 The DAC soft trigger is not valid. #0 1 The DAC soft trigger is valid. #1 DACTRGSEL DAC trigger select 5 1 read-write 0 The DAC hardware trigger is selected. #0 1 The DAC software trigger is selected. #1 LPEN DAC low power control 3 1 read-write 0 high power mode. #0 1 low power mode. #1 C1 DAC Control Register 1 0x22 8 read-write n 0x0 0x0 DACBFEN DAC buffer enable 0 1 read-write 0 Buffer read pointer disabled. The converted data is always the first word of the buffer. #0 1 Buffer read pointer enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer. #1 DACBFMD DAC buffer work mode select 1 2 read-write 00 Normal Mode #00 01 Swing Mode #01 10 One-Time Scan Mode #10 11 Reserved #11 DACBFWM DAC buffer watermark select 3 2 read-write 00 1 word #00 01 2 words #01 10 3 words #10 11 4 words #11 DMAEN DMA enable select 7 1 read-write 0 DMA disabled. #0 1 DMA enabled. When DMA enabled, DMA request will be generated by original interrupts. And interrupts will not be presented on this module at the same time. #1 RESERVED no description available 5 2 read-only C2 DAC Control Register 2 0x23 8 read-write n 0x0 0x0 DACBFRP DAC buffer read pointer 4 4 read-write DACBFUP DAC buffer upper limit 0 4 read-write DAT0H DAC Data High Register 0x2 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write RESERVED no description available 4 4 read-only DAT0L DAC Data Low Register 0x0 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT10H DAC Data High Register 0x7A 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write RESERVED no description available 4 4 read-only DAT10L DAC Data Low Register 0x6E 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT11H DAC Data High Register 0x91 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write RESERVED no description available 4 4 read-only DAT11L DAC Data Low Register 0x84 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT12H DAC Data High Register 0xAA 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write RESERVED no description available 4 4 read-only DAT12L DAC Data Low Register 0x9C 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT13H DAC Data High Register 0xC5 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write RESERVED no description available 4 4 read-only DAT13L DAC Data Low Register 0xB6 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT14H DAC Data High Register 0xE2 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write RESERVED no description available 4 4 read-only DAT14L DAC Data Low Register 0xD2 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT15H DAC Data High Register 0x101 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write RESERVED no description available 4 4 read-only DAT15L DAC Data Low Register 0xF0 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT1H DAC Data High Register 0x5 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write RESERVED no description available 4 4 read-only DAT1L DAC Data Low Register 0x2 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT2H DAC Data High Register 0xA 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write RESERVED no description available 4 4 read-only DAT2L DAC Data Low Register 0x6 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT3H DAC Data High Register 0x11 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write RESERVED no description available 4 4 read-only DAT3L DAC Data Low Register 0xC 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT4H DAC Data High Register 0x1A 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write RESERVED no description available 4 4 read-only DAT4L DAC Data Low Register 0x14 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT5H DAC Data High Register 0x25 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write RESERVED no description available 4 4 read-only DAT5L DAC Data Low Register 0x1E 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT6H DAC Data High Register 0x32 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write RESERVED no description available 4 4 read-only DAT6L DAC Data Low Register 0x2A 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT7H DAC Data High Register 0x41 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write RESERVED no description available 4 4 read-only DAT7L DAC Data Low Register 0x38 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT8H DAC Data High Register 0x52 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write RESERVED no description available 4 4 read-only DAT8L DAC Data Low Register 0x48 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT9H DAC Data High Register 0x65 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write RESERVED no description available 4 4 read-only DAT9L DAC Data Low Register 0x5A 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write SR DAC Status Register 0x20 8 read-write n 0x0 0x0 DACBFRPBF DAC buffer read pointer bottom position flag 0 1 read-write 0 The DAC buffer read pointer is not equal to the DACBFUP. #0 1 The DAC buffer read pointer is equal to the DACBFUP. #1 DACBFRPTF DAC buffer read pointer top position flag 1 1 read-write 0 The DAC buffer read pointer is not zero. #0 1 The DAC buffer read pointer is zero. #1 DACBFWMF DAC buffer watermark flag 2 1 read-write 0 The DAC buffer read pointer has not reached the watermark level. #0 1 The DAC buffer read pointer has reached the watermark level. #1 RESERVED no description available 3 5 read-only DAC1 12-Bit Digital-to-Analog Converter DAC 0x0 0x0 0x24 registers n DAC1 82 INT_DAC1 98 C0 DAC Control Register 0x21 8 read-write n 0x0 0x0 DACBBIEN DAC buffer read pointer bottom flag interrupt enable 0 1 read-write 0 The DAC buffer read pointer bottom flag interrupt is disabled. #0 1 The DAC buffer read pointer bottom flag interrupt is enabled. #1 DACBTIEN DAC buffer read pointer top flag interrupt enable 1 1 read-write 0 The DAC buffer read pointer top flag interrupt is disabled. #0 1 The DAC buffer read pointer top flag interrupt is enabled. #1 DACBWIEN DAC buffer watermark interrupt enable 2 1 read-write 0 The DAC buffer watermark interrupt is disabled. #0 1 The DAC buffer watermark interrupt is enabled. #1 DACEN DAC enable 7 1 read-write 0 The DAC system is disabled. #0 1 The DAC system is enabled. #1 DACRFS DAC Reference Select 6 1 read-write 0 The DAC selets DACREF_1 as the reference voltage. #0 1 The DAC selets DACREF_2 as the reference voltage. #1 DACSWTRG DAC software trigger 4 1 write-only 0 The DAC soft trigger is not valid. #0 1 The DAC soft trigger is valid. #1 DACTRGSEL DAC trigger select 5 1 read-write 0 The DAC hardware trigger is selected. #0 1 The DAC software trigger is selected. #1 LPEN DAC low power control 3 1 read-write 0 high power mode. #0 1 low power mode. #1 C1 DAC Control Register 1 0x22 8 read-write n 0x0 0x0 DACBFEN DAC buffer enable 0 1 read-write 0 Buffer read pointer disabled. The converted data is always the first word of the buffer. #0 1 Buffer read pointer enabled. The converted data is the word that the read pointer points to. It means converted data can be from any word of the buffer. #1 DACBFMD DAC buffer work mode select 1 2 read-write 00 Normal Mode #00 01 Swing Mode #01 10 One-Time Scan Mode #10 11 Reserved #11 DACBFWM DAC buffer watermark select 3 2 read-write 00 1 word #00 01 2 words #01 10 3 words #10 11 4 words #11 DMAEN DMA enable select 7 1 read-write 0 DMA disabled. #0 1 DMA enabled. When DMA enabled, DMA request will be generated by original interrupts. And interrupts will not be presented on this module at the same time. #1 RESERVED no description available 5 2 read-only C2 DAC Control Register 2 0x23 8 read-write n 0x0 0x0 DACBFRP DAC buffer read pointer 4 4 read-write DACBFUP DAC buffer upper limit 0 4 read-write DAT0H DAC Data High Register 0x2 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write RESERVED no description available 4 4 read-only DAT0L DAC Data Low Register 0x0 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT10H DAC Data High Register 0x7A 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write RESERVED no description available 4 4 read-only DAT10L DAC Data Low Register 0x6E 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT11H DAC Data High Register 0x91 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write RESERVED no description available 4 4 read-only DAT11L DAC Data Low Register 0x84 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT12H DAC Data High Register 0xAA 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write RESERVED no description available 4 4 read-only DAT12L DAC Data Low Register 0x9C 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT13H DAC Data High Register 0xC5 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write RESERVED no description available 4 4 read-only DAT13L DAC Data Low Register 0xB6 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT14H DAC Data High Register 0xE2 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write RESERVED no description available 4 4 read-only DAT14L DAC Data Low Register 0xD2 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT15H DAC Data High Register 0x101 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write RESERVED no description available 4 4 read-only DAT15L DAC Data Low Register 0xF0 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT1H DAC Data High Register 0x5 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write RESERVED no description available 4 4 read-only DAT1L DAC Data Low Register 0x2 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT2H DAC Data High Register 0xA 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write RESERVED no description available 4 4 read-only DAT2L DAC Data Low Register 0x6 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT3H DAC Data High Register 0x11 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write RESERVED no description available 4 4 read-only DAT3L DAC Data Low Register 0xC 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT4H DAC Data High Register 0x1A 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write RESERVED no description available 4 4 read-only DAT4L DAC Data Low Register 0x14 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT5H DAC Data High Register 0x25 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write RESERVED no description available 4 4 read-only DAT5L DAC Data Low Register 0x1E 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT6H DAC Data High Register 0x32 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write RESERVED no description available 4 4 read-only DAT6L DAC Data Low Register 0x2A 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT7H DAC Data High Register 0x41 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write RESERVED no description available 4 4 read-only DAT7L DAC Data Low Register 0x38 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT8H DAC Data High Register 0x52 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write RESERVED no description available 4 4 read-only DAT8L DAC Data Low Register 0x48 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write DAT9H DAC Data High Register 0x65 8 read-write n 0x0 0x0 DATA no description available 0 4 read-write RESERVED no description available 4 4 read-only DAT9L DAC Data Low Register 0x5A 8 read-write n 0x0 0x0 DATA no description available 0 8 read-write SR DAC Status Register 0x20 8 read-write n 0x0 0x0 DACBFRPBF DAC buffer read pointer bottom position flag 0 1 read-write 0 The DAC buffer read pointer is not equal to the DACBFUP. #0 1 The DAC buffer read pointer is equal to the DACBFUP. #1 DACBFRPTF DAC buffer read pointer top position flag 1 1 read-write 0 The DAC buffer read pointer is not zero. #0 1 The DAC buffer read pointer is zero. #1 DACBFWMF DAC buffer watermark flag 2 1 read-write 0 The DAC buffer read pointer has not reached the watermark level. #0 1 The DAC buffer read pointer has reached the watermark level. #1 RESERVED no description available 3 5 read-only DMA Enhanced direct memory access controller DMA 0x0 0x0 0x1400 registers n DMA0_DMA16 0 DMA1_DMA17 1 DMA2_DMA18 2 DMA3_DMA19 3 DMA4_DMA20 4 DMA5_DMA21 5 DMA6_DMA22 6 DMA7_DMA23 7 DMA8_DMA24 8 DMA9_DMA25 9 DMA10_DMA26 10 DMA11_DMA27 11 DMA12_DMA28 12 DMA13_DMA29 13 DMA14_DMA30 14 DMA15_DMA31 15 DMA_Error 16 INT_DMA0_DMA16 16 INT_DMA1_DMA17 17 INT_DMA2_DMA18 18 INT_DMA3_DMA19 19 INT_DMA4_DMA20 20 INT_DMA5_DMA21 21 INT_DMA6_DMA22 22 INT_DMA7_DMA23 23 INT_DMA8_DMA24 24 INT_DMA9_DMA25 25 INT_DMA10_DMA26 26 INT_DMA11_DMA27 27 INT_DMA12_DMA28 28 INT_DMA13_DMA29 29 INT_DMA14_DMA30 30 INT_DMA15_DMA31 31 INT_DMA_Error 32 CDNE Clear DONE Status Bit Register 0x1C 8 write-only n 0x0 0x0 CADN Clears All DONE Bits 6 1 write-only 0 Clears only the TCDn_CSR[DONE] bit specified in the CDNE field #0 1 Clears all bits in TCDn_CSR[DONE] #1 CDNE Clear DONE Bit 0 5 write-only NOP no description available 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 RESERVED no description available 5 1 write-only CEEI Clear Enable Error Interrupt Register 0x18 8 write-only n 0x0 0x0 CAEE Clear All Enable Error Interrupts 6 1 write-only 0 Clear only the EEI bit specified in the CEEI field #0 1 Clear all bits in EEI #1 CEEI Clear Enable Error Interrupt 0 5 write-only NOP no description available 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 RESERVED no description available 5 1 write-only CERQ Clear Enable Request Register 0x1A 8 write-only n 0x0 0x0 CAER Clear All Enable Requests 6 1 write-only 0 Clear only the ERQ bit specified in the CERQ field #0 1 Clear all bits in ERQ #1 CERQ Clear Enable Request 0 5 write-only NOP no description available 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 RESERVED no description available 5 1 write-only CERR Clear Error Register 0x1E 8 write-only n 0x0 0x0 CAEI Clear All Error Indicators 6 1 write-only 0 Clear only the ERR bit specified in the CERR field #0 1 Clear all bits in ERR #1 CERR Clear Error Indicator 0 5 write-only NOP no description available 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 RESERVED no description available 5 1 write-only CINT Clear Interrupt Request Register 0x1F 8 write-only n 0x0 0x0 CAIR Clear All Interrupt Requests 6 1 write-only 0 Clear only the INT bit specified in the CINT field #0 1 Clear all bits in INT #1 CINT Clear interrupt request 0 5 write-only NOP no description available 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 RESERVED no description available 5 1 write-only CR Control Register 0x0 32 read-write n 0x0 0x0 CLM Continuous Link Mode 6 1 read-write 0 A minor loop channel link made to itself goes through channel arbitration before being activated again. #0 1 A minor loop channel link made to itself does not go through channel arbitration before being activated again. Upon minor loop completion, the channel activates again if that channel has a minor loop channel link enabled and the link channel is itself. This effectively applies the minor loop offsets and restarts the next minor loop. #1 CX Cancel Transfer 17 1 read-write 0 Normal operation #0 1 Cancel the remaining data transfer. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The CX bit clears itself after the cancel has been honored. This cancel retires the channel normally as if the minor loop was completed. #1 ECX Error Cancel Transfer 16 1 read-write 0 Normal operation #0 1 Cancel the remaining data transfer in the same fashion as the CX bit. Stop the executing channel and force the minor loop to finish. The cancel takes effect after the last write of the current read/write sequence. The ECX bit clears itself after the cancel is honored. In addition to cancelling the transfer, ECX treats the cancel as an error condition, thus updating the ES register and generating an optional error interrupt. #1 EDBG Enable Debug 1 1 read-write 0 When in debug mode, the DMA continues to operate. #0 1 When in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete. Channel execution resumes when the system exits debug mode or the EDBG bit is cleared. #1 EMLM Enable Minor Loop Mapping 7 1 read-write 0 Disabled. TCDn.word2 is defined as a 32-bit NBYTES field. #0 1 Enabled. TCDn.word2 is redefined to include individual enable fields, an offset field, and the NBYTES field. The individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. The NBYTES field is reduced when either offset is enabled. #1 ERCA Enable Round Robin Channel Arbitration 2 1 read-write 0 Fixed priority arbitration is used for channel selection within each group. #0 1 Round robin arbitration is used for channel selection within each group. #1 ERGA Enable Round Robin Group Arbitration 3 1 read-write 0 Fixed priority arbitration is used for selection among the groups. #0 1 Round robin arbitration is used for selection among the groups. #1 GRP0PRI Channel Group 0 Priority 8 2 read-write GRP1PRI Channel Group 1 Priority 10 2 read-write HALT Halt DMA Operations 5 1 read-write 0 Normal operation #0 1 Stall the start of any new channels. Executing channels are allowed to complete. Channel execution resumes when this bit is cleared. #1 HOE Halt On Error 4 1 read-write 0 Normal operation #0 1 Any error causes the HALT bit to set. Subsequently, all service requests are ignored until the HALT bit is cleared. #1 RESERVED no description available 0 1 read-only RESERVED no description available 12 2 read-only RESERVED no description available 14 2 read-only RESERVED no description available 18 14 read-only DCHPRI0 Channel n Priority Register 0x506 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable preempt ability. This bit resets to zero. 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption. This bit resets to zero. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI1 Channel n Priority Register 0x403 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable preempt ability. This bit resets to zero. 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption. This bit resets to zero. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI10 Channel n Priority Register 0xB2D 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable preempt ability. This bit resets to zero. 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption. This bit resets to zero. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI11 Channel n Priority Register 0xA24 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable preempt ability. This bit resets to zero. 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption. This bit resets to zero. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI12 Channel n Priority Register 0x1178 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable preempt ability. This bit resets to zero. 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption. This bit resets to zero. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI13 Channel n Priority Register 0x1069 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable preempt ability. This bit resets to zero. 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption. This bit resets to zero. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI14 Channel n Priority Register 0xF5B 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable preempt ability. This bit resets to zero. 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption. This bit resets to zero. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI15 Channel n Priority Register 0xE4E 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable preempt ability. This bit resets to zero. 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption. This bit resets to zero. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI16 Channel n Priority Register 0x15BE 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable preempt ability. This bit resets to zero. 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption. This bit resets to zero. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI17 Channel n Priority Register 0x14AB 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable preempt ability. This bit resets to zero. 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption. This bit resets to zero. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI18 Channel n Priority Register 0x1399 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable preempt ability. This bit resets to zero. 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption. This bit resets to zero. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI19 Channel n Priority Register 0x1288 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable preempt ability. This bit resets to zero. 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption. This bit resets to zero. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI2 Channel n Priority Register 0x301 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable preempt ability. This bit resets to zero. 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption. This bit resets to zero. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI20 Channel n Priority Register 0x1A14 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable preempt ability. This bit resets to zero. 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption. This bit resets to zero. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI21 Channel n Priority Register 0x18FD 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable preempt ability. This bit resets to zero. 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption. This bit resets to zero. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI22 Channel n Priority Register 0x17E7 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable preempt ability. This bit resets to zero. 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption. This bit resets to zero. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI23 Channel n Priority Register 0x16D2 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable preempt ability. This bit resets to zero. 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption. This bit resets to zero. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI24 Channel n Priority Register 0x1E7A 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable preempt ability. This bit resets to zero. 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption. This bit resets to zero. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI25 Channel n Priority Register 0x1D5F 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable preempt ability. This bit resets to zero. 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption. This bit resets to zero. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI26 Channel n Priority Register 0x1C45 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable preempt ability. This bit resets to zero. 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption. This bit resets to zero. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI27 Channel n Priority Register 0x1B2C 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable preempt ability. This bit resets to zero. 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption. This bit resets to zero. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI28 Channel n Priority Register 0x22F0 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable preempt ability. This bit resets to zero. 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption. This bit resets to zero. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI29 Channel n Priority Register 0x21D1 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable preempt ability. This bit resets to zero. 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption. This bit resets to zero. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI3 Channel n Priority Register 0x200 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable preempt ability. This bit resets to zero. 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption. This bit resets to zero. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI30 Channel n Priority Register 0x20B3 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable preempt ability. This bit resets to zero. 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption. This bit resets to zero. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI31 Channel n Priority Register 0x1F96 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable preempt ability. This bit resets to zero. 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption. This bit resets to zero. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI4 Channel n Priority Register 0x91C 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable preempt ability. This bit resets to zero. 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption. This bit resets to zero. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI5 Channel n Priority Register 0x815 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable preempt ability. This bit resets to zero. 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption. This bit resets to zero. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI6 Channel n Priority Register 0x70F 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable preempt ability. This bit resets to zero. 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption. This bit resets to zero. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI7 Channel n Priority Register 0x60A 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable preempt ability. This bit resets to zero. 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption. This bit resets to zero. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI8 Channel n Priority Register 0xD42 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable preempt ability. This bit resets to zero. 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption. This bit resets to zero. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 GRPPRI Channel n Current Group Priority 4 2 read-only DCHPRI9 Channel n Priority Register 0xC37 8 read-write n 0x0 0x0 CHPRI Channel n Arbitration Priority 0 4 read-write DPA Disable preempt ability. This bit resets to zero. 6 1 read-write 0 Channel n can suspend a lower priority channel #0 1 Channel n cannot suspend any channel, regardless of channel priority #1 ECP Enable Channel Preemption. This bit resets to zero. 7 1 read-write 0 Channel n cannot be suspended by a higher priority channel's service request #0 1 Channel n can be temporarily suspended by the service request of a higher priority channel #1 GRPPRI Channel n Current Group Priority 4 2 read-only EEI Enable Error Interrupt Register 0x14 32 read-write n 0x0 0x0 EEI0 Enable Error Interrupt 0 0 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI1 Enable Error Interrupt 1 1 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI10 Enable Error Interrupt 10 10 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI11 Enable Error Interrupt 11 11 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI12 Enable Error Interrupt 12 12 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI13 Enable Error Interrupt 13 13 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI14 Enable Error Interrupt 14 14 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI15 Enable Error Interrupt 15 15 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI16 Enable Error Interrupt 16 16 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI17 Enable Error Interrupt 17 17 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI18 Enable Error Interrupt 18 18 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI19 Enable Error Interrupt 19 19 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI2 Enable Error Interrupt 2 2 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI20 Enable Error Interrupt 20 20 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI21 Enable Error Interrupt 21 21 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI22 Enable Error Interrupt 22 22 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI23 Enable Error Interrupt 23 23 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI24 Enable Error Interrupt 24 24 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI25 Enable Error Interrupt 25 25 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI26 Enable Error Interrupt 26 26 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI27 Enable Error Interrupt 27 27 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI28 Enable Error Interrupt 28 28 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI29 Enable Error Interrupt 29 29 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI3 Enable Error Interrupt 3 3 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI30 Enable Error Interrupt 30 30 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI31 Enable Error Interrupt 31 31 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI4 Enable Error Interrupt 4 4 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI5 Enable Error Interrupt 5 5 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI6 Enable Error Interrupt 6 6 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI7 Enable Error Interrupt 7 7 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI8 Enable Error Interrupt 8 8 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 EEI9 Enable Error Interrupt 9 9 1 read-write 0 The error signal for corresponding channel does not generate an error interrupt #0 1 The assertion of the error signal for corresponding channel generates an error interrupt request #1 ERQ Enable Request Register 0xC 32 read-write n 0x0 0x0 ERQ0 Enable DMA Request 0 0 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ1 Enable DMA Request 1 1 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ10 Enable DMA Request 10 10 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ11 Enable DMA Request 11 11 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ12 Enable DMA Request 12 12 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ13 Enable DMA Request 13 13 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ14 Enable DMA Request 14 14 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ15 Enable DMA Request 15 15 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ16 Enable DMA Request 16 16 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ17 Enable DMA Request 17 17 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ18 Enable DMA Request 18 18 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ19 Enable DMA Request 19 19 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ2 Enable DMA Request 2 2 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ20 Enable DMA Request 20 20 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ21 Enable DMA Request 21 21 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ22 Enable DMA Request 22 22 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ23 Enable DMA Request 23 23 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ24 Enable DMA Request 24 24 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ25 Enable DMA Request 25 25 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ26 Enable DMA Request 26 26 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ27 Enable DMA Request 27 27 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ28 Enable DMA Request 28 28 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ29 Enable DMA Request 29 29 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ3 Enable DMA Request 3 3 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ30 Enable DMA Request 30 30 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ31 Enable DMA Request 31 31 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ4 Enable DMA Request 4 4 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ5 Enable DMA Request 5 5 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ6 Enable DMA Request 6 6 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ7 Enable DMA Request 7 7 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ8 Enable DMA Request 8 8 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERQ9 Enable DMA Request 9 9 1 read-write 0 The DMA request signal for the corresponding channel is disabled #0 1 The DMA request signal for the corresponding channel is enabled #1 ERR Error Register 0x2C 32 read-write n 0x0 0x0 ERR0 Error In Channel 0 0 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR1 Error In Channel 1 1 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR10 Error In Channel 10 10 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR11 Error In Channel 11 11 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR12 Error In Channel 12 12 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR13 Error In Channel 13 13 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR14 Error In Channel 14 14 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR15 Error In Channel 15 15 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR16 Error In Channel 16 16 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR17 Error In Channel 17 17 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR18 Error In Channel 18 18 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR19 Error In Channel 19 19 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR2 Error In Channel 2 2 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR20 Error In Channel 20 20 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR21 Error In Channel 21 21 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR22 Error In Channel 22 22 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR23 Error In Channel 23 23 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR24 Error In Channel 24 24 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR25 Error In Channel 25 25 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR26 Error In Channel 26 26 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR27 Error In Channel 27 27 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR28 Error In Channel 28 28 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR29 Error In Channel 29 29 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR3 Error In Channel 3 3 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR30 Error In Channel 30 30 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR31 Error In Channel 31 31 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR4 Error In Channel 4 4 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR5 Error In Channel 5 5 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR6 Error In Channel 6 6 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR7 Error In Channel 7 7 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR8 Error In Channel 8 8 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ERR9 Error In Channel 9 9 1 read-write 0 An error in the corresponding channel has not occurred #0 1 An error in the corresponding channel has occurred #1 ES Error Status Register 0x4 32 read-only n 0x0 0x0 CPE Channel Priority Error 14 1 read-only 0 No channel priority error #0 1 The last recorded error was a configuration error in the channel priorities within a group. Channel priorities within a group are not unique. #1 DAE Destination Address Error 5 1 read-only 0 No destination address configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR is inconsistent with TCDn_ATTR[DSIZE]. #1 DBE Destination Bus Error 0 1 read-only 0 No destination bus error #0 1 The last recorded error was a bus error on a destination write #1 DOE Destination Offset Error 4 1 read-only 0 No destination offset configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE]. #1 ECX Transfer Cancelled 16 1 read-only 0 No cancelled transfers #0 1 The last recorded entry was a cancelled transfer by the error cancel transfer input #1 ERRCHN Error Channel Number or Cancelled Channel Number 8 5 read-only GPE Group Priority Error 15 1 read-only 0 No group priority error #0 1 The last recorded error was a configuration error among the group priorities. All group priorities are not unique. #1 NCE NBYTES/CITER Configuration Error 3 1 read-only 0 No NBYTES/CITER configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] is equal to zero, or TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK] #1 RESERVED no description available 13 1 read-only RESERVED no description available 17 14 read-only SAE Source Address Error 7 1 read-only 0 No source address configuration error. #0 1 The last recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR is inconsistent with TCDn_ATTR[SSIZE]. #1 SBE Source Bus Error 1 1 read-only 0 No source bus error #0 1 The last recorded error was a bus error on a source read #1 SGE Scatter/Gather Configuration Error 2 1 read-only 0 No scatter/gather configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_DLASTSGA field. This field is checked at the beginning of a scatter/gather operation after major loop completion if TCDn_CSR[ESG] is enabled. TCDn_DLASTSGA is not on a 32 byte boundary. #1 SOE Source Offset Error 6 1 read-only 0 No source offset configuration error #0 1 The last recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE]. #1 VLD no description available 31 1 read-only 0 No ERR bits are set #0 1 At least one ERR bit is set indicating a valid error exists that has not been cleared #1 HRS Hardware Request Status Register 0x34 32 read-write n 0x0 0x0 HRS0 Hardware Request Status Channel 0 0 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS1 Hardware Request Status Channel 1 1 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS10 Hardware Request Status Channel 10 10 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS11 Hardware Request Status Channel 11 11 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS12 Hardware Request Status Channel 12 12 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS13 Hardware Request Status Channel 13 13 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS14 Hardware Request Status Channel 14 14 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS15 Hardware Request Status Channel 15 15 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS16 Hardware Request Status Channel 16 16 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS17 Hardware Request Status Channel 17 17 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS18 Hardware Request Status Channel 18 18 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS19 Hardware Request Status Channel 19 19 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS2 Hardware Request Status Channel 2 2 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS20 Hardware Request Status Channel 20 20 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS21 Hardware Request Status Channel 21 21 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS22 Hardware Request Status Channel 22 22 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS23 Hardware Request Status Channel 23 23 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS24 Hardware Request Status Channel 24 24 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS25 Hardware Request Status Channel 25 25 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS26 Hardware Request Status Channel 26 26 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS27 Hardware Request Status Channel 27 27 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS28 Hardware Request Status Channel 28 28 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS29 Hardware Request Status Channel 29 29 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS3 Hardware Request Status Channel 3 3 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS30 Hardware Request Status Channel 30 30 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS31 Hardware Request Status Channel 31 31 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS4 Hardware Request Status Channel 4 4 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS5 Hardware Request Status Channel 5 5 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS6 Hardware Request Status Channel 6 6 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS7 Hardware Request Status Channel 7 7 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS8 Hardware Request Status Channel 8 8 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 HRS9 Hardware Request Status Channel 9 9 1 read-write 0 A hardware service request for the corresponding channel is not present #0 1 A hardware service request for the corresponding channel is present #1 INT Interrupt Request Register 0x24 32 read-write n 0x0 0x0 INT0 Interrupt Request 0 0 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT1 Interrupt Request 1 1 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT10 Interrupt Request 10 10 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT11 Interrupt Request 11 11 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT12 Interrupt Request 12 12 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT13 Interrupt Request 13 13 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT14 Interrupt Request 14 14 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT15 Interrupt Request 15 15 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT16 Interrupt Request 16 16 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT17 Interrupt Request 17 17 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT18 Interrupt Request 18 18 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT19 Interrupt Request 19 19 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT2 Interrupt Request 2 2 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT20 Interrupt Request 20 20 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT21 Interrupt Request 21 21 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT22 Interrupt Request 22 22 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT23 Interrupt Request 23 23 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT24 Interrupt Request 24 24 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT25 Interrupt Request 25 25 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT26 Interrupt Request 26 26 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT27 Interrupt Request 27 27 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT28 Interrupt Request 28 28 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT29 Interrupt Request 29 29 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT3 Interrupt Request 3 3 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT30 Interrupt Request 30 30 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT31 Interrupt Request 31 31 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT4 Interrupt Request 4 4 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT5 Interrupt Request 5 5 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT6 Interrupt Request 6 6 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT7 Interrupt Request 7 7 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT8 Interrupt Request 8 8 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 INT9 Interrupt Request 9 9 1 read-write 0 The interrupt request for corresponding channel is cleared #0 1 The interrupt request for corresponding channel is active #1 SEEI Set Enable Error Interrupt Register 0x19 8 write-only n 0x0 0x0 NOP no description available 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 RESERVED no description available 5 1 write-only SAEE Sets All Enable Error Interrupts 6 1 write-only 0 Set only the EEI bit specified in the SEEI field. #0 1 Sets all bits in EEI #1 SEEI Set Enable Error Interrupt 0 5 write-only SERQ Set Enable Request Register 0x1B 8 write-only n 0x0 0x0 NOP no description available 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 RESERVED no description available 5 1 write-only SAER Set All Enable Requests 6 1 write-only 0 Set only the ERQ bit specified in the SERQ field #0 1 Set all bits in ERQ #1 SERQ Set Enable Request 0 5 write-only SSRT Set START Bit Register 0x1D 8 write-only n 0x0 0x0 NOP no description available 7 1 write-only 0 Normal operation #0 1 No operation, ignore the other bits in this register #1 RESERVED no description available 5 1 write-only SAST Set All START Bits (activates all channels) 6 1 write-only 0 Set only the TCDn_CSR[START] bit specified in the SSRT field #0 1 Set all bits in TCDn_CSR[START] #1 SSRT Set START Bit 0 5 write-only TCD0_ATTR TCD Transfer Attributes 0x200C 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 011 Reserved #011 100 16-byte burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TCD0_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x203C 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD0_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x203C 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD0_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x202C 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD0_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x202C 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD0_CSR TCD Control and Status 0x2038 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 01 Reserved #01 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 5 read-write RESERVED no description available 13 1 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD0_DADDR TCD Destination Address 0x2020 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD0_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x2030 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD0_DOFF TCD Signed Destination Address Offset 0x2028 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD0_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x2010 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD0_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x2010 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD0_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x2010 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset Enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD0_SADDR TCD Source Address 0x2000 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD0_SLAST TCD Last Source Address Adjustment 0x2018 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD0_SOFF TCD Signed Source Address Offset 0x2008 16 read-write n 0x0 0x0 SOFF Source Address Signed Offset 0 16 read-write TCD10_ATTR TCD Transfer Attributes 0xC728 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 011 Reserved #011 100 16-byte burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TCD10_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xC848 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD10_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xC848 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD10_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xC7E8 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD10_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xC7E8 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD10_CSR TCD Control and Status 0xC830 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 01 Reserved #01 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 5 read-write RESERVED no description available 13 1 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD10_DADDR TCD Destination Address 0xC7A0 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD10_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0xC800 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD10_DOFF TCD Signed Destination Address Offset 0xC7D0 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD10_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0xC740 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD10_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0xC740 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD10_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0xC740 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset Enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD10_SADDR TCD Source Address 0xC6E0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD10_SLAST TCD Last Source Address Adjustment 0xC770 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD10_SOFF TCD Signed Source Address Offset 0xC710 16 read-write n 0x0 0x0 SOFF Source Address Signed Offset 0 16 read-write TCD11_ATTR TCD Transfer Attributes 0xD88E 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 011 Reserved #011 100 16-byte burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TCD11_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xD9C6 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD11_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xD9C6 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD11_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xD95E 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD11_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xD95E 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD11_CSR TCD Control and Status 0xD9AC 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 01 Reserved #01 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 5 read-write RESERVED no description available 13 1 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD11_DADDR TCD Destination Address 0xD910 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD11_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0xD978 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD11_DOFF TCD Signed Destination Address Offset 0xD944 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD11_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0xD8A8 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD11_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0xD8A8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD11_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0xD8A8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset Enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD11_SADDR TCD Source Address 0xD840 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD11_SLAST TCD Last Source Address Adjustment 0xD8DC 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD11_SOFF TCD Signed Source Address Offset 0xD874 16 read-write n 0x0 0x0 SOFF Source Address Signed Offset 0 16 read-write TCD12_ATTR TCD Transfer Attributes 0xEA14 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 011 Reserved #011 100 16-byte burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TCD12_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xEB64 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD12_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xEB64 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD12_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xEAF4 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD12_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xEAF4 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD12_CSR TCD Control and Status 0xEB48 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 01 Reserved #01 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 5 read-write RESERVED no description available 13 1 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD12_DADDR TCD Destination Address 0xEAA0 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD12_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0xEB10 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD12_DOFF TCD Signed Destination Address Offset 0xEAD8 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD12_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0xEA30 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD12_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0xEA30 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD12_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0xEA30 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset Enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD12_SADDR TCD Source Address 0xE9C0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD12_SLAST TCD Last Source Address Adjustment 0xEA68 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD12_SOFF TCD Signed Source Address Offset 0xE9F8 16 read-write n 0x0 0x0 SOFF Source Address Signed Offset 0 16 read-write TCD13_ATTR TCD Transfer Attributes 0xFBBA 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 011 Reserved #011 100 16-byte burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TCD13_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xFD22 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD13_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xFD22 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD13_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xFCAA 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD13_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xFCAA 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD13_CSR TCD Control and Status 0xFD04 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 01 Reserved #01 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 5 read-write RESERVED no description available 13 1 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD13_DADDR TCD Destination Address 0xFC50 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD13_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0xFCC8 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD13_DOFF TCD Signed Destination Address Offset 0xFC8C 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD13_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0xFBD8 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD13_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0xFBD8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD13_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0xFBD8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset Enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD13_SADDR TCD Source Address 0xFB60 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD13_SLAST TCD Last Source Address Adjustment 0xFC14 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD13_SOFF TCD Signed Source Address Offset 0xFB9C 16 read-write n 0x0 0x0 SOFF Source Address Signed Offset 0 16 read-write TCD14_ATTR TCD Transfer Attributes 0x10D80 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 011 Reserved #011 100 16-byte burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TCD14_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x10F00 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD14_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x10F00 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD14_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x10E80 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD14_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x10E80 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD14_CSR TCD Control and Status 0x10EE0 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 01 Reserved #01 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 5 read-write RESERVED no description available 13 1 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD14_DADDR TCD Destination Address 0x10E20 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD14_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x10EA0 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD14_DOFF TCD Signed Destination Address Offset 0x10E60 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD14_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x10DA0 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD14_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x10DA0 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD14_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x10DA0 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset Enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD14_SADDR TCD Source Address 0x10D20 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD14_SLAST TCD Last Source Address Adjustment 0x10DE0 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD14_SOFF TCD Signed Source Address Offset 0x10D60 16 read-write n 0x0 0x0 SOFF Source Address Signed Offset 0 16 read-write TCD15_ATTR TCD Transfer Attributes 0x11F66 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 011 Reserved #011 100 16-byte burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TCD15_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x120FE 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD15_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x120FE 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD15_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x12076 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD15_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x12076 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD15_CSR TCD Control and Status 0x120DC 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 01 Reserved #01 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 5 read-write RESERVED no description available 13 1 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD15_DADDR TCD Destination Address 0x12010 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD15_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x12098 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD15_DOFF TCD Signed Destination Address Offset 0x12054 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD15_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x11F88 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD15_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x11F88 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD15_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x11F88 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset Enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD15_SADDR TCD Source Address 0x11F00 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD15_SLAST TCD Last Source Address Adjustment 0x11FCC 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD15_SOFF TCD Signed Source Address Offset 0x11F44 16 read-write n 0x0 0x0 SOFF Source Address Signed Offset 0 16 read-write TCD16_ATTR TCD Transfer Attributes 0x1316C 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 011 Reserved #011 100 16-byte burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TCD16_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1331C 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD16_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1331C 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD16_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1328C 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD16_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1328C 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD16_CSR TCD Control and Status 0x132F8 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 01 Reserved #01 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 5 read-write RESERVED no description available 13 1 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD16_DADDR TCD Destination Address 0x13220 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD16_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x132B0 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD16_DOFF TCD Signed Destination Address Offset 0x13268 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD16_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x13190 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD16_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x13190 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD16_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x13190 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset Enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD16_SADDR TCD Source Address 0x13100 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD16_SLAST TCD Last Source Address Adjustment 0x131D8 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD16_SOFF TCD Signed Source Address Offset 0x13148 16 read-write n 0x0 0x0 SOFF Source Address Signed Offset 0 16 read-write TCD17_ATTR TCD Transfer Attributes 0x14392 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 011 Reserved #011 100 16-byte burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TCD17_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1455A 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD17_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1455A 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD17_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x144C2 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD17_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x144C2 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD17_CSR TCD Control and Status 0x14534 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 01 Reserved #01 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 5 read-write RESERVED no description available 13 1 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD17_DADDR TCD Destination Address 0x14450 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD17_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x144E8 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD17_DOFF TCD Signed Destination Address Offset 0x1449C 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD17_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x143B8 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD17_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x143B8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD17_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x143B8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset Enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD17_SADDR TCD Source Address 0x14320 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD17_SLAST TCD Last Source Address Adjustment 0x14404 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD17_SOFF TCD Signed Source Address Offset 0x1436C 16 read-write n 0x0 0x0 SOFF Source Address Signed Offset 0 16 read-write TCD18_ATTR TCD Transfer Attributes 0x155D8 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 011 Reserved #011 100 16-byte burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TCD18_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x157B8 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD18_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x157B8 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD18_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x15718 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD18_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x15718 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD18_CSR TCD Control and Status 0x15790 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 01 Reserved #01 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 5 read-write RESERVED no description available 13 1 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD18_DADDR TCD Destination Address 0x156A0 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD18_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x15740 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD18_DOFF TCD Signed Destination Address Offset 0x156F0 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD18_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x15600 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD18_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x15600 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD18_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x15600 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset Enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD18_SADDR TCD Source Address 0x15560 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD18_SLAST TCD Last Source Address Adjustment 0x15650 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD18_SOFF TCD Signed Source Address Offset 0x155B0 16 read-write n 0x0 0x0 SOFF Source Address Signed Offset 0 16 read-write TCD19_ATTR TCD Transfer Attributes 0x1683E 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 011 Reserved #011 100 16-byte burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TCD19_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x16A36 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD19_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x16A36 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD19_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1698E 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD19_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1698E 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD19_CSR TCD Control and Status 0x16A0C 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 01 Reserved #01 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 5 read-write RESERVED no description available 13 1 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD19_DADDR TCD Destination Address 0x16910 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD19_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x169B8 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD19_DOFF TCD Signed Destination Address Offset 0x16964 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD19_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x16868 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD19_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x16868 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD19_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x16868 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset Enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD19_SADDR TCD Source Address 0x167C0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD19_SLAST TCD Last Source Address Adjustment 0x168BC 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD19_SOFF TCD Signed Source Address Offset 0x16814 16 read-write n 0x0 0x0 SOFF Source Address Signed Offset 0 16 read-write TCD1_ATTR TCD Transfer Attributes 0x3032 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 011 Reserved #011 100 16-byte burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TCD1_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x307A 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD1_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x307A 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD1_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x3062 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD1_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x3062 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD1_CSR TCD Control and Status 0x3074 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 01 Reserved #01 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 5 read-write RESERVED no description available 13 1 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD1_DADDR TCD Destination Address 0x3050 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD1_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x3068 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD1_DOFF TCD Signed Destination Address Offset 0x305C 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD1_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x3038 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD1_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x3038 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD1_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x3038 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset Enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD1_SADDR TCD Source Address 0x3020 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD1_SLAST TCD Last Source Address Adjustment 0x3044 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD1_SOFF TCD Signed Source Address Offset 0x302C 16 read-write n 0x0 0x0 SOFF Source Address Signed Offset 0 16 read-write TCD20_ATTR TCD Transfer Attributes 0x17AC4 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 011 Reserved #011 100 16-byte burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TCD20_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x17CD4 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD20_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x17CD4 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD20_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x17C24 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD20_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x17C24 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD20_CSR TCD Control and Status 0x17CA8 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 01 Reserved #01 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 5 read-write RESERVED no description available 13 1 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD20_DADDR TCD Destination Address 0x17BA0 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD20_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x17C50 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD20_DOFF TCD Signed Destination Address Offset 0x17BF8 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD20_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x17AF0 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD20_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x17AF0 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD20_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x17AF0 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset Enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD20_SADDR TCD Source Address 0x17A40 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD20_SLAST TCD Last Source Address Adjustment 0x17B48 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD20_SOFF TCD Signed Source Address Offset 0x17A98 16 read-write n 0x0 0x0 SOFF Source Address Signed Offset 0 16 read-write TCD21_ATTR TCD Transfer Attributes 0x18D6A 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 011 Reserved #011 100 16-byte burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TCD21_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x18F92 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD21_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x18F92 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD21_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x18EDA 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD21_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x18EDA 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD21_CSR TCD Control and Status 0x18F64 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 01 Reserved #01 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 5 read-write RESERVED no description available 13 1 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD21_DADDR TCD Destination Address 0x18E50 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD21_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x18F08 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD21_DOFF TCD Signed Destination Address Offset 0x18EAC 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD21_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x18D98 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD21_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x18D98 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD21_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x18D98 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset Enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD21_SADDR TCD Source Address 0x18CE0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD21_SLAST TCD Last Source Address Adjustment 0x18DF4 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD21_SOFF TCD Signed Source Address Offset 0x18D3C 16 read-write n 0x0 0x0 SOFF Source Address Signed Offset 0 16 read-write TCD22_ATTR TCD Transfer Attributes 0x1A030 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 011 Reserved #011 100 16-byte burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TCD22_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1A270 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD22_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1A270 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD22_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1A1B0 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD22_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1A1B0 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD22_CSR TCD Control and Status 0x1A240 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 01 Reserved #01 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 5 read-write RESERVED no description available 13 1 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD22_DADDR TCD Destination Address 0x1A120 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD22_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1A1E0 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD22_DOFF TCD Signed Destination Address Offset 0x1A180 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD22_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x1A060 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD22_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x1A060 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD22_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x1A060 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset Enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD22_SADDR TCD Source Address 0x19FA0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD22_SLAST TCD Last Source Address Adjustment 0x1A0C0 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD22_SOFF TCD Signed Source Address Offset 0x1A000 16 read-write n 0x0 0x0 SOFF Source Address Signed Offset 0 16 read-write TCD23_ATTR TCD Transfer Attributes 0x1B316 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 011 Reserved #011 100 16-byte burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TCD23_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1B56E 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD23_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1B56E 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD23_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1B4A6 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD23_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1B4A6 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD23_CSR TCD Control and Status 0x1B53C 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 01 Reserved #01 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 5 read-write RESERVED no description available 13 1 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD23_DADDR TCD Destination Address 0x1B410 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD23_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1B4D8 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD23_DOFF TCD Signed Destination Address Offset 0x1B474 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD23_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x1B348 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD23_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x1B348 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD23_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x1B348 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset Enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD23_SADDR TCD Source Address 0x1B280 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD23_SLAST TCD Last Source Address Adjustment 0x1B3AC 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD23_SOFF TCD Signed Source Address Offset 0x1B2E4 16 read-write n 0x0 0x0 SOFF Source Address Signed Offset 0 16 read-write TCD24_ATTR TCD Transfer Attributes 0x1C61C 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 011 Reserved #011 100 16-byte burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TCD24_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1C88C 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD24_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1C88C 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD24_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1C7BC 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD24_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1C7BC 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD24_CSR TCD Control and Status 0x1C858 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 01 Reserved #01 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 5 read-write RESERVED no description available 13 1 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD24_DADDR TCD Destination Address 0x1C720 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD24_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1C7F0 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD24_DOFF TCD Signed Destination Address Offset 0x1C788 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD24_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x1C650 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD24_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x1C650 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD24_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x1C650 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset Enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD24_SADDR TCD Source Address 0x1C580 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD24_SLAST TCD Last Source Address Adjustment 0x1C6B8 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD24_SOFF TCD Signed Source Address Offset 0x1C5E8 16 read-write n 0x0 0x0 SOFF Source Address Signed Offset 0 16 read-write TCD25_ATTR TCD Transfer Attributes 0x1D942 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 011 Reserved #011 100 16-byte burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TCD25_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1DBCA 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD25_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1DBCA 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD25_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1DAF2 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD25_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1DAF2 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD25_CSR TCD Control and Status 0x1DB94 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 01 Reserved #01 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 5 read-write RESERVED no description available 13 1 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD25_DADDR TCD Destination Address 0x1DA50 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD25_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1DB28 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD25_DOFF TCD Signed Destination Address Offset 0x1DABC 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD25_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x1D978 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD25_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x1D978 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD25_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x1D978 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset Enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD25_SADDR TCD Source Address 0x1D8A0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD25_SLAST TCD Last Source Address Adjustment 0x1D9E4 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD25_SOFF TCD Signed Source Address Offset 0x1D90C 16 read-write n 0x0 0x0 SOFF Source Address Signed Offset 0 16 read-write TCD26_ATTR TCD Transfer Attributes 0x1EC88 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 011 Reserved #011 100 16-byte burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TCD26_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1EF28 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD26_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1EF28 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD26_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x1EE48 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD26_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x1EE48 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD26_CSR TCD Control and Status 0x1EEF0 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 01 Reserved #01 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 5 read-write RESERVED no description available 13 1 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD26_DADDR TCD Destination Address 0x1EDA0 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD26_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x1EE80 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD26_DOFF TCD Signed Destination Address Offset 0x1EE10 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD26_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x1ECC0 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD26_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x1ECC0 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD26_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x1ECC0 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset Enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD26_SADDR TCD Source Address 0x1EBE0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD26_SLAST TCD Last Source Address Adjustment 0x1ED30 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD26_SOFF TCD Signed Source Address Offset 0x1EC50 16 read-write n 0x0 0x0 SOFF Source Address Signed Offset 0 16 read-write TCD27_ATTR TCD Transfer Attributes 0x1FFEE 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 011 Reserved #011 100 16-byte burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TCD27_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x202A6 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD27_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x202A6 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD27_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x201BE 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD27_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x201BE 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD27_CSR TCD Control and Status 0x2026C 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 01 Reserved #01 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 5 read-write RESERVED no description available 13 1 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD27_DADDR TCD Destination Address 0x20110 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD27_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x201F8 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD27_DOFF TCD Signed Destination Address Offset 0x20184 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD27_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x20028 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD27_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x20028 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD27_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x20028 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset Enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD27_SADDR TCD Source Address 0x1FF40 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD27_SLAST TCD Last Source Address Adjustment 0x2009C 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD27_SOFF TCD Signed Source Address Offset 0x1FFB4 16 read-write n 0x0 0x0 SOFF Source Address Signed Offset 0 16 read-write TCD28_ATTR TCD Transfer Attributes 0x21374 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 011 Reserved #011 100 16-byte burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TCD28_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x21644 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD28_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x21644 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD28_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x21554 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD28_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x21554 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD28_CSR TCD Control and Status 0x21608 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 01 Reserved #01 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 5 read-write RESERVED no description available 13 1 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD28_DADDR TCD Destination Address 0x214A0 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD28_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x21590 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD28_DOFF TCD Signed Destination Address Offset 0x21518 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD28_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x213B0 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD28_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x213B0 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD28_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x213B0 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset Enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD28_SADDR TCD Source Address 0x212C0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD28_SLAST TCD Last Source Address Adjustment 0x21428 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD28_SOFF TCD Signed Source Address Offset 0x21338 16 read-write n 0x0 0x0 SOFF Source Address Signed Offset 0 16 read-write TCD29_ATTR TCD Transfer Attributes 0x2271A 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 011 Reserved #011 100 16-byte burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TCD29_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x22A02 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD29_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x22A02 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD29_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x2290A 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD29_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x2290A 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD29_CSR TCD Control and Status 0x229C4 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 01 Reserved #01 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 5 read-write RESERVED no description available 13 1 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD29_DADDR TCD Destination Address 0x22850 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD29_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x22948 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD29_DOFF TCD Signed Destination Address Offset 0x228CC 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD29_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x22758 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD29_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x22758 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD29_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x22758 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset Enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD29_SADDR TCD Source Address 0x22660 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD29_SLAST TCD Last Source Address Adjustment 0x227D4 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD29_SOFF TCD Signed Source Address Offset 0x226DC 16 read-write n 0x0 0x0 SOFF Source Address Signed Offset 0 16 read-write TCD2_ATTR TCD Transfer Attributes 0x4078 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 011 Reserved #011 100 16-byte burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TCD2_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x40D8 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD2_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x40D8 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD2_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x40B8 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD2_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x40B8 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD2_CSR TCD Control and Status 0x40D0 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 01 Reserved #01 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 5 read-write RESERVED no description available 13 1 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD2_DADDR TCD Destination Address 0x40A0 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD2_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x40C0 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD2_DOFF TCD Signed Destination Address Offset 0x40B0 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD2_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x4080 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD2_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x4080 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD2_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x4080 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset Enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD2_SADDR TCD Source Address 0x4060 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD2_SLAST TCD Last Source Address Adjustment 0x4090 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD2_SOFF TCD Signed Source Address Offset 0x4070 16 read-write n 0x0 0x0 SOFF Source Address Signed Offset 0 16 read-write TCD30_ATTR TCD Transfer Attributes 0x23AE0 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 011 Reserved #011 100 16-byte burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TCD30_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x23DE0 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD30_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x23DE0 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD30_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x23CE0 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD30_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x23CE0 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD30_CSR TCD Control and Status 0x23DA0 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 01 Reserved #01 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 5 read-write RESERVED no description available 13 1 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD30_DADDR TCD Destination Address 0x23C20 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD30_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x23D20 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD30_DOFF TCD Signed Destination Address Offset 0x23CA0 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD30_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x23B20 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD30_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x23B20 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD30_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x23B20 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset Enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD30_SADDR TCD Source Address 0x23A20 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD30_SLAST TCD Last Source Address Adjustment 0x23BA0 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD30_SOFF TCD Signed Source Address Offset 0x23AA0 16 read-write n 0x0 0x0 SOFF Source Address Signed Offset 0 16 read-write TCD31_ATTR TCD Transfer Attributes 0x24EC6 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 011 Reserved #011 100 16-byte burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TCD31_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x251DE 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD31_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x251DE 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD31_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x250D6 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD31_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x250D6 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD31_CSR TCD Control and Status 0x2519C 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 01 Reserved #01 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 5 read-write RESERVED no description available 13 1 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD31_DADDR TCD Destination Address 0x25010 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD31_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x25118 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD31_DOFF TCD Signed Destination Address Offset 0x25094 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD31_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x24F08 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD31_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x24F08 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD31_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x24F08 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset Enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD31_SADDR TCD Source Address 0x24E00 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD31_SLAST TCD Last Source Address Adjustment 0x24F8C 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD31_SOFF TCD Signed Source Address Offset 0x24E84 16 read-write n 0x0 0x0 SOFF Source Address Signed Offset 0 16 read-write TCD3_ATTR TCD Transfer Attributes 0x50DE 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 011 Reserved #011 100 16-byte burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TCD3_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x5156 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD3_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x5156 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD3_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x512E 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD3_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x512E 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD3_CSR TCD Control and Status 0x514C 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 01 Reserved #01 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 5 read-write RESERVED no description available 13 1 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD3_DADDR TCD Destination Address 0x5110 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD3_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x5138 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD3_DOFF TCD Signed Destination Address Offset 0x5124 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD3_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x50E8 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD3_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x50E8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD3_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x50E8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset Enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD3_SADDR TCD Source Address 0x50C0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD3_SLAST TCD Last Source Address Adjustment 0x50FC 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD3_SOFF TCD Signed Source Address Offset 0x50D4 16 read-write n 0x0 0x0 SOFF Source Address Signed Offset 0 16 read-write TCD4_ATTR TCD Transfer Attributes 0x6164 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 011 Reserved #011 100 16-byte burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TCD4_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x61F4 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD4_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x61F4 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD4_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x61C4 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD4_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x61C4 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD4_CSR TCD Control and Status 0x61E8 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 01 Reserved #01 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 5 read-write RESERVED no description available 13 1 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD4_DADDR TCD Destination Address 0x61A0 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD4_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x61D0 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD4_DOFF TCD Signed Destination Address Offset 0x61B8 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD4_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x6170 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD4_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x6170 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD4_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x6170 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset Enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD4_SADDR TCD Source Address 0x6140 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD4_SLAST TCD Last Source Address Adjustment 0x6188 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD4_SOFF TCD Signed Source Address Offset 0x6158 16 read-write n 0x0 0x0 SOFF Source Address Signed Offset 0 16 read-write TCD5_ATTR TCD Transfer Attributes 0x720A 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 011 Reserved #011 100 16-byte burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TCD5_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x72B2 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD5_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x72B2 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD5_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x727A 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD5_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x727A 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD5_CSR TCD Control and Status 0x72A4 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 01 Reserved #01 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 5 read-write RESERVED no description available 13 1 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD5_DADDR TCD Destination Address 0x7250 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD5_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x7288 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD5_DOFF TCD Signed Destination Address Offset 0x726C 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD5_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x7218 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD5_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x7218 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD5_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x7218 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset Enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD5_SADDR TCD Source Address 0x71E0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD5_SLAST TCD Last Source Address Adjustment 0x7234 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD5_SOFF TCD Signed Source Address Offset 0x71FC 16 read-write n 0x0 0x0 SOFF Source Address Signed Offset 0 16 read-write TCD6_ATTR TCD Transfer Attributes 0x82D0 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 011 Reserved #011 100 16-byte burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TCD6_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x8390 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD6_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x8390 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD6_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x8350 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD6_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x8350 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD6_CSR TCD Control and Status 0x8380 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 01 Reserved #01 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 5 read-write RESERVED no description available 13 1 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD6_DADDR TCD Destination Address 0x8320 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD6_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x8360 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD6_DOFF TCD Signed Destination Address Offset 0x8340 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD6_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x82E0 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD6_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x82E0 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD6_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x82E0 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset Enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD6_SADDR TCD Source Address 0x82A0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD6_SLAST TCD Last Source Address Adjustment 0x8300 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD6_SOFF TCD Signed Source Address Offset 0x82C0 16 read-write n 0x0 0x0 SOFF Source Address Signed Offset 0 16 read-write TCD7_ATTR TCD Transfer Attributes 0x93B6 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 011 Reserved #011 100 16-byte burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TCD7_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x948E 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD7_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x948E 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD7_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0x9446 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD7_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0x9446 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD7_CSR TCD Control and Status 0x947C 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 01 Reserved #01 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 5 read-write RESERVED no description available 13 1 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD7_DADDR TCD Destination Address 0x9410 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD7_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0x9458 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD7_DOFF TCD Signed Destination Address Offset 0x9434 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD7_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0x93C8 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD7_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0x93C8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD7_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0x93C8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset Enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD7_SADDR TCD Source Address 0x9380 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD7_SLAST TCD Last Source Address Adjustment 0x93EC 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD7_SOFF TCD Signed Source Address Offset 0x93A4 16 read-write n 0x0 0x0 SOFF Source Address Signed Offset 0 16 read-write TCD8_ATTR TCD Transfer Attributes 0xA4BC 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 011 Reserved #011 100 16-byte burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TCD8_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xA5AC 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD8_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xA5AC 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD8_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xA55C 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD8_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xA55C 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD8_CSR TCD Control and Status 0xA598 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 01 Reserved #01 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 5 read-write RESERVED no description available 13 1 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD8_DADDR TCD Destination Address 0xA520 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD8_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0xA570 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD8_DOFF TCD Signed Destination Address Offset 0xA548 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD8_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0xA4D0 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD8_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0xA4D0 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD8_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0xA4D0 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset Enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD8_SADDR TCD Source Address 0xA480 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD8_SLAST TCD Last Source Address Adjustment 0xA4F8 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD8_SOFF TCD Signed Source Address Offset 0xA4A8 16 read-write n 0x0 0x0 SOFF Source Address Signed Offset 0 16 read-write TCD9_ATTR TCD Transfer Attributes 0xB5E2 16 read-write n 0x0 0x0 DMOD Destination Address Modulo 3 5 read-write DSIZE Destination Data Transfer Size 0 3 read-write SMOD Source Address Modulo 11 5 read-write 0 Source address modulo feature is disabled #0 SSIZE Source data transfer size 8 3 read-write 000 8-bit #000 001 16-bit #001 010 32-bit #010 011 Reserved #011 100 16-byte burst #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 TCD9_BITER_ELINKNO TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xB6EA 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 15 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD9_BITER_ELINKYES TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xB6EA 16 read-write n 0x0 0x0 BITER Starting Major Iteration Count 0 9 read-write ELINK Enables channel-to-channel linking on minor loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD9_CITER_ELINKNO TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) DMA 0xB692 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 15 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 TCD9_CITER_ELINKYES TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) DMA 0xB692 16 read-write n 0x0 0x0 CITER Current Major Iteration Count 0 9 read-write ELINK Enable channel-to-channel linking on minor-loop complete 15 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 LINKCH Link Channel Number 9 5 read-write RESERVED no description available 14 1 read-write TCD9_CSR TCD Control and Status 0xB6D4 16 read-write n 0x0 0x0 ACTIVE Channel Active 6 1 read-write BWC Bandwidth Control 14 2 read-write 00 No eDMA engine stalls #00 01 Reserved #01 10 eDMA engine stalls for 4 cycles after each r/w #10 11 eDMA engine stalls for 8 cycles after each r/w #11 DONE Channel Done 7 1 read-write DREQ Disable Request 3 1 read-write 0 The channel's ERQ bit is not affected #0 1 The channel's ERQ bit is cleared when the major loop is complete #1 ESG Enable Scatter/Gather Processing 4 1 read-write 0 The current channel's TCD is normal format. #0 1 The current channel's TCD specifies a scatter gather format. The DLASTSGA field provides a memory pointer to the next TCD to be loaded into this channel after the major loop completes its execution. #1 INTHALF Enable an interrupt when major counter is half complete. 2 1 read-write 0 The half-point interrupt is disabled #0 1 The half-point interrupt is enabled #1 INTMAJOR Enable an interrupt when major iteration count completes 1 1 read-write 0 The end-of-major loop interrupt is disabled #0 1 The end-of-major loop interrupt is enabled #1 MAJORELINK Enable channel-to-channel linking on major loop complete 5 1 read-write 0 The channel-to-channel linking is disabled #0 1 The channel-to-channel linking is enabled #1 MAJORLINKCH Link Channel Number 8 5 read-write RESERVED no description available 13 1 read-write START Channel Start 0 1 read-write 0 The channel is not explicitly started #0 1 The channel is explicitly started via a software initiated service request #1 TCD9_DADDR TCD Destination Address 0xB650 32 read-write n 0x0 0x0 DADDR Destination Address 0 32 read-write TCD9_DLASTSGA TCD Last Destination Address Adjustment/Scatter Gather Address 0xB6A8 32 read-write n 0x0 0x0 DLASTSGA no description available 0 32 read-write TCD9_DOFF TCD Signed Destination Address Offset 0xB67C 16 read-write n 0x0 0x0 DOFF Destination Address Signed Offset 0 16 read-write TCD9_NBYTES_MLNO TCD Minor Byte Count (Minor Loop Disabled) DMA 0xB5F8 32 read-write n 0x0 0x0 NBYTES Minor Byte Transfer Count 0 32 read-write TCD9_NBYTES_MLOFFNO TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) DMA 0xB5F8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 NBYTES Minor Byte Transfer Count 0 30 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD9_NBYTES_MLOFFYES TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) DMA 0xB5F8 32 read-write n 0x0 0x0 DMLOE Destination Minor Loop Offset Enable 30 1 read-write 0 The minor loop offset is not applied to the DADDR #0 1 The minor loop offset is applied to the DADDR #1 MLOFF If SMLOE or DMLOE is set, this field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop completes. 10 20 read-write NBYTES Minor Byte Transfer Count 0 10 read-write SMLOE Source Minor Loop Offset Enable 31 1 read-write 0 The minor loop offset is not applied to the SADDR #0 1 The minor loop offset is applied to the SADDR #1 TCD9_SADDR TCD Source Address 0xB5A0 32 read-write n 0x0 0x0 SADDR Source Address 0 32 read-write TCD9_SLAST TCD Last Source Address Adjustment 0xB624 32 read-write n 0x0 0x0 SLAST Last Source Address Adjustment 0 32 read-write TCD9_SOFF TCD Signed Source Address Offset 0xB5CC 16 read-write n 0x0 0x0 SOFF Source Address Signed Offset 0 16 read-write DMAMUX0 DMA channel multiplexor DMAMUX 0x0 0x0 0x10 registers n CHCFG0 Channel Configuration Register 0x0 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG1 Channel Configuration Register 0x1 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG10 Channel Configuration Register 0x37 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG11 Channel Configuration Register 0x42 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG12 Channel Configuration Register 0x4E 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG13 Channel Configuration Register 0x5B 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG14 Channel Configuration Register 0x69 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG15 Channel Configuration Register 0x78 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG2 Channel Configuration Register 0x3 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG3 Channel Configuration Register 0x6 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG4 Channel Configuration Register 0xA 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG5 Channel Configuration Register 0xF 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG6 Channel Configuration Register 0x15 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG7 Channel Configuration Register 0x1C 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG8 Channel Configuration Register 0x24 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG9 Channel Configuration Register 0x2D 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 DMAMUX1 DMA channel multiplexor DMAMUX 0x0 0x0 0x10 registers n CHCFG0 Channel Configuration Register 0x0 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG1 Channel Configuration Register 0x1 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG10 Channel Configuration Register 0x37 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG11 Channel Configuration Register 0x42 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG12 Channel Configuration Register 0x4E 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG13 Channel Configuration Register 0x5B 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG14 Channel Configuration Register 0x69 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG15 Channel Configuration Register 0x78 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG2 Channel Configuration Register 0x3 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG3 Channel Configuration Register 0x6 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG4 Channel Configuration Register 0xA 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG5 Channel Configuration Register 0xF 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG6 Channel Configuration Register 0x15 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG7 Channel Configuration Register 0x1C 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG8 Channel Configuration Register 0x24 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 CHCFG9 Channel Configuration Register 0x2D 8 read-write n 0x0 0x0 ENBL DMA Channel Enable 7 1 read-write 0 DMA channel is disabled. This mode is primarily used during configuration of the DMA Mux. The DMA has separate channel enables/disables, which should be used to disable or re-configure a DMA channel. #0 1 DMA channel is enabled #1 SOURCE DMA Channel Source (slot) 0 6 read-write TRIG DMA Channel Trigger Enable 6 1 read-write 0 Triggering is disabled. If triggering is disabled, and the ENBL bit is set, the DMA Channel will simply route the specified source to the DMA channel. (normal mode) #0 1 Triggering is enabled. If triggering is enabled, and the ENBL bit is set, the DMAMUX is in periodic trigger mode. #1 EWM External Watchdog Monitor EWM 0x0 0x0 0x4 registers n Watchdog 22 INT_Watchdog 38 CMPH Compare High Register 0x3 8 read-write n 0x0 0x0 COMPAREH no description available 0 8 read-write CMPL Compare Low Register 0x2 8 read-write n 0x0 0x0 COMPAREL no description available 0 8 read-write CTRL Control Register 0x0 8 read-write n 0x0 0x0 ASSIN EWM_in's Assertion State Select. 1 1 read-write EWMEN EWM enable. 0 1 read-write INEN Input Enable. 2 1 read-write INTEN Interrupt Enable. 3 1 read-write RESERVED no description available 4 4 read-only SERV Service Register 0x1 8 write-only n 0x0 0x0 SERVICE no description available 0 8 write-only FB FlexBus external bus interface FB 0x0 0x0 0x64 registers n CSAR0 Chip select address register 0x0 32 read-write n 0x0 0x0 BA Base address 16 16 read-write RESERVED no description available 0 16 read-only CSAR1 Chip select address register 0xC 32 read-write n 0x0 0x0 BA Base address 16 16 read-write RESERVED no description available 0 16 read-only CSAR2 Chip select address register 0x24 32 read-write n 0x0 0x0 BA Base address 16 16 read-write RESERVED no description available 0 16 read-only CSAR3 Chip select address register 0x48 32 read-write n 0x0 0x0 BA Base address 16 16 read-write RESERVED no description available 0 16 read-only CSAR4 Chip select address register 0x78 32 read-write n 0x0 0x0 BA Base address 16 16 read-write RESERVED no description available 0 16 read-only CSAR5 Chip select address register 0xB4 32 read-write n 0x0 0x0 BA Base address 16 16 read-write RESERVED no description available 0 16 read-only CSCR0 Chip select control register 0x10 32 read-write n 0x0 0x0 AA Auto-acknowledge enable 8 1 read-write 0 No internal FB_TA is asserted. Cycle is terminated externally #0 1 Internal transfer acknowledge is asserted as specified by WS #1 ASET Address setup 20 2 read-write 00 Assert FB_CSn on first rising clock edge after address is asserted. (Default FB_CSn) #00 01 Assert FB_CSn on second rising clock edge after address is asserted. #01 10 Assert FB_CSn on third rising clock edge after address is asserted. #10 11 Assert FB_CSn on fourth rising clock edge after address is asserted. (Default FB_CS0) #11 BEM Byte-enable mode 5 1 read-write 0 The FB_BE n signals are not asserted for reads. The FB_BE n signals are asserted for data write only. #0 1 The FB_BE n signals are asserted for read and write accesses #1 BLS Byte-lane shift 9 1 read-write 0 Not shifted. Data is left-justfied on FB_AD. #0 1 Shifted. Data is right justified on FB_AD. #1 BSTR Burst-read enable 4 1 read-write 0 Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a longword read from an 8-bit port is broken into four 8-bit reads. #0 1 Enables data burst reads larger than the specified port size, including longword reads from 8- and 16-bit ports, word reads from 8-bit ports, and line reads from 8, 16-, and 32-bit ports. #1 BSTW Burst-write enable 3 1 read-write 0 Break data larger than the specified port size into individual, port-sized, non-burst writes. For example, a longword write to an 8-bit port takes four byte writes. #0 1 Enables burst write of data larger than the specified port size, including longword writes to 8 and 16-bit ports, word writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. #1 EXTS no description available 22 1 read-write 0 FB_TS /FB_ALE asserts for one bus clock cycle #0 1 FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts #1 PS Port size 6 2 read-write 00 32-bit port size. Valid data sampled and driven on FB_D[31:0] #00 01 8-bit port size. Valid data sampled and driven on FB_D[31:24] if BLS = 0 or FB_D[7:0] if BLS = 1 #01 10 16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1 #10 11 16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1 #11 RDAH Read address hold or deselect 18 2 read-write 00 If AA is cleared, 1 cycle. If AA is set, 0 cycles. #00 01 If AA is cleared, 2 cycles. If AA is set, 1 cycle. #01 10 If AA is cleared, 3 cycles. If AA is set, 2 cycles. #10 11 If AA is cleared, 4 cycles. If AA is set, 3 cycles. #11 RESERVED no description available 0 3 read-only RESERVED no description available 24 2 read-only SWS Secondary wait states 26 6 read-write SWSEN Secondary wait state enable 23 1 read-write 0 The WS value inserts wait states before an internal transfer acknowledge is generated for all transfers #0 1 The SWS value inserts wait states before an internal transfer acknowledge is generated for burst transfer secondary terminations #1 WRAH Write address hold or deselect 16 2 read-write 00 Hold address and attributes one cycle after FB_CSn negates on writes. (Default FB_CSn) #00 01 Hold address and attributes two cycles after FB_CSn negates on writes. #01 10 Hold address and attributes three cycles after FB_CSn negates on writes. #10 11 Hold address and attributes four cycles after FB_CSn negates on writes. (Default FB_CS0) #11 WS Wait states 10 6 read-write CSCR1 Chip select control register 0x24 32 read-write n 0x0 0x0 AA Auto-acknowledge enable 8 1 read-write 0 No internal FB_TA is asserted. Cycle is terminated externally #0 1 Internal transfer acknowledge is asserted as specified by WS #1 ASET Address setup 20 2 read-write 00 Assert FB_CSn on first rising clock edge after address is asserted. (Default FB_CSn) #00 01 Assert FB_CSn on second rising clock edge after address is asserted. #01 10 Assert FB_CSn on third rising clock edge after address is asserted. #10 11 Assert FB_CSn on fourth rising clock edge after address is asserted. (Default FB_CS0) #11 BEM Byte-enable mode 5 1 read-write 0 The FB_BE n signals are not asserted for reads. The FB_BE n signals are asserted for data write only. #0 1 The FB_BE n signals are asserted for read and write accesses #1 BLS Byte-lane shift 9 1 read-write 0 Not shifted. Data is left-justfied on FB_AD. #0 1 Shifted. Data is right justified on FB_AD. #1 BSTR Burst-read enable 4 1 read-write 0 Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a longword read from an 8-bit port is broken into four 8-bit reads. #0 1 Enables data burst reads larger than the specified port size, including longword reads from 8- and 16-bit ports, word reads from 8-bit ports, and line reads from 8, 16-, and 32-bit ports. #1 BSTW Burst-write enable 3 1 read-write 0 Break data larger than the specified port size into individual, port-sized, non-burst writes. For example, a longword write to an 8-bit port takes four byte writes. #0 1 Enables burst write of data larger than the specified port size, including longword writes to 8 and 16-bit ports, word writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. #1 EXTS no description available 22 1 read-write 0 FB_TS /FB_ALE asserts for one bus clock cycle #0 1 FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts #1 PS Port size 6 2 read-write 00 32-bit port size. Valid data sampled and driven on FB_D[31:0] #00 01 8-bit port size. Valid data sampled and driven on FB_D[31:24] if BLS = 0 or FB_D[7:0] if BLS = 1 #01 10 16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1 #10 11 16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1 #11 RDAH Read address hold or deselect 18 2 read-write 00 If AA is cleared, 1 cycle. If AA is set, 0 cycles. #00 01 If AA is cleared, 2 cycles. If AA is set, 1 cycle. #01 10 If AA is cleared, 3 cycles. If AA is set, 2 cycles. #10 11 If AA is cleared, 4 cycles. If AA is set, 3 cycles. #11 RESERVED no description available 0 3 read-only RESERVED no description available 24 2 read-only SWS Secondary wait states 26 6 read-write SWSEN Secondary wait state enable 23 1 read-write 0 The WS value inserts wait states before an internal transfer acknowledge is generated for all transfers #0 1 The SWS value inserts wait states before an internal transfer acknowledge is generated for burst transfer secondary terminations #1 WRAH Write address hold or deselect 16 2 read-write 00 Hold address and attributes one cycle after FB_CSn negates on writes. (Default FB_CSn) #00 01 Hold address and attributes two cycles after FB_CSn negates on writes. #01 10 Hold address and attributes three cycles after FB_CSn negates on writes. #10 11 Hold address and attributes four cycles after FB_CSn negates on writes. (Default FB_CS0) #11 WS Wait states 10 6 read-write CSCR2 Chip select control register 0x44 32 read-write n 0x0 0x0 AA Auto-acknowledge enable 8 1 read-write 0 No internal FB_TA is asserted. Cycle is terminated externally #0 1 Internal transfer acknowledge is asserted as specified by WS #1 ASET Address setup 20 2 read-write 00 Assert FB_CSn on first rising clock edge after address is asserted. (Default FB_CSn) #00 01 Assert FB_CSn on second rising clock edge after address is asserted. #01 10 Assert FB_CSn on third rising clock edge after address is asserted. #10 11 Assert FB_CSn on fourth rising clock edge after address is asserted. (Default FB_CS0) #11 BEM Byte-enable mode 5 1 read-write 0 The FB_BE n signals are not asserted for reads. The FB_BE n signals are asserted for data write only. #0 1 The FB_BE n signals are asserted for read and write accesses #1 BLS Byte-lane shift 9 1 read-write 0 Not shifted. Data is left-justfied on FB_AD. #0 1 Shifted. Data is right justified on FB_AD. #1 BSTR Burst-read enable 4 1 read-write 0 Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a longword read from an 8-bit port is broken into four 8-bit reads. #0 1 Enables data burst reads larger than the specified port size, including longword reads from 8- and 16-bit ports, word reads from 8-bit ports, and line reads from 8, 16-, and 32-bit ports. #1 BSTW Burst-write enable 3 1 read-write 0 Break data larger than the specified port size into individual, port-sized, non-burst writes. For example, a longword write to an 8-bit port takes four byte writes. #0 1 Enables burst write of data larger than the specified port size, including longword writes to 8 and 16-bit ports, word writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. #1 EXTS no description available 22 1 read-write 0 FB_TS /FB_ALE asserts for one bus clock cycle #0 1 FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts #1 PS Port size 6 2 read-write 00 32-bit port size. Valid data sampled and driven on FB_D[31:0] #00 01 8-bit port size. Valid data sampled and driven on FB_D[31:24] if BLS = 0 or FB_D[7:0] if BLS = 1 #01 10 16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1 #10 11 16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1 #11 RDAH Read address hold or deselect 18 2 read-write 00 If AA is cleared, 1 cycle. If AA is set, 0 cycles. #00 01 If AA is cleared, 2 cycles. If AA is set, 1 cycle. #01 10 If AA is cleared, 3 cycles. If AA is set, 2 cycles. #10 11 If AA is cleared, 4 cycles. If AA is set, 3 cycles. #11 RESERVED no description available 0 3 read-only RESERVED no description available 24 2 read-only SWS Secondary wait states 26 6 read-write SWSEN Secondary wait state enable 23 1 read-write 0 The WS value inserts wait states before an internal transfer acknowledge is generated for all transfers #0 1 The SWS value inserts wait states before an internal transfer acknowledge is generated for burst transfer secondary terminations #1 WRAH Write address hold or deselect 16 2 read-write 00 Hold address and attributes one cycle after FB_CSn negates on writes. (Default FB_CSn) #00 01 Hold address and attributes two cycles after FB_CSn negates on writes. #01 10 Hold address and attributes three cycles after FB_CSn negates on writes. #10 11 Hold address and attributes four cycles after FB_CSn negates on writes. (Default FB_CS0) #11 WS Wait states 10 6 read-write CSCR3 Chip select control register 0x70 32 read-write n 0x0 0x0 AA Auto-acknowledge enable 8 1 read-write 0 No internal FB_TA is asserted. Cycle is terminated externally #0 1 Internal transfer acknowledge is asserted as specified by WS #1 ASET Address setup 20 2 read-write 00 Assert FB_CSn on first rising clock edge after address is asserted. (Default FB_CSn) #00 01 Assert FB_CSn on second rising clock edge after address is asserted. #01 10 Assert FB_CSn on third rising clock edge after address is asserted. #10 11 Assert FB_CSn on fourth rising clock edge after address is asserted. (Default FB_CS0) #11 BEM Byte-enable mode 5 1 read-write 0 The FB_BE n signals are not asserted for reads. The FB_BE n signals are asserted for data write only. #0 1 The FB_BE n signals are asserted for read and write accesses #1 BLS Byte-lane shift 9 1 read-write 0 Not shifted. Data is left-justfied on FB_AD. #0 1 Shifted. Data is right justified on FB_AD. #1 BSTR Burst-read enable 4 1 read-write 0 Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a longword read from an 8-bit port is broken into four 8-bit reads. #0 1 Enables data burst reads larger than the specified port size, including longword reads from 8- and 16-bit ports, word reads from 8-bit ports, and line reads from 8, 16-, and 32-bit ports. #1 BSTW Burst-write enable 3 1 read-write 0 Break data larger than the specified port size into individual, port-sized, non-burst writes. For example, a longword write to an 8-bit port takes four byte writes. #0 1 Enables burst write of data larger than the specified port size, including longword writes to 8 and 16-bit ports, word writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. #1 EXTS no description available 22 1 read-write 0 FB_TS /FB_ALE asserts for one bus clock cycle #0 1 FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts #1 PS Port size 6 2 read-write 00 32-bit port size. Valid data sampled and driven on FB_D[31:0] #00 01 8-bit port size. Valid data sampled and driven on FB_D[31:24] if BLS = 0 or FB_D[7:0] if BLS = 1 #01 10 16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1 #10 11 16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1 #11 RDAH Read address hold or deselect 18 2 read-write 00 If AA is cleared, 1 cycle. If AA is set, 0 cycles. #00 01 If AA is cleared, 2 cycles. If AA is set, 1 cycle. #01 10 If AA is cleared, 3 cycles. If AA is set, 2 cycles. #10 11 If AA is cleared, 4 cycles. If AA is set, 3 cycles. #11 RESERVED no description available 0 3 read-only RESERVED no description available 24 2 read-only SWS Secondary wait states 26 6 read-write SWSEN Secondary wait state enable 23 1 read-write 0 The WS value inserts wait states before an internal transfer acknowledge is generated for all transfers #0 1 The SWS value inserts wait states before an internal transfer acknowledge is generated for burst transfer secondary terminations #1 WRAH Write address hold or deselect 16 2 read-write 00 Hold address and attributes one cycle after FB_CSn negates on writes. (Default FB_CSn) #00 01 Hold address and attributes two cycles after FB_CSn negates on writes. #01 10 Hold address and attributes three cycles after FB_CSn negates on writes. #10 11 Hold address and attributes four cycles after FB_CSn negates on writes. (Default FB_CS0) #11 WS Wait states 10 6 read-write CSCR4 Chip select control register 0xA8 32 read-write n 0x0 0x0 AA Auto-acknowledge enable 8 1 read-write 0 No internal FB_TA is asserted. Cycle is terminated externally #0 1 Internal transfer acknowledge is asserted as specified by WS #1 ASET Address setup 20 2 read-write 00 Assert FB_CSn on first rising clock edge after address is asserted. (Default FB_CSn) #00 01 Assert FB_CSn on second rising clock edge after address is asserted. #01 10 Assert FB_CSn on third rising clock edge after address is asserted. #10 11 Assert FB_CSn on fourth rising clock edge after address is asserted. (Default FB_CS0) #11 BEM Byte-enable mode 5 1 read-write 0 The FB_BE n signals are not asserted for reads. The FB_BE n signals are asserted for data write only. #0 1 The FB_BE n signals are asserted for read and write accesses #1 BLS Byte-lane shift 9 1 read-write 0 Not shifted. Data is left-justfied on FB_AD. #0 1 Shifted. Data is right justified on FB_AD. #1 BSTR Burst-read enable 4 1 read-write 0 Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a longword read from an 8-bit port is broken into four 8-bit reads. #0 1 Enables data burst reads larger than the specified port size, including longword reads from 8- and 16-bit ports, word reads from 8-bit ports, and line reads from 8, 16-, and 32-bit ports. #1 BSTW Burst-write enable 3 1 read-write 0 Break data larger than the specified port size into individual, port-sized, non-burst writes. For example, a longword write to an 8-bit port takes four byte writes. #0 1 Enables burst write of data larger than the specified port size, including longword writes to 8 and 16-bit ports, word writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. #1 EXTS no description available 22 1 read-write 0 FB_TS /FB_ALE asserts for one bus clock cycle #0 1 FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts #1 PS Port size 6 2 read-write 00 32-bit port size. Valid data sampled and driven on FB_D[31:0] #00 01 8-bit port size. Valid data sampled and driven on FB_D[31:24] if BLS = 0 or FB_D[7:0] if BLS = 1 #01 10 16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1 #10 11 16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1 #11 RDAH Read address hold or deselect 18 2 read-write 00 If AA is cleared, 1 cycle. If AA is set, 0 cycles. #00 01 If AA is cleared, 2 cycles. If AA is set, 1 cycle. #01 10 If AA is cleared, 3 cycles. If AA is set, 2 cycles. #10 11 If AA is cleared, 4 cycles. If AA is set, 3 cycles. #11 RESERVED no description available 0 3 read-only RESERVED no description available 24 2 read-only SWS Secondary wait states 26 6 read-write SWSEN Secondary wait state enable 23 1 read-write 0 The WS value inserts wait states before an internal transfer acknowledge is generated for all transfers #0 1 The SWS value inserts wait states before an internal transfer acknowledge is generated for burst transfer secondary terminations #1 WRAH Write address hold or deselect 16 2 read-write 00 Hold address and attributes one cycle after FB_CSn negates on writes. (Default FB_CSn) #00 01 Hold address and attributes two cycles after FB_CSn negates on writes. #01 10 Hold address and attributes three cycles after FB_CSn negates on writes. #10 11 Hold address and attributes four cycles after FB_CSn negates on writes. (Default FB_CS0) #11 WS Wait states 10 6 read-write CSCR5 Chip select control register 0xEC 32 read-write n 0x0 0x0 AA Auto-acknowledge enable 8 1 read-write 0 No internal FB_TA is asserted. Cycle is terminated externally #0 1 Internal transfer acknowledge is asserted as specified by WS #1 ASET Address setup 20 2 read-write 00 Assert FB_CSn on first rising clock edge after address is asserted. (Default FB_CSn) #00 01 Assert FB_CSn on second rising clock edge after address is asserted. #01 10 Assert FB_CSn on third rising clock edge after address is asserted. #10 11 Assert FB_CSn on fourth rising clock edge after address is asserted. (Default FB_CS0) #11 BEM Byte-enable mode 5 1 read-write 0 The FB_BE n signals are not asserted for reads. The FB_BE n signals are asserted for data write only. #0 1 The FB_BE n signals are asserted for read and write accesses #1 BLS Byte-lane shift 9 1 read-write 0 Not shifted. Data is left-justfied on FB_AD. #0 1 Shifted. Data is right justified on FB_AD. #1 BSTR Burst-read enable 4 1 read-write 0 Data exceeding the specified port size is broken into individual, port-sized, non-burst reads. For example, a longword read from an 8-bit port is broken into four 8-bit reads. #0 1 Enables data burst reads larger than the specified port size, including longword reads from 8- and 16-bit ports, word reads from 8-bit ports, and line reads from 8, 16-, and 32-bit ports. #1 BSTW Burst-write enable 3 1 read-write 0 Break data larger than the specified port size into individual, port-sized, non-burst writes. For example, a longword write to an 8-bit port takes four byte writes. #0 1 Enables burst write of data larger than the specified port size, including longword writes to 8 and 16-bit ports, word writes to 8-bit ports, and line writes to 8-, 16-, and 32-bit ports. #1 EXTS no description available 22 1 read-write 0 FB_TS /FB_ALE asserts for one bus clock cycle #0 1 FB_TS /FB_ALE remains asserted until the first positive clock edge after FB_CSn asserts #1 PS Port size 6 2 read-write 00 32-bit port size. Valid data sampled and driven on FB_D[31:0] #00 01 8-bit port size. Valid data sampled and driven on FB_D[31:24] if BLS = 0 or FB_D[7:0] if BLS = 1 #01 10 16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1 #10 11 16-bit port size. Valid data sampled and driven on FB_D[31:16] if BLS = 0 or FB_D[15:0] if BLS = 1 #11 RDAH Read address hold or deselect 18 2 read-write 00 If AA is cleared, 1 cycle. If AA is set, 0 cycles. #00 01 If AA is cleared, 2 cycles. If AA is set, 1 cycle. #01 10 If AA is cleared, 3 cycles. If AA is set, 2 cycles. #10 11 If AA is cleared, 4 cycles. If AA is set, 3 cycles. #11 RESERVED no description available 0 3 read-only RESERVED no description available 24 2 read-only SWS Secondary wait states 26 6 read-write SWSEN Secondary wait state enable 23 1 read-write 0 The WS value inserts wait states before an internal transfer acknowledge is generated for all transfers #0 1 The SWS value inserts wait states before an internal transfer acknowledge is generated for burst transfer secondary terminations #1 WRAH Write address hold or deselect 16 2 read-write 00 Hold address and attributes one cycle after FB_CSn negates on writes. (Default FB_CSn) #00 01 Hold address and attributes two cycles after FB_CSn negates on writes. #01 10 Hold address and attributes three cycles after FB_CSn negates on writes. #10 11 Hold address and attributes four cycles after FB_CSn negates on writes. (Default FB_CS0) #11 WS Wait states 10 6 read-write CSMR0 Chip select mask register 0x8 32 read-write n 0x0 0x0 BAM Base address mask 16 16 read-write 0 Corresponding address bit is used in chip-select decode #0 1 Corresponding address bit is a don't care in chip-select decode. #1 RESERVED no description available 1 7 read-only RESERVED no description available 9 7 read-only V Valid 0 1 read-write 0 Chip select invalid #0 1 Chip select valid #1 WP Write protect 8 1 read-write 0 Read and write accesses are allowed #0 1 Only read accesses are allowed #1 CSMR1 Chip select mask register 0x18 32 read-write n 0x0 0x0 BAM Base address mask 16 16 read-write 0 Corresponding address bit is used in chip-select decode #0 1 Corresponding address bit is a don't care in chip-select decode. #1 RESERVED no description available 1 7 read-only RESERVED no description available 9 7 read-only V Valid 0 1 read-write 0 Chip select invalid #0 1 Chip select valid #1 WP Write protect 8 1 read-write 0 Read and write accesses are allowed #0 1 Only read accesses are allowed #1 CSMR2 Chip select mask register 0x34 32 read-write n 0x0 0x0 BAM Base address mask 16 16 read-write 0 Corresponding address bit is used in chip-select decode #0 1 Corresponding address bit is a don't care in chip-select decode. #1 RESERVED no description available 1 7 read-only RESERVED no description available 9 7 read-only V Valid 0 1 read-write 0 Chip select invalid #0 1 Chip select valid #1 WP Write protect 8 1 read-write 0 Read and write accesses are allowed #0 1 Only read accesses are allowed #1 CSMR3 Chip select mask register 0x5C 32 read-write n 0x0 0x0 BAM Base address mask 16 16 read-write 0 Corresponding address bit is used in chip-select decode #0 1 Corresponding address bit is a don't care in chip-select decode. #1 RESERVED no description available 1 7 read-only RESERVED no description available 9 7 read-only V Valid 0 1 read-write 0 Chip select invalid #0 1 Chip select valid #1 WP Write protect 8 1 read-write 0 Read and write accesses are allowed #0 1 Only read accesses are allowed #1 CSMR4 Chip select mask register 0x90 32 read-write n 0x0 0x0 BAM Base address mask 16 16 read-write 0 Corresponding address bit is used in chip-select decode #0 1 Corresponding address bit is a don't care in chip-select decode. #1 RESERVED no description available 1 7 read-only RESERVED no description available 9 7 read-only V Valid 0 1 read-write 0 Chip select invalid #0 1 Chip select valid #1 WP Write protect 8 1 read-write 0 Read and write accesses are allowed #0 1 Only read accesses are allowed #1 CSMR5 Chip select mask register 0xD0 32 read-write n 0x0 0x0 BAM Base address mask 16 16 read-write 0 Corresponding address bit is used in chip-select decode #0 1 Corresponding address bit is a don't care in chip-select decode. #1 RESERVED no description available 1 7 read-only RESERVED no description available 9 7 read-only V Valid 0 1 read-write 0 Chip select invalid #0 1 Chip select valid #1 WP Write protect 8 1 read-write 0 Read and write accesses are allowed #0 1 Only read accesses are allowed #1 CSPMCR Chip select port multiplexing control register 0x60 32 read-write n 0x0 0x0 GROUP1 FlexBus signal group 1 multiplex control 28 4 read-write 0000 FB_ALE #0000 0001 FB_CS1 #0001 0010 FB_TS #0010 GROUP2 FlexBus signal group 2 multiplex control 24 4 read-write 0000 FB_CS4 #0000 0001 FB_TSIZ0 #0001 0010 FB_BE_31_24 #0010 GROUP3 FlexBus signal group 3 multiplex control 20 4 read-write 0000 FB_CS5 #0000 0001 FB_TSIZ1 #0001 0010 FB_BE_23_16 #0010 GROUP4 FlexBus signal group 4 multiplex control 16 4 read-write 0000 FB_TBST #0000 0001 FB_CS2 #0001 0010 FB_BE_15_8 #0010 GROUP5 FlexBus signal group 5 multiplex control 12 4 read-write 0000 FB_TA #0000 0001 FB_CS3. You must also set CSCRn[AA]. #0001 0010 FB_BE_7_0. You must also set CSCRn[AA]. #0010 RESERVED no description available 0 12 read-only FMC Flash Memory Controller FMC 0x0 0x0 0x300 registers n DATAW0S0LM Cache Data Storage (lowermost word) 0x418 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW0S0ML Cache Data Storage (mid-lower word) 0x410 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW0S0MU Cache Data Storage (mid-upper word) 0x408 32 read-write n 0x0 0x0 data Bits [95:64] of data entry 0 32 read-write DATAW0S0UM Cache Data Storage (uppermost word) 0x400 32 read-write n 0x0 0x0 data Bits [127:96] of data entry 0 32 read-write DATAW0S1LM Cache Data Storage (lowermost word) 0x634 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW0S1ML Cache Data Storage (mid-lower word) 0x628 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW0S1MU Cache Data Storage (mid-upper word) 0x61C 32 read-write n 0x0 0x0 data Bits [95:64] of data entry 0 32 read-write DATAW0S1UM Cache Data Storage (uppermost word) 0x610 32 read-write n 0x0 0x0 data Bits [127:96] of data entry 0 32 read-write DATAW0S2LM Cache Data Storage (lowermost word) 0x860 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW0S2ML Cache Data Storage (mid-lower word) 0x850 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW0S2MU Cache Data Storage (mid-upper word) 0x840 32 read-write n 0x0 0x0 data Bits [95:64] of data entry 0 32 read-write DATAW0S2UM Cache Data Storage (uppermost word) 0x830 32 read-write n 0x0 0x0 data Bits [127:96] of data entry 0 32 read-write DATAW0S3LM Cache Data Storage (lowermost word) 0xA9C 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW0S3ML Cache Data Storage (mid-lower word) 0xA88 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW0S3MU Cache Data Storage (mid-upper word) 0xA74 32 read-write n 0x0 0x0 data Bits [95:64] of data entry 0 32 read-write DATAW0S3UM Cache Data Storage (uppermost word) 0xA60 32 read-write n 0x0 0x0 data Bits [127:96] of data entry 0 32 read-write DATAW1S0LM Cache Data Storage (lowermost word) 0x498 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW1S0ML Cache Data Storage (mid-lower word) 0x490 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW1S0MU Cache Data Storage (mid-upper word) 0x488 32 read-write n 0x0 0x0 data Bits [95:64] of data entry 0 32 read-write DATAW1S0UM Cache Data Storage (uppermost word) 0x480 32 read-write n 0x0 0x0 data Bits [127:96] of data entry 0 32 read-write DATAW1S1LM Cache Data Storage (lowermost word) 0x6F4 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW1S1ML Cache Data Storage (mid-lower word) 0x6E8 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW1S1MU Cache Data Storage (mid-upper word) 0x6DC 32 read-write n 0x0 0x0 data Bits [95:64] of data entry 0 32 read-write DATAW1S1UM Cache Data Storage (uppermost word) 0x6D0 32 read-write n 0x0 0x0 data Bits [127:96] of data entry 0 32 read-write DATAW1S2LM Cache Data Storage (lowermost word) 0x960 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW1S2ML Cache Data Storage (mid-lower word) 0x950 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW1S2MU Cache Data Storage (mid-upper word) 0x940 32 read-write n 0x0 0x0 data Bits [95:64] of data entry 0 32 read-write DATAW1S2UM Cache Data Storage (uppermost word) 0x930 32 read-write n 0x0 0x0 data Bits [127:96] of data entry 0 32 read-write DATAW1S3LM Cache Data Storage (lowermost word) 0xBDC 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW1S3ML Cache Data Storage (mid-lower word) 0xBC8 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW1S3MU Cache Data Storage (mid-upper word) 0xBB4 32 read-write n 0x0 0x0 data Bits [95:64] of data entry 0 32 read-write DATAW1S3UM Cache Data Storage (uppermost word) 0xBA0 32 read-write n 0x0 0x0 data Bits [127:96] of data entry 0 32 read-write DATAW2S0LM Cache Data Storage (lowermost word) 0x518 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW2S0ML Cache Data Storage (mid-lower word) 0x510 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW2S0MU Cache Data Storage (mid-upper word) 0x508 32 read-write n 0x0 0x0 data Bits [95:64] of data entry 0 32 read-write DATAW2S0UM Cache Data Storage (uppermost word) 0x500 32 read-write n 0x0 0x0 data Bits [127:96] of data entry 0 32 read-write DATAW2S1LM Cache Data Storage (lowermost word) 0x7B4 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW2S1ML Cache Data Storage (mid-lower word) 0x7A8 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW2S1MU Cache Data Storage (mid-upper word) 0x79C 32 read-write n 0x0 0x0 data Bits [95:64] of data entry 0 32 read-write DATAW2S1UM Cache Data Storage (uppermost word) 0x790 32 read-write n 0x0 0x0 data Bits [127:96] of data entry 0 32 read-write DATAW2S2LM Cache Data Storage (lowermost word) 0xA60 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW2S2ML Cache Data Storage (mid-lower word) 0xA50 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW2S2MU Cache Data Storage (mid-upper word) 0xA40 32 read-write n 0x0 0x0 data Bits [95:64] of data entry 0 32 read-write DATAW2S2UM Cache Data Storage (uppermost word) 0xA30 32 read-write n 0x0 0x0 data Bits [127:96] of data entry 0 32 read-write DATAW2S3LM Cache Data Storage (lowermost word) 0xD1C 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW2S3ML Cache Data Storage (mid-lower word) 0xD08 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW2S3MU Cache Data Storage (mid-upper word) 0xCF4 32 read-write n 0x0 0x0 data Bits [95:64] of data entry 0 32 read-write DATAW2S3UM Cache Data Storage (uppermost word) 0xCE0 32 read-write n 0x0 0x0 data Bits [127:96] of data entry 0 32 read-write DATAW3S0LM Cache Data Storage (lowermost word) 0x598 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW3S0ML Cache Data Storage (mid-lower word) 0x590 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW3S0MU Cache Data Storage (mid-upper word) 0x588 32 read-write n 0x0 0x0 data Bits [95:64] of data entry 0 32 read-write DATAW3S0UM Cache Data Storage (uppermost word) 0x580 32 read-write n 0x0 0x0 data Bits [127:96] of data entry 0 32 read-write DATAW3S1LM Cache Data Storage (lowermost word) 0x874 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW3S1ML Cache Data Storage (mid-lower word) 0x868 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW3S1MU Cache Data Storage (mid-upper word) 0x85C 32 read-write n 0x0 0x0 data Bits [95:64] of data entry 0 32 read-write DATAW3S1UM Cache Data Storage (uppermost word) 0x850 32 read-write n 0x0 0x0 data Bits [127:96] of data entry 0 32 read-write DATAW3S2LM Cache Data Storage (lowermost word) 0xB60 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW3S2ML Cache Data Storage (mid-lower word) 0xB50 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW3S2MU Cache Data Storage (mid-upper word) 0xB40 32 read-write n 0x0 0x0 data Bits [95:64] of data entry 0 32 read-write DATAW3S2UM Cache Data Storage (uppermost word) 0xB30 32 read-write n 0x0 0x0 data Bits [127:96] of data entry 0 32 read-write DATAW3S3LM Cache Data Storage (lowermost word) 0xE5C 32 read-write n 0x0 0x0 data Bits [31:0] of data entry 0 32 read-write DATAW3S3ML Cache Data Storage (mid-lower word) 0xE48 32 read-write n 0x0 0x0 data Bits [63:32] of data entry 0 32 read-write DATAW3S3MU Cache Data Storage (mid-upper word) 0xE34 32 read-write n 0x0 0x0 data Bits [95:64] of data entry 0 32 read-write DATAW3S3UM Cache Data Storage (uppermost word) 0xE20 32 read-write n 0x0 0x0 data Bits [127:96] of data entry 0 32 read-write PFAPR Flash Access Protection Register 0x0 32 read-write n 0x0 0x0 M0AP Master 0 Access Protection 0 2 read-write 00 No access may be performed by this master #00 01 Only read accesses may be performed by this master #01 10 Only write accesses may be performed by this master #10 11 Both read and write accesses may be performed by this master #11 M0PFD Master 0 Prefetch Disable 16 1 read-write 0 Prefetching for this master is enabled. #0 1 Prefetching for this master is disabled. #1 M1AP Master 1 Access Protection 2 2 read-write 00 No access may be performed by this master #00 01 Only read accesses may be performed by this master #01 10 Only write accesses may be performed by this master #10 11 Both read and write accesses may be performed by this master #11 M1PFD Master 1 Prefetch Disable 17 1 read-write 0 Prefetching for this master is enabled. #0 1 Prefetching for this master is disabled. #1 M2AP Master 2 Access Protection 4 2 read-write 00 No access may be performed by this master #00 01 Only read accesses may be performed by this master #01 10 Only write accesses may be performed by this master #10 11 Both read and write accesses may be performed by this master #11 M2PFD Master 2 Prefetch Disable 18 1 read-write 0 Prefetching for this master is enabled. #0 1 Prefetching for this master is disabled. #1 M3AP Master 3 Access Protection 6 2 read-write 00 No access may be performed by this master #00 01 Only read accesses may be performed by this master #01 10 Only write accesses may be performed by this master #10 11 Both read and write accesses may be performed by this master #11 M3PFD Master 3 Prefetch Disable 19 1 read-write 0 Prefetching for this master is enabled. #0 1 Prefetching for this master is disabled. #1 M4AP Master 4 Access Protection 8 2 read-write 00 No access may be performed by this master #00 01 Only read accesses may be performed by this master #01 10 Only write accesses may be performed by this master #10 11 Both read and write accesses may be performed by this master #11 M4PFD Master 4 Prefetch Disable 20 1 read-write 0 Prefetching for this master is enabled. #0 1 Prefetching for this master is disabled. #1 M5AP Master 5 Access Protection 10 2 read-write 00 No access may be performed by this master #00 01 Only read accesses may be performed by this master #01 10 Only write accesses may be performed by this master #10 11 Both read and write accesses may be performed by this master #11 M5PFD Master 5 Prefetch Disable 21 1 read-write 0 Prefetching for this master is enabled. #0 1 Prefetching for this master is disabled. #1 M6AP Master 6 Access Protection 12 2 read-write 00 No access may be performed by this master #00 01 Only read accesses may be performed by this master #01 10 Only write accesses may be performed by this master #10 11 Both read and write accesses may be performed by this master #11 M6PFD Master 6 Prefetch Disable 22 1 read-write 0 Prefetching for this master is enabled. #0 1 Prefetching for this master is disabled. #1 M7AP Master 7 Access Protection 14 2 read-write 00 No access may be performed by this master. #00 01 Only read accesses may be performed by this master. #01 10 Only write accesses may be performed by this master. #10 11 Both read and write accesses may be performed by this master. #11 M7PFD Master 7 Prefetch Disable 23 1 read-write 0 Prefetching for this master is enabled. #0 1 Prefetching for this master is disabled. #1 RESERVED no description available 24 8 read-only PFB01CR Flash Bank 0-1 Control Register 0x4 32 read-write n 0x0 0x0 B01DCE Bank 0-1 Data Cache Enable 4 1 read-write 0 Do not cache data references. #0 1 Cache data references. #1 B01DPE Bank 0-1 Data Prefetch Enable 2 1 read-write 0 Do not prefetch in response to data references. #0 1 Enable prefetches in response to data references. #1 B01ICE Bank 0-1 Instruction Cache Enable 3 1 read-write 0 Do not cache instruction fetches. #0 1 Cache instruction fetches. #1 B01IPE Bank 0-1 Instruction Prefetch Enable 1 1 read-write 0 Do not prefetch in response to instruction fetches. #0 1 Enable prefetches in response to instruction fetches. #1 B01MW Bank 0-1 Memory Width 17 2 read-only 00 32 bits #00 01 64 bits #01 10 128 bits #10 11 Reserved #11 B01RWSC Bank 0-1 Read Wait State Control 28 4 read-only B01SEBE Bank 0-1 Single Entry Buffer Enable 0 1 read-write 0 Single entry buffer is disabled. #0 1 Single entry buffer is enabled. #1 CINV_WAY Cache Invalidate Way x 20 4 write-only 0 No cache way invalidation for the corresponding cache #0 1 Invalidate cache way for the corresponding cache: clear the tag, data, and vld bits of ways selected #1 CLCK_WAY Cache Lock Way x 24 4 read-write 0 Cache way is unlocked and may be displaced #0 1 Cache way is locked and its contents are not displaced #1 CRC Cache Replacement Control 5 3 read-write 000 LRU replacement algorithm per set across all four ways #000 001 Reserved #001 010 Independent LRU with ways [0-1] for ifetches, [2-3] for data #010 011 Independent LRU with ways [0-2] for ifetches, [3] for data #011 1xx Reserved #1xx RESERVED no description available 8 8 read-only RESERVED no description available 16 1 read-only S_B_INV Invalidate Prefetch Speculation Buffer 19 1 write-only 0 Speculation buffer and single entry buffer are not affected. #0 1 Invalidate (clear) speculation buffer and single entry buffer. #1 PFB23CR Flash Bank 2-3 Control Register 0x8 32 read-write n 0x0 0x0 B23DCE Bank 2-3 Data Cache Enable 4 1 read-write 0 Do not cache data references. #0 1 Cache data references. #1 B23DPE Bank 2-3 Data Prefetch Enable 2 1 read-write 0 Do not prefetch in response to data references. #0 1 Enable prefetches in response to data references. #1 B23ICE Bank 2-3 Instruction Cache Enable 3 1 read-write 0 Do not cache instruction fetches. #0 1 Cache instruction fetches. #1 B23IPE Bank 2-3 Instruction Prefetch Enable 1 1 read-write 0 Do not prefetch in response to instruction fetches. #0 1 Enable prefetches in response to instruction fetches. #1 B23MW Bank 2-3 Memory Width 17 2 read-only 00 32 bits #00 01 64 bits #01 10 128 bits #10 11 Reserved #11 B23RWSC Bank 2-3 Read Wait State Control 28 4 read-only B23SEBE Bank 2-3 Single Entry Buffer Enable 0 1 read-write 0 Single entry buffer is disabled. #0 1 Single entry buffer is enabled. #1 RESERVED no description available 5 3 read-only RESERVED no description available 8 8 read-only RESERVED no description available 16 1 read-only RESERVED no description available 19 9 read-only TAGVDW0S0 Cache Tag Storage 0x200 32 read-write n 0x0 0x0 RESERVED no description available 1 5 read-only RESERVED no description available 20 12 read-only tag 13-bit tag for cache entry 6 14 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW0S1 Cache Tag Storage 0x304 32 read-write n 0x0 0x0 RESERVED no description available 1 5 read-only RESERVED no description available 20 12 read-only tag 13-bit tag for cache entry 6 14 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW0S2 Cache Tag Storage 0x40C 32 read-write n 0x0 0x0 RESERVED no description available 1 5 read-only RESERVED no description available 20 12 read-only tag 13-bit tag for cache entry 6 14 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW0S3 Cache Tag Storage 0x518 32 read-write n 0x0 0x0 RESERVED no description available 1 5 read-only RESERVED no description available 20 12 read-only tag 13-bit tag for cache entry 6 14 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW1S0 Cache Tag Storage 0x220 32 read-write n 0x0 0x0 RESERVED no description available 1 5 read-only RESERVED no description available 20 12 read-only tag 13-bit tag for cache entry 6 14 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW1S1 Cache Tag Storage 0x334 32 read-write n 0x0 0x0 RESERVED no description available 1 5 read-only RESERVED no description available 20 12 read-only tag 13-bit tag for cache entry 6 14 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW1S2 Cache Tag Storage 0x44C 32 read-write n 0x0 0x0 RESERVED no description available 1 5 read-only RESERVED no description available 20 12 read-only tag 13-bit tag for cache entry 6 14 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW1S3 Cache Tag Storage 0x568 32 read-write n 0x0 0x0 RESERVED no description available 1 5 read-only RESERVED no description available 20 12 read-only tag 13-bit tag for cache entry 6 14 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW2S0 Cache Tag Storage 0x240 32 read-write n 0x0 0x0 RESERVED no description available 1 5 read-only RESERVED no description available 20 12 read-only tag 13-bit tag for cache entry 6 14 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW2S1 Cache Tag Storage 0x364 32 read-write n 0x0 0x0 RESERVED no description available 1 5 read-only RESERVED no description available 20 12 read-only tag 13-bit tag for cache entry 6 14 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW2S2 Cache Tag Storage 0x48C 32 read-write n 0x0 0x0 RESERVED no description available 1 5 read-only RESERVED no description available 20 12 read-only tag 13-bit tag for cache entry 6 14 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW2S3 Cache Tag Storage 0x5B8 32 read-write n 0x0 0x0 RESERVED no description available 1 5 read-only RESERVED no description available 20 12 read-only tag 13-bit tag for cache entry 6 14 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW3S0 Cache Tag Storage 0x260 32 read-write n 0x0 0x0 RESERVED no description available 1 5 read-only RESERVED no description available 20 12 read-only tag 13-bit tag for cache entry 6 14 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW3S1 Cache Tag Storage 0x394 32 read-write n 0x0 0x0 RESERVED no description available 1 5 read-only RESERVED no description available 20 12 read-only tag 13-bit tag for cache entry 6 14 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW3S2 Cache Tag Storage 0x4CC 32 read-write n 0x0 0x0 RESERVED no description available 1 5 read-only RESERVED no description available 20 12 read-only tag 13-bit tag for cache entry 6 14 read-write valid 1-bit valid for cache entry 0 1 read-write TAGVDW3S3 Cache Tag Storage 0x608 32 read-write n 0x0 0x0 RESERVED no description available 1 5 read-only RESERVED no description available 20 12 read-only tag 13-bit tag for cache entry 6 14 read-write valid 1-bit valid for cache entry 0 1 read-write FTFE Flash Memory Interface FTFE 0x0 0x0 0x18 registers n FTFE 18 Read_Collision 19 INT_FTFE 34 INT_Read_Collision 35 FCCOB0 Flash Common Command Object Registers 0x1A 8 read-write n 0x0 0x0 CCOBn no description available 0 8 read-write FCCOB1 Flash Common Command Object Registers 0x13 8 read-write n 0x0 0x0 CCOBn no description available 0 8 read-write FCCOB2 Flash Common Command Object Registers 0xD 8 read-write n 0x0 0x0 CCOBn no description available 0 8 read-write FCCOB3 Flash Common Command Object Registers 0x8 8 read-write n 0x0 0x0 CCOBn no description available 0 8 read-write FCCOB4 Flash Common Command Object Registers 0x40 8 read-write n 0x0 0x0 CCOBn no description available 0 8 read-write FCCOB5 Flash Common Command Object Registers 0x35 8 read-write n 0x0 0x0 CCOBn no description available 0 8 read-write FCCOB6 Flash Common Command Object Registers 0x2B 8 read-write n 0x0 0x0 CCOBn no description available 0 8 read-write FCCOB7 Flash Common Command Object Registers 0x22 8 read-write n 0x0 0x0 CCOBn no description available 0 8 read-write FCCOB8 Flash Common Command Object Registers 0x76 8 read-write n 0x0 0x0 CCOBn no description available 0 8 read-write FCCOB9 Flash Common Command Object Registers 0x67 8 read-write n 0x0 0x0 CCOBn no description available 0 8 read-write FCCOBA Flash Common Command Object Registers 0x59 8 read-write n 0x0 0x0 CCOBn no description available 0 8 read-write FCCOBB Flash Common Command Object Registers 0x4C 8 read-write n 0x0 0x0 CCOBn no description available 0 8 read-write FCNFG Flash Configuration Register 0x1 8 read-write n 0x0 0x0 CCIE Command Complete Interrupt Enable 7 1 read-write 0 Command complete interrupt disabled #0 1 Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set. #1 EEERDY no description available 0 1 read-only 0 For devices with FlexNVM: FlexRAM is not available for EEPROM operation. #0 1 For devices with FlexNVM: FlexRAM is available for EEPROM operations where: reads from the FlexRAM return data previously written to the FlexRAM in EEPROM mode and writes launch an EEPROM operation to store the written data in the FlexRAM and EEPROM backup. #1 ERSAREQ Erase All Request 5 1 read-only 0 No request or request complete #0 1 Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state. #1 ERSSUSP Erase Suspend 4 1 read-write 0 No suspend requested #0 1 Suspend the current Erase Flash Sector command execution. #1 PFLSH FTFE configuration 2 1 read-only 0 For devices with FlexNVM: FTFE configuration supports two logical program flash blocks and two logical FlexNVM blocks For devices with program flash only: Reserved #0 1 For devices with FlexNVM: Reserved For devices with program flash only: FTFE configuration supports four logical program flash blocks #1 RAMRDY RAM Ready 1 1 read-only 0 For devices with FlexNVM: FlexRAM is not available for traditional RAM access. For devices without FlexNVM: Programming acceleration RAM is not available. #0 1 For devices with FlexNVM: FlexRAM is available as traditional RAM only; writes to the FlexRAM do not trigger EEPROM operations. For devices without FlexNVM: Programming acceleration RAM is available. #1 RDCOLLIE Read Collision Error Interrupt Enable 6 1 read-write 0 Read collision error interrupt disabled #0 1 Read collision error interrupt enabled. An interrupt request is generated whenever an FTFE read collision error is detected (see the description of FSTAT[RDCOLERR]). #1 SWAP Swap 3 1 read-only 0 For devices with FlexNVM: Logical program flash 0 block is located at relative address 0x0000 For devices with program flash only: Logical program flash 0/1 blocks are located at relative address 0x0000 #0 1 For devices with FlexNVM: Logical program flash 1 block is located at relative address 0x0000 For devices with program flash only: Logical program flash 2/3 blocks are located at relative address 0x0000 #1 FDPROT Data Flash Protection Register 0x17 8 read-write n 0x0 0x0 DPROT Data Flash Region Protect 0 8 read-write 0 Data Flash region is protected #0 1 Data Flash region is not protected #1 FEPROT EEPROM Protection Register 0x16 8 read-write n 0x0 0x0 EPROT EEPROM Region Protect 0 8 read-write 0 For devices with program flash only: Reserved For devices with FlexNVM: EEPROM region is protected #0 1 For devices with program flash only: Reserved For devices with FlexNVM: EEPROM region is not protected #1 FOPT Flash Option Register 0x3 8 read-only n 0x0 0x0 OPT Nonvolatile Option 0 8 read-only FPROT0 Program Flash Protection Registers 0x56 8 read-write n 0x0 0x0 PROT Program Flash Region Protect 0 8 read-write 0 Program flash region is protected. #0 1 Program flash region is not protected #1 FPROT1 Program Flash Protection Registers 0x43 8 read-write n 0x0 0x0 PROT Program Flash Region Protect 0 8 read-write 0 Program flash region is protected. #0 1 Program flash region is not protected #1 FPROT2 Program Flash Protection Registers 0x31 8 read-write n 0x0 0x0 PROT Program Flash Region Protect 0 8 read-write 0 Program flash region is protected. #0 1 Program flash region is not protected #1 FPROT3 Program Flash Protection Registers 0x20 8 read-write n 0x0 0x0 PROT Program Flash Region Protect 0 8 read-write 0 Program flash region is protected. #0 1 Program flash region is not protected #1 FSEC Flash Security Register 0x2 8 read-only n 0x0 0x0 FSLACC Freescale Failure Analysis Access Code 2 2 read-only 00 Freescale factory access granted #00 01 Freescale factory access denied #01 10 Freescale factory access denied #10 11 Freescale factory access granted #11 KEYEN Backdoor Key Security Enable 6 2 read-only 00 Backdoor key access disabled #00 01 Backdoor key access disabled (preferred KEYEN state to disable backdoor key access) #01 10 Backdoor key access enabled #10 11 Backdoor key access disabled #11 MEEN Mass Erase Enable Bits 4 2 read-only 00 Mass erase is enabled #00 01 Mass erase is enabled #01 10 Mass erase is disabled #10 11 Mass erase is enabled #11 SEC Flash Security 0 2 read-only 00 MCU security status is secure #00 01 MCU security status is secure #01 10 MCU security status is unsecure (The standard shipping condition of the FTFE is unsecure.) #10 11 MCU security status is secure #11 FSTAT Flash Status Register 0x0 8 read-write n 0x0 0x0 ACCERR Flash Access Error Flag 5 1 read-write 0 No access error detected #0 1 Access error detected #1 CCIF Command Complete Interrupt Flag 7 1 read-write 0 FTFE command or EEPROM file system operation in progress #0 1 FTFE command or EEPROM file system operation has completed #1 FPVIOL Flash Protection Violation Flag 4 1 read-write 0 No protection violation detected #0 1 Protection violation detected #1 MGSTAT0 Memory Controller Command Completion Status Flag 0 1 read-only RDCOLERR FTFE Read Collision Error Flag 6 1 read-write 0 No collision error detected #0 1 Collision error detected #1 RESERVED no description available 1 3 read-only FTFE_FlashConfig Flash Memory Interface FTFE_FlashConfig 0x0 0x0 0x10 registers n BACKKEY0 Backdoor Comparison Key 0. 0x3 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only BACKKEY1 Backdoor Comparison Key 1. 0x2 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only BACKKEY2 Backdoor Comparison Key 2. 0x1 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only BACKKEY3 Backdoor Comparison Key 3. 0x0 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only BACKKEY4 Backdoor Comparison Key 4. 0x7 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only BACKKEY5 Backdoor Comparison Key 5. 0x6 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only BACKKEY6 Backdoor Comparison Key 6. 0x5 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only BACKKEY7 Backdoor Comparison Key 7. 0x4 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only FDPROT Non-volatile D-Flash Protection Register 0xF 8 read-only n 0x0 0x0 DPROT D-Flash Region Protect 0 8 read-only FEPROT Non-volatile EERAM Protection Register 0xE 8 read-only n 0x0 0x0 EPROT no description available 0 8 read-only FOPT Non-volatile Flash Option Register 0xD 8 read-only n 0x0 0x0 EZPORT_DIS no description available 1 1 read-only LPBOOT no description available 0 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 3 1 read-only RESERVED no description available 4 1 read-only RESERVED no description available 5 1 read-only RESERVED no description available 6 1 read-only RESERVED no description available 7 1 read-only FPROT0 Non-volatile P-Flash Protection 0 - High Register 0xB 8 read-only n 0x0 0x0 PROT P-Flash Region Protect 0 8 read-only FPROT1 Non-volatile P-Flash Protection 0 - Low Register 0xA 8 read-only n 0x0 0x0 PROT P-Flash Region Protect 0 8 read-only FPROT2 Non-volatile P-Flash Protection 1 - High Register 0x9 8 read-only n 0x0 0x0 PROT P-Flash Region Protect 0 8 read-only FPROT3 Non-volatile P-Flash Protection 1 - Low Register 0x8 8 read-only n 0x0 0x0 PROT P-Flash Region Protect 0 8 read-only FSEC Non-volatile Flash Security Register 0xC 8 read-only n 0x0 0x0 FSLACC Freescale Failure Analysis Access Code 2 2 read-only KEYEN Backdoor Key Security Enable 6 2 read-only MEEN no description available 4 2 read-only SEC Flash Security 0 2 read-only NV_BACKKEY0 Backdoor Comparison Key 0. 0x3 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY1 Backdoor Comparison Key 1. 0x2 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY2 Backdoor Comparison Key 2. 0x1 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY3 Backdoor Comparison Key 3. 0x0 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY4 Backdoor Comparison Key 4. 0x7 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY5 Backdoor Comparison Key 5. 0x6 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY6 Backdoor Comparison Key 6. 0x5 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_BACKKEY7 Backdoor Comparison Key 7. 0x4 8 read-only n 0x0 0x0 KEY Backdoor Comparison Key. 0 8 read-only NV_FDPROT Non-volatile D-Flash Protection Register 0xF 8 read-only n 0x0 0x0 DPROT D-Flash Region Protect 0 8 read-only NV_FEPROT Non-volatile EERAM Protection Register 0xE 8 read-only n 0x0 0x0 EPROT no description available 0 8 read-only NV_FOPT Non-volatile Flash Option Register 0xD 8 read-only n 0x0 0x0 EZPORT_DIS no description available 1 1 read-only 00 EzPort operation is disabled #00 01 EzPort operation is enabled #01 LPBOOT no description available 0 1 read-only 00 Low-power boot #00 01 Normal boot #01 RESERVED no description available 2 1 read-only RESERVED no description available 3 1 read-only RESERVED no description available 4 1 read-only RESERVED no description available 5 1 read-only RESERVED no description available 6 1 read-only RESERVED no description available 7 1 read-only NV_FPROT0 Non-volatile P-Flash Protection 0 - High Register 0xB 8 read-only n 0x0 0x0 PROT P-Flash Region Protect 0 8 read-only NV_FPROT1 Non-volatile P-Flash Protection 0 - Low Register 0xA 8 read-only n 0x0 0x0 PROT P-Flash Region Protect 0 8 read-only NV_FPROT2 Non-volatile P-Flash Protection 1 - High Register 0x9 8 read-only n 0x0 0x0 PROT P-Flash Region Protect 0 8 read-only NV_FPROT3 Non-volatile P-Flash Protection 1 - Low Register 0x8 8 read-only n 0x0 0x0 PROT P-Flash Region Protect 0 8 read-only NV_FSEC Non-volatile Flash Security Register 0xC 8 read-only n 0x0 0x0 FSLACC Freescale Failure Analysis Access Code 2 2 read-only 10 Freescale factory access denied #10 11 Freescale factory access granted #11 KEYEN Backdoor Key Security Enable 6 2 read-only 10 Backdoor key access enabled #10 11 Backdoor key access disabled #11 MEEN no description available 4 2 read-only 10 Mass erase is disabled #10 11 Mass erase is enabled #11 SEC Flash Security 0 2 read-only 10 MCU security status is unsecure #10 11 MCU security status is secure #11 FTM0 FlexTimer Module FTM 0x0 0x0 0x9C registers n FTM0 62 INT_FTM0 78 C0SC Channel (n) Status and Control 0x18 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write RESERVED no description available 1 1 read-only RESERVED no description available 8 24 read-only C0V Channel (n) Value 0x20 32 read-write n 0x0 0x0 RESERVED no description available 16 16 read-only VAL Channel Value 0 16 read-write C1SC Channel (n) Status and Control 0x2C 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write RESERVED no description available 1 1 read-only RESERVED no description available 8 24 read-only C1V Channel (n) Value 0x38 32 read-write n 0x0 0x0 RESERVED no description available 16 16 read-only VAL Channel Value 0 16 read-write C2SC Channel (n) Status and Control 0x48 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write RESERVED no description available 1 1 read-only RESERVED no description available 8 24 read-only C2V Channel (n) Value 0x58 32 read-write n 0x0 0x0 RESERVED no description available 16 16 read-only VAL Channel Value 0 16 read-write C3SC Channel (n) Status and Control 0x6C 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write RESERVED no description available 1 1 read-only RESERVED no description available 8 24 read-only C3V Channel (n) Value 0x80 32 read-write n 0x0 0x0 RESERVED no description available 16 16 read-only VAL Channel Value 0 16 read-write C4SC Channel (n) Status and Control 0x98 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write RESERVED no description available 1 1 read-only RESERVED no description available 8 24 read-only C4V Channel (n) Value 0xB0 32 read-write n 0x0 0x0 RESERVED no description available 16 16 read-only VAL Channel Value 0 16 read-write C5SC Channel (n) Status and Control 0xCC 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write RESERVED no description available 1 1 read-only RESERVED no description available 8 24 read-only C5V Channel (n) Value 0xE8 32 read-write n 0x0 0x0 RESERVED no description available 16 16 read-only VAL Channel Value 0 16 read-write C6SC Channel (n) Status and Control 0x108 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write RESERVED no description available 1 1 read-only RESERVED no description available 8 24 read-only C6V Channel (n) Value 0x128 32 read-write n 0x0 0x0 RESERVED no description available 16 16 read-only VAL Channel Value 0 16 read-write C7SC Channel (n) Status and Control 0x14C 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write RESERVED no description available 1 1 read-only RESERVED no description available 8 24 read-only C7V Channel (n) Value 0x170 32 read-write n 0x0 0x0 RESERVED no description available 16 16 read-only VAL Channel Value 0 16 read-write CNT Counter 0x4 32 read-write n 0x0 0x0 COUNT Counter value 0 16 read-write RESERVED no description available 16 16 read-only CNTIN Counter Initial Value 0x4C 32 read-write n 0x0 0x0 INIT no description available 0 16 read-write RESERVED no description available 16 16 read-write COMBINE Function for Linked Channels 0x64 32 read-write n 0x0 0x0 COMBINE0 Combine Channels for n = 0 0 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMBINE1 Combine Channels for n = 2 8 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMBINE2 Combine Channels for n = 4 16 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMBINE3 Combine Channels for n = 6 24 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP0 Complement of Channel (n) for n = 0 1 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 COMP1 Complement of Channel (n) for n = 2 9 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 COMP2 Complement of Channel (n) for n = 4 17 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 COMP3 Complement of Channel (n) for n = 6 25 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAP0 Dual Edge Capture Mode Captures for n = 0 3 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAP1 Dual Edge Capture Mode Captures for n = 2 11 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAP2 Dual Edge Capture Mode Captures for n = 4 19 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAP3 Dual Edge Capture Mode Captures for n = 6 27 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAPEN0 Dual Edge Capture Mode Enable for n = 0 2 1 read-write 0 The dual edge capture mode in this pair of channels is disabled. #0 1 The dual edge capture mode in this pair of channels is enabled. #1 DECAPEN1 Dual Edge Capture Mode Enable for n = 2 10 1 read-write 0 The dual edge capture mode in this pair of channels is disabled. #0 1 The dual edge capture mode in this pair of channels is enabled. #1 DECAPEN2 Dual Edge Capture Mode Enable for n = 4 18 1 read-write 0 The dual edge capture mode in this pair of channels is disabled. #0 1 The dual edge capture mode in this pair of channels is enabled. #1 DECAPEN3 Dual Edge Capture Mode Enable for n = 6 26 1 read-write 0 The dual edge capture mode in this pair of channels is disabled. #0 1 The dual edge capture mode in this pair of channels is enabled. #1 DTEN0 Deadtime Enable for n = 0 4 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 DTEN1 Deadtime Enable for n = 2 12 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 DTEN2 Deadtime Enable for n = 4 20 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 DTEN3 Deadtime Enable for n = 6 28 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 FAULTEN0 Fault Control Enable for n = 0 6 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 FAULTEN1 Fault Control Enable for n = 2 14 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 FAULTEN2 Fault Control Enable for n = 4 22 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 FAULTEN3 Fault Control Enable for n = 6 30 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 RESERVED no description available 7 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 31 1 read-only SYNCEN0 Synchronization Enable for n = 0 5 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 SYNCEN1 Synchronization Enable for n = 2 13 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 SYNCEN2 Synchronization Enable for n = 4 21 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 SYNCEN3 Synchronization Enable for n = 6 29 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 CONF Configuration 0x84 32 read-write n 0x0 0x0 BDMMODE BDM Mode 6 2 read-write GTBEEN Global time base enable 9 1 read-write 0 Use of an external global time base is disabled. #0 1 Use of an external global time base is enabled. #1 GTBEOUT Global time base output 10 1 read-write 0 A global time base signal generation is disabled. #0 1 A global time base signal generation is enabled. #1 NUMTOF TOF Frequency 0 5 read-write RESERVED no description available 5 1 read-only RESERVED no description available 8 1 read-only RESERVED no description available 11 21 read-only DEADTIME Deadtime Insertion Control 0x68 32 read-write n 0x0 0x0 DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the system clock by 1. #0x 10 Divide the system clock by 4. #10 11 Divide the system clock by 16. #11 DTVAL Deadtime Value 0 6 read-write RESERVED no description available 8 24 read-only EXTTRIG FTM External Trigger 0x6C 32 read-write n 0x0 0x0 CH0TRIG Channel 0 Trigger Enable 4 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH1TRIG Channel 1 Trigger Enable 5 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH2TRIG Channel 2 Trigger Enable 0 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH3TRIG Channel 3 Trigger Enable 1 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH4TRIG Channel 4 Trigger Enable 2 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH5TRIG Channel 5 Trigger Enable 3 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 INITTRIGEN Initialization Trigger Enable 6 1 read-write 0 The generation of initialization trigger is disabled. #0 1 The generation of initialization trigger is enabled. #1 RESERVED no description available 8 24 read-write TRIGF Channel Trigger Flag 7 1 read-write 0 No channel trigger was generated. #0 1 A channel trigger was generated. #1 FILTER Input Capture Filter Control 0x78 32 read-write n 0x0 0x0 CH0FVAL Channel 0 Input Filter 0 4 read-write CH1FVAL Channel 1 Input Filter 4 4 read-write CH2FVAL Channel 2 Input Filter 8 4 read-write CH3FVAL Channel 3 Input Filter 12 4 read-write RESERVED no description available 16 16 read-write FLTCTRL Fault Control 0x7C 32 read-write n 0x0 0x0 FAULT0EN Fault Input 0 Enable 0 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT1EN Fault Input 1 Enable 1 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT2EN Fault Input 2 Enable 2 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT3EN Fault Input 3 Enable 3 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FFLTR0EN Fault Input 0 Filter Enable 4 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR1EN Fault Input 1 Filter Enable 5 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR2EN Fault Input 2 Filter Enable 6 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR3EN Fault Input 3 Filter Enable 7 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFVAL Fault Input Filter 8 4 read-write RESERVED no description available 12 20 read-only FLTPOL FTM Fault Input Polarity 0x88 32 read-write n 0x0 0x0 FLT0POL Fault Input 0 Polarity 0 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT1POL Fault Input 1 Polarity 1 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT2POL Fault Input 2 Polarity 2 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT3POL Fault Input 3 Polarity 3 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 RESERVED no description available 4 28 read-only FMS Fault Mode Status 0x74 32 read-write n 0x0 0x0 FAULTF Fault Detection Flag 7 1 read-only 0 No fault condition was detected. #0 1 A fault condition was detected. #1 FAULTF0 Fault Detection Flag 0 0 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF1 Fault Detection Flag 1 1 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF2 Fault Detection Flag 2 2 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF3 Fault Detection Flag 3 3 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTIN Fault Inputs 5 1 read-only 0 The logic OR of the enabled fault inputs is 0. #0 1 The logic OR of the enabled fault inputs is 1. #1 RESERVED no description available 4 1 read-only RESERVED no description available 8 24 read-only WPEN Write Protection Enable 6 1 read-write 0 Write protection is disabled. Write protected bits can be written. #0 1 Write protection is enabled. Write protected bits cannot be written. #1 INVCTRL FTM Inverting Control 0x90 32 read-write n 0x0 0x0 INV0EN Pair Channels 0 Inverting Enable 0 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV1EN Pair Channels 1 Inverting Enable 1 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV2EN Pair Channels 2 Inverting Enable 2 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV3EN Pair Channels 3 Inverting Enable 3 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 RESERVED no description available 4 28 read-only MOD Modulo 0x8 32 read-write n 0x0 0x0 MOD no description available 0 16 read-write RESERVED no description available 16 16 read-write MODE Features Mode Selection 0x54 32 read-write n 0x0 0x0 CAPTEST Capture Test Mode Enable 4 1 read-write 0 Capture test mode is disabled. #0 1 Capture test mode is enabled. #1 FAULTIE Fault Interrupt Enable 7 1 read-write 0 Fault control interrupt is disabled. #0 1 Fault control interrupt is enabled. #1 FAULTM Fault Control Mode 5 2 read-write 00 Fault control is disabled for all channels. #00 01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. #01 10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing. #10 11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. #11 FTMEN FTM Enable 0 1 read-write 0 Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not use the FTM-specific registers. #0 1 All registers including the FTM-specific registers (second set of registers) are available for use with no restrictions. #1 INIT Initialize the Channels Output 1 1 read-write PWMSYNC PWM Synchronization Mode 3 1 read-write 0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. #0 1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. #1 RESERVED no description available 8 24 read-only WPDIS Write Protection Disable 2 1 read-write 0 Write protection is enabled. #0 1 Write protection is disabled. #1 OUTINIT Initial State for Channels Output 0x5C 32 read-write n 0x0 0x0 CH0OI Channel 0 Output Initialization Value 0 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH1OI Channel 1 Output Initialization Value 1 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH2OI Channel 2 Output Initialization Value 2 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH3OI Channel 3 Output Initialization Value 3 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH4OI Channel 4 Output Initialization Value 4 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH5OI Channel 5 Output Initialization Value 5 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH6OI Channel 6 Output Initialization Value 6 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH7OI Channel 7 Output Initialization Value 7 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 RESERVED no description available 8 24 read-only OUTMASK Output Mask 0x60 32 read-write n 0x0 0x0 CH0OM Channel 0 Output Mask 0 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH1OM Channel 1 Output Mask 1 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH2OM Channel 2 Output Mask 2 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH3OM Channel 3 Output Mask 3 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH4OM Channel 4 Output Mask 4 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH5OM Channel 5 Output Mask 5 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH6OM Channel 6 Output Mask 6 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH7OM Channel 7 Output Mask 7 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 RESERVED no description available 8 24 read-only POL Channels Polarity 0x70 32 read-write n 0x0 0x0 POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL4 Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL5 Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL6 Channel 6 Polarity 6 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL7 Channel 7 Polarity 7 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 RESERVED no description available 8 24 read-write PWMLOAD FTM PWM Load 0x98 32 read-write n 0x0 0x0 CH0SEL Channel 0 Select 0 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH1SEL Channel 1 Select 1 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH2SEL Channel 2 Select 2 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH3SEL Channel 3 Select 3 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH4SEL Channel 4 Select 4 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH5SEL Channel 5 Select 5 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH6SEL Channel 6 Select 6 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH7SEL Channel 7 Select 7 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 LDOK Load Enable 9 1 read-write 0 Loading updated values is disabled. #0 1 Loading updated values is enabled. #1 RESERVED no description available 8 1 read-only RESERVED no description available 10 22 read-only QDCTRL Quadrature Decoder Control and Status 0x80 32 read-write n 0x0 0x0 PHAFLTREN Phase A Input Filter Enable 7 1 read-write 0 Phase A input filter is disabled. #0 1 Phase A input filter is enabled. #1 PHAPOL Phase A Input Polarity 5 1 read-write 0 Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal. #1 PHBFLTREN Phase B Input Filter Enable 6 1 read-write 0 Phase B input filter is disabled. #0 1 Phase B input filter is enabled. #1 PHBPOL Phase B Input Polarity 4 1 read-write 0 Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal. #1 QUADEN Quadrature Decoder Mode Enable 0 1 read-write 0 Quadrature decoder mode is disabled. #0 1 Quadrature decoder mode is enabled. #1 QUADIR FTM Counter Direction in Quadrature Decoder Mode 2 1 read-only 0 Counting direction is decreasing (FTM counter decrement). #0 1 Counting direction is increasing (FTM counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase A and phase B encoding mode. #0 1 Count and direction encoding mode. #1 RESERVED no description available 8 24 read-only TOFDIR Timer Overflow Direction in Quadrature Decoder Mode 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register). #1 SC Status and Control 0x0 32 read-write n 0x0 0x0 CLKS Clock Source Selection 3 2 read-write 00 No clock selected (This in effect disables the FTM counter.) #00 01 System clock #01 10 Fixed frequency clock #10 11 External clock #11 CPWMS Center-aligned PWM Select 5 1 read-write 0 FTM counter operates in up counting mode. #0 1 FTM counter operates in up-down counting mode. #1 PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 RESERVED no description available 8 24 read-only TOF Timer Overflow Flag 7 1 read-only 0 FTM counter has not overflowed. #0 1 FTM counter has overflowed. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 STATUS Capture and Compare Status 0x50 32 read-only n 0x0 0x0 CH0F Channel 0 Flag 0 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4F Channel 4 Flag 4 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5F Channel 5 Flag 5 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH6F Channel 6 Flag 6 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH7F Channel 7 Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 RESERVED no description available 8 24 read-only SWOCTRL FTM Software Output Control 0x94 32 read-write n 0x0 0x0 CH0OC Channel 0 Software Output Control Enable 0 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH0OCV Channel 0 Software Output Control Value 8 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH1OC Channel 1 Software Output Control Enable 1 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH1OCV Channel 1 Software Output Control Value 9 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH2OC Channel 2 Software Output Control Enable 2 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH2OCV Channel 2 Software Output Control Value 10 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH3OC Channel 3 Software Output Control Enable 3 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH3OCV Channel 3 Software Output Control Value 11 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH4OC Channel 4 Software Output Control Enable 4 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH4OCV Channel 4 Software Output Control Value 12 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH5OC Channel 5 Software Output Control Enable 5 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH5OCV Channel 5 Software Output Control Value 13 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH6OC Channel 6 Software Output Control Enable 6 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH6OCV Channel 6 Software Output Control Value 14 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH7OC Channel 7 Software Output Control Enable 7 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH7OCV Channel 7 Software Output Control Value 15 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 RESERVED no description available 16 16 read-only SYNC Synchronization 0x58 32 read-write n 0x0 0x0 CNTMAX Maximum loading point enable 1 1 read-write 0 The maximum loading point is disabled. #0 1 The maximum loading point is enabled. #1 CNTMIN Minimum loading point enable 0 1 read-write 0 The minimum loading point is disabled. #0 1 The minimum loading point is enabled. #1 REINIT FTM Counter Reinitialization by Synchronization (FTM Counter Synchronization) 2 1 read-write 0 FTM counter continues to count normally. #0 1 FTM counter is updated with its initial value when the selected trigger is detected. #1 RESERVED no description available 8 24 read-only SWSYNC PWM Synchronization Software Trigger 7 1 read-write 0 Software trigger is not selected. #0 1 Software trigger is selected. #1 SYNCHOM Output Mask Synchronization 3 1 read-write 0 OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. #0 1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization. #1 TRIG0 PWM Synchronization Hardware Trigger 0 4 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG1 PWM Synchronization Hardware Trigger 1 5 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG2 PWM Synchronization Hardware Trigger 2 6 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 SYNCONF Synchronization Configuration 0x8C 32 read-write n 0x0 0x0 CNTINC CNTIN register synchronization 2 1 read-write 0 CNTIN register is updated with its buffer value at all rising edges of system clock. #0 1 CNTIN register is updated with its buffer value by the PWM synchronization. #1 HWINVC no description available 19 1 read-write 0 A hardware trigger does not activate the INVCTRL register synchronization. #0 1 A hardware trigger activates the INVCTRL register synchronization. #1 HWOM no description available 18 1 read-write 0 A hardware trigger does not activate the OUTMASK register synchronization. #0 1 A hardware trigger activates the OUTMASK register synchronization. #1 HWRSTCNT no description available 16 1 read-write 0 A hardware trigger does not activate the FTM counter synchronization. #0 1 A hardware trigger activates the FTM counter synchronization. #1 HWSOC no description available 20 1 read-write 0 A hardware trigger does not activate the SWOCTRL register synchronization. #0 1 A hardware trigger activates the SWOCTRL register synchronization. #1 HWTRIGMODE Hardware Trigger Mode 0 1 read-write 0 FTM clears the TRIGj bit when the hardware trigger j is detected. #0 1 FTM does not clear the TRIGj bit when the hardware trigger j is detected. #1 HWWRBUF no description available 17 1 read-write 0 A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 A hardware trigger activates MOD, CNTIN, and CV registers synchronization. #1 INVC INVCTRL register synchronization 4 1 read-write 0 INVCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 INVCTRL register is updated with its buffer value by the PWM synchronization. #1 RESERVED no description available 1 1 read-only RESERVED no description available 3 1 read-only RESERVED no description available 6 1 read-only RESERVED no description available 13 3 read-only RESERVED no description available 21 11 read-only SWINVC no description available 11 1 read-write 0 The software trigger does not activate the INVCTRL register synchronization. #0 1 The software trigger activates the INVCTRL register synchronization. #1 SWOC SWOCTRL register synchronization 5 1 read-write 0 SWOCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 SWOCTRL register is updated with its buffer value by the PWM synchronization. #1 SWOM no description available 10 1 read-write 0 The software trigger does not activate the OUTMASK register synchronization. #0 1 The software trigger activates the OUTMASK register synchronization. #1 SWRSTCNT no description available 8 1 read-write 0 The software trigger does not activate the FTM counter synchronization. #0 1 The software trigger activates the FTM counter synchronization. #1 SWSOC no description available 12 1 read-write 0 The software trigger does not activate the SWOCTRL register synchronization. #0 1 The software trigger activates the SWOCTRL register synchronization. #1 SWWRBUF no description available 9 1 read-write 0 The software trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 The software trigger activates MOD, CNTIN, and CV registers synchronization. #1 SYNCMODE Synchronization Mode 7 1 read-write 0 Legacy PWM synchronization is selected. #0 1 Enhanced PWM synchronization is selected. #1 FTM1 FlexTimer Module FTM 0x0 0x0 0x9C registers n FTM1 63 INT_FTM1 79 C0SC Channel (n) Status and Control 0x18 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write RESERVED no description available 1 1 read-only RESERVED no description available 8 24 read-only C0V Channel (n) Value 0x20 32 read-write n 0x0 0x0 RESERVED no description available 16 16 read-only VAL Channel Value 0 16 read-write C1SC Channel (n) Status and Control 0x2C 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write RESERVED no description available 1 1 read-only RESERVED no description available 8 24 read-only C1V Channel (n) Value 0x38 32 read-write n 0x0 0x0 RESERVED no description available 16 16 read-only VAL Channel Value 0 16 read-write CNT Counter 0x4 32 read-write n 0x0 0x0 COUNT Counter value 0 16 read-write RESERVED no description available 16 16 read-only CNTIN Counter Initial Value 0x4C 32 read-write n 0x0 0x0 INIT no description available 0 16 read-write RESERVED no description available 16 16 read-write COMBINE Function for Linked Channels 0x64 32 read-write n 0x0 0x0 COMBINE0 Combine Channels for n = 0 0 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMBINE1 Combine Channels for n = 2 8 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMBINE2 Combine Channels for n = 4 16 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMBINE3 Combine Channels for n = 6 24 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP0 Complement of Channel (n) for n = 0 1 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 COMP1 Complement of Channel (n) for n = 2 9 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 COMP2 Complement of Channel (n) for n = 4 17 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 COMP3 Complement of Channel (n) for n = 6 25 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAP0 Dual Edge Capture Mode Captures for n = 0 3 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAP1 Dual Edge Capture Mode Captures for n = 2 11 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAP2 Dual Edge Capture Mode Captures for n = 4 19 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAP3 Dual Edge Capture Mode Captures for n = 6 27 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAPEN0 Dual Edge Capture Mode Enable for n = 0 2 1 read-write 0 The dual edge capture mode in this pair of channels is disabled. #0 1 The dual edge capture mode in this pair of channels is enabled. #1 DECAPEN1 Dual Edge Capture Mode Enable for n = 2 10 1 read-write 0 The dual edge capture mode in this pair of channels is disabled. #0 1 The dual edge capture mode in this pair of channels is enabled. #1 DECAPEN2 Dual Edge Capture Mode Enable for n = 4 18 1 read-write 0 The dual edge capture mode in this pair of channels is disabled. #0 1 The dual edge capture mode in this pair of channels is enabled. #1 DECAPEN3 Dual Edge Capture Mode Enable for n = 6 26 1 read-write 0 The dual edge capture mode in this pair of channels is disabled. #0 1 The dual edge capture mode in this pair of channels is enabled. #1 DTEN0 Deadtime Enable for n = 0 4 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 DTEN1 Deadtime Enable for n = 2 12 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 DTEN2 Deadtime Enable for n = 4 20 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 DTEN3 Deadtime Enable for n = 6 28 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 FAULTEN0 Fault Control Enable for n = 0 6 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 FAULTEN1 Fault Control Enable for n = 2 14 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 FAULTEN2 Fault Control Enable for n = 4 22 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 FAULTEN3 Fault Control Enable for n = 6 30 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 RESERVED no description available 7 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 31 1 read-only SYNCEN0 Synchronization Enable for n = 0 5 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 SYNCEN1 Synchronization Enable for n = 2 13 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 SYNCEN2 Synchronization Enable for n = 4 21 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 SYNCEN3 Synchronization Enable for n = 6 29 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 CONF Configuration 0x84 32 read-write n 0x0 0x0 BDMMODE BDM Mode 6 2 read-write GTBEEN Global time base enable 9 1 read-write 0 Use of an external global time base is disabled. #0 1 Use of an external global time base is enabled. #1 GTBEOUT Global time base output 10 1 read-write 0 A global time base signal generation is disabled. #0 1 A global time base signal generation is enabled. #1 NUMTOF TOF Frequency 0 5 read-write RESERVED no description available 5 1 read-only RESERVED no description available 8 1 read-only RESERVED no description available 11 21 read-only DEADTIME Deadtime Insertion Control 0x68 32 read-write n 0x0 0x0 DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the system clock by 1. #0x 10 Divide the system clock by 4. #10 11 Divide the system clock by 16. #11 DTVAL Deadtime Value 0 6 read-write RESERVED no description available 8 24 read-only EXTTRIG FTM External Trigger 0x6C 32 read-write n 0x0 0x0 CH0TRIG Channel 0 Trigger Enable 4 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH1TRIG Channel 1 Trigger Enable 5 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH2TRIG Channel 2 Trigger Enable 0 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH3TRIG Channel 3 Trigger Enable 1 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH4TRIG Channel 4 Trigger Enable 2 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH5TRIG Channel 5 Trigger Enable 3 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 INITTRIGEN Initialization Trigger Enable 6 1 read-write 0 The generation of initialization trigger is disabled. #0 1 The generation of initialization trigger is enabled. #1 RESERVED no description available 8 24 read-write TRIGF Channel Trigger Flag 7 1 read-write 0 No channel trigger was generated. #0 1 A channel trigger was generated. #1 FILTER Input Capture Filter Control 0x78 32 read-write n 0x0 0x0 CH0FVAL Channel 0 Input Filter 0 4 read-write CH1FVAL Channel 1 Input Filter 4 4 read-write CH2FVAL Channel 2 Input Filter 8 4 read-write CH3FVAL Channel 3 Input Filter 12 4 read-write RESERVED no description available 16 16 read-write FLTCTRL Fault Control 0x7C 32 read-write n 0x0 0x0 FAULT0EN Fault Input 0 Enable 0 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT1EN Fault Input 1 Enable 1 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT2EN Fault Input 2 Enable 2 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT3EN Fault Input 3 Enable 3 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FFLTR0EN Fault Input 0 Filter Enable 4 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR1EN Fault Input 1 Filter Enable 5 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR2EN Fault Input 2 Filter Enable 6 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR3EN Fault Input 3 Filter Enable 7 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFVAL Fault Input Filter 8 4 read-write RESERVED no description available 12 20 read-only FLTPOL FTM Fault Input Polarity 0x88 32 read-write n 0x0 0x0 FLT0POL Fault Input 0 Polarity 0 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT1POL Fault Input 1 Polarity 1 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT2POL Fault Input 2 Polarity 2 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT3POL Fault Input 3 Polarity 3 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 RESERVED no description available 4 28 read-only FMS Fault Mode Status 0x74 32 read-write n 0x0 0x0 FAULTF Fault Detection Flag 7 1 read-only 0 No fault condition was detected. #0 1 A fault condition was detected. #1 FAULTF0 Fault Detection Flag 0 0 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF1 Fault Detection Flag 1 1 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF2 Fault Detection Flag 2 2 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF3 Fault Detection Flag 3 3 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTIN Fault Inputs 5 1 read-only 0 The logic OR of the enabled fault inputs is 0. #0 1 The logic OR of the enabled fault inputs is 1. #1 RESERVED no description available 4 1 read-only RESERVED no description available 8 24 read-only WPEN Write Protection Enable 6 1 read-write 0 Write protection is disabled. Write protected bits can be written. #0 1 Write protection is enabled. Write protected bits cannot be written. #1 INVCTRL FTM Inverting Control 0x90 32 read-write n 0x0 0x0 INV0EN Pair Channels 0 Inverting Enable 0 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV1EN Pair Channels 1 Inverting Enable 1 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV2EN Pair Channels 2 Inverting Enable 2 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV3EN Pair Channels 3 Inverting Enable 3 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 RESERVED no description available 4 28 read-only MOD Modulo 0x8 32 read-write n 0x0 0x0 MOD no description available 0 16 read-write RESERVED no description available 16 16 read-write MODE Features Mode Selection 0x54 32 read-write n 0x0 0x0 CAPTEST Capture Test Mode Enable 4 1 read-write 0 Capture test mode is disabled. #0 1 Capture test mode is enabled. #1 FAULTIE Fault Interrupt Enable 7 1 read-write 0 Fault control interrupt is disabled. #0 1 Fault control interrupt is enabled. #1 FAULTM Fault Control Mode 5 2 read-write 00 Fault control is disabled for all channels. #00 01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. #01 10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing. #10 11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. #11 FTMEN FTM Enable 0 1 read-write 0 Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not use the FTM-specific registers. #0 1 All registers including the FTM-specific registers (second set of registers) are available for use with no restrictions. #1 INIT Initialize the Channels Output 1 1 read-write PWMSYNC PWM Synchronization Mode 3 1 read-write 0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. #0 1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. #1 RESERVED no description available 8 24 read-only WPDIS Write Protection Disable 2 1 read-write 0 Write protection is enabled. #0 1 Write protection is disabled. #1 OUTINIT Initial State for Channels Output 0x5C 32 read-write n 0x0 0x0 CH0OI Channel 0 Output Initialization Value 0 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH1OI Channel 1 Output Initialization Value 1 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH2OI Channel 2 Output Initialization Value 2 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH3OI Channel 3 Output Initialization Value 3 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH4OI Channel 4 Output Initialization Value 4 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH5OI Channel 5 Output Initialization Value 5 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH6OI Channel 6 Output Initialization Value 6 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH7OI Channel 7 Output Initialization Value 7 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 RESERVED no description available 8 24 read-only OUTMASK Output Mask 0x60 32 read-write n 0x0 0x0 CH0OM Channel 0 Output Mask 0 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH1OM Channel 1 Output Mask 1 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH2OM Channel 2 Output Mask 2 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH3OM Channel 3 Output Mask 3 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH4OM Channel 4 Output Mask 4 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH5OM Channel 5 Output Mask 5 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH6OM Channel 6 Output Mask 6 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH7OM Channel 7 Output Mask 7 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 RESERVED no description available 8 24 read-only POL Channels Polarity 0x70 32 read-write n 0x0 0x0 POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL4 Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL5 Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL6 Channel 6 Polarity 6 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL7 Channel 7 Polarity 7 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 RESERVED no description available 8 24 read-write PWMLOAD FTM PWM Load 0x98 32 read-write n 0x0 0x0 CH0SEL Channel 0 Select 0 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH1SEL Channel 1 Select 1 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH2SEL Channel 2 Select 2 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH3SEL Channel 3 Select 3 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH4SEL Channel 4 Select 4 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH5SEL Channel 5 Select 5 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH6SEL Channel 6 Select 6 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH7SEL Channel 7 Select 7 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 LDOK Load Enable 9 1 read-write 0 Loading updated values is disabled. #0 1 Loading updated values is enabled. #1 RESERVED no description available 8 1 read-only RESERVED no description available 10 22 read-only QDCTRL Quadrature Decoder Control and Status 0x80 32 read-write n 0x0 0x0 PHAFLTREN Phase A Input Filter Enable 7 1 read-write 0 Phase A input filter is disabled. #0 1 Phase A input filter is enabled. #1 PHAPOL Phase A Input Polarity 5 1 read-write 0 Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal. #1 PHBFLTREN Phase B Input Filter Enable 6 1 read-write 0 Phase B input filter is disabled. #0 1 Phase B input filter is enabled. #1 PHBPOL Phase B Input Polarity 4 1 read-write 0 Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal. #1 QUADEN Quadrature Decoder Mode Enable 0 1 read-write 0 Quadrature decoder mode is disabled. #0 1 Quadrature decoder mode is enabled. #1 QUADIR FTM Counter Direction in Quadrature Decoder Mode 2 1 read-only 0 Counting direction is decreasing (FTM counter decrement). #0 1 Counting direction is increasing (FTM counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase A and phase B encoding mode. #0 1 Count and direction encoding mode. #1 RESERVED no description available 8 24 read-only TOFDIR Timer Overflow Direction in Quadrature Decoder Mode 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register). #1 SC Status and Control 0x0 32 read-write n 0x0 0x0 CLKS Clock Source Selection 3 2 read-write 00 No clock selected (This in effect disables the FTM counter.) #00 01 System clock #01 10 Fixed frequency clock #10 11 External clock #11 CPWMS Center-aligned PWM Select 5 1 read-write 0 FTM counter operates in up counting mode. #0 1 FTM counter operates in up-down counting mode. #1 PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 RESERVED no description available 8 24 read-only TOF Timer Overflow Flag 7 1 read-only 0 FTM counter has not overflowed. #0 1 FTM counter has overflowed. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 STATUS Capture and Compare Status 0x50 32 read-only n 0x0 0x0 CH0F Channel 0 Flag 0 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4F Channel 4 Flag 4 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5F Channel 5 Flag 5 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH6F Channel 6 Flag 6 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH7F Channel 7 Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 RESERVED no description available 8 24 read-only SWOCTRL FTM Software Output Control 0x94 32 read-write n 0x0 0x0 CH0OC Channel 0 Software Output Control Enable 0 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH0OCV Channel 0 Software Output Control Value 8 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH1OC Channel 1 Software Output Control Enable 1 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH1OCV Channel 1 Software Output Control Value 9 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH2OC Channel 2 Software Output Control Enable 2 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH2OCV Channel 2 Software Output Control Value 10 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH3OC Channel 3 Software Output Control Enable 3 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH3OCV Channel 3 Software Output Control Value 11 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH4OC Channel 4 Software Output Control Enable 4 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH4OCV Channel 4 Software Output Control Value 12 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH5OC Channel 5 Software Output Control Enable 5 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH5OCV Channel 5 Software Output Control Value 13 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH6OC Channel 6 Software Output Control Enable 6 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH6OCV Channel 6 Software Output Control Value 14 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH7OC Channel 7 Software Output Control Enable 7 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH7OCV Channel 7 Software Output Control Value 15 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 RESERVED no description available 16 16 read-only SYNC Synchronization 0x58 32 read-write n 0x0 0x0 CNTMAX Maximum loading point enable 1 1 read-write 0 The maximum loading point is disabled. #0 1 The maximum loading point is enabled. #1 CNTMIN Minimum loading point enable 0 1 read-write 0 The minimum loading point is disabled. #0 1 The minimum loading point is enabled. #1 REINIT FTM Counter Reinitialization by Synchronization (FTM Counter Synchronization) 2 1 read-write 0 FTM counter continues to count normally. #0 1 FTM counter is updated with its initial value when the selected trigger is detected. #1 RESERVED no description available 8 24 read-only SWSYNC PWM Synchronization Software Trigger 7 1 read-write 0 Software trigger is not selected. #0 1 Software trigger is selected. #1 SYNCHOM Output Mask Synchronization 3 1 read-write 0 OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. #0 1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization. #1 TRIG0 PWM Synchronization Hardware Trigger 0 4 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG1 PWM Synchronization Hardware Trigger 1 5 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG2 PWM Synchronization Hardware Trigger 2 6 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 SYNCONF Synchronization Configuration 0x8C 32 read-write n 0x0 0x0 CNTINC CNTIN register synchronization 2 1 read-write 0 CNTIN register is updated with its buffer value at all rising edges of system clock. #0 1 CNTIN register is updated with its buffer value by the PWM synchronization. #1 HWINVC no description available 19 1 read-write 0 A hardware trigger does not activate the INVCTRL register synchronization. #0 1 A hardware trigger activates the INVCTRL register synchronization. #1 HWOM no description available 18 1 read-write 0 A hardware trigger does not activate the OUTMASK register synchronization. #0 1 A hardware trigger activates the OUTMASK register synchronization. #1 HWRSTCNT no description available 16 1 read-write 0 A hardware trigger does not activate the FTM counter synchronization. #0 1 A hardware trigger activates the FTM counter synchronization. #1 HWSOC no description available 20 1 read-write 0 A hardware trigger does not activate the SWOCTRL register synchronization. #0 1 A hardware trigger activates the SWOCTRL register synchronization. #1 HWTRIGMODE Hardware Trigger Mode 0 1 read-write 0 FTM clears the TRIGj bit when the hardware trigger j is detected. #0 1 FTM does not clear the TRIGj bit when the hardware trigger j is detected. #1 HWWRBUF no description available 17 1 read-write 0 A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 A hardware trigger activates MOD, CNTIN, and CV registers synchronization. #1 INVC INVCTRL register synchronization 4 1 read-write 0 INVCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 INVCTRL register is updated with its buffer value by the PWM synchronization. #1 RESERVED no description available 1 1 read-only RESERVED no description available 3 1 read-only RESERVED no description available 6 1 read-only RESERVED no description available 13 3 read-only RESERVED no description available 21 11 read-only SWINVC no description available 11 1 read-write 0 The software trigger does not activate the INVCTRL register synchronization. #0 1 The software trigger activates the INVCTRL register synchronization. #1 SWOC SWOCTRL register synchronization 5 1 read-write 0 SWOCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 SWOCTRL register is updated with its buffer value by the PWM synchronization. #1 SWOM no description available 10 1 read-write 0 The software trigger does not activate the OUTMASK register synchronization. #0 1 The software trigger activates the OUTMASK register synchronization. #1 SWRSTCNT no description available 8 1 read-write 0 The software trigger does not activate the FTM counter synchronization. #0 1 The software trigger activates the FTM counter synchronization. #1 SWSOC no description available 12 1 read-write 0 The software trigger does not activate the SWOCTRL register synchronization. #0 1 The software trigger activates the SWOCTRL register synchronization. #1 SWWRBUF no description available 9 1 read-write 0 The software trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 The software trigger activates MOD, CNTIN, and CV registers synchronization. #1 SYNCMODE Synchronization Mode 7 1 read-write 0 Legacy PWM synchronization is selected. #0 1 Enhanced PWM synchronization is selected. #1 FTM2 FlexTimer Module FTM 0x0 0x0 0x9C registers n FTM2 64 INT_FTM2 80 C0SC Channel (n) Status and Control 0x18 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write RESERVED no description available 1 1 read-only RESERVED no description available 8 24 read-only C0V Channel (n) Value 0x20 32 read-write n 0x0 0x0 RESERVED no description available 16 16 read-only VAL Channel Value 0 16 read-write C1SC Channel (n) Status and Control 0x2C 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write RESERVED no description available 1 1 read-only RESERVED no description available 8 24 read-only C1V Channel (n) Value 0x38 32 read-write n 0x0 0x0 RESERVED no description available 16 16 read-only VAL Channel Value 0 16 read-write CNT Counter 0x4 32 read-write n 0x0 0x0 COUNT Counter value 0 16 read-write RESERVED no description available 16 16 read-only CNTIN Counter Initial Value 0x4C 32 read-write n 0x0 0x0 INIT no description available 0 16 read-write RESERVED no description available 16 16 read-write COMBINE Function for Linked Channels 0x64 32 read-write n 0x0 0x0 COMBINE0 Combine Channels for n = 0 0 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMBINE1 Combine Channels for n = 2 8 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMBINE2 Combine Channels for n = 4 16 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMBINE3 Combine Channels for n = 6 24 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP0 Complement of Channel (n) for n = 0 1 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 COMP1 Complement of Channel (n) for n = 2 9 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 COMP2 Complement of Channel (n) for n = 4 17 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 COMP3 Complement of Channel (n) for n = 6 25 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAP0 Dual Edge Capture Mode Captures for n = 0 3 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAP1 Dual Edge Capture Mode Captures for n = 2 11 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAP2 Dual Edge Capture Mode Captures for n = 4 19 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAP3 Dual Edge Capture Mode Captures for n = 6 27 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAPEN0 Dual Edge Capture Mode Enable for n = 0 2 1 read-write 0 The dual edge capture mode in this pair of channels is disabled. #0 1 The dual edge capture mode in this pair of channels is enabled. #1 DECAPEN1 Dual Edge Capture Mode Enable for n = 2 10 1 read-write 0 The dual edge capture mode in this pair of channels is disabled. #0 1 The dual edge capture mode in this pair of channels is enabled. #1 DECAPEN2 Dual Edge Capture Mode Enable for n = 4 18 1 read-write 0 The dual edge capture mode in this pair of channels is disabled. #0 1 The dual edge capture mode in this pair of channels is enabled. #1 DECAPEN3 Dual Edge Capture Mode Enable for n = 6 26 1 read-write 0 The dual edge capture mode in this pair of channels is disabled. #0 1 The dual edge capture mode in this pair of channels is enabled. #1 DTEN0 Deadtime Enable for n = 0 4 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 DTEN1 Deadtime Enable for n = 2 12 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 DTEN2 Deadtime Enable for n = 4 20 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 DTEN3 Deadtime Enable for n = 6 28 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 FAULTEN0 Fault Control Enable for n = 0 6 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 FAULTEN1 Fault Control Enable for n = 2 14 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 FAULTEN2 Fault Control Enable for n = 4 22 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 FAULTEN3 Fault Control Enable for n = 6 30 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 RESERVED no description available 7 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 31 1 read-only SYNCEN0 Synchronization Enable for n = 0 5 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 SYNCEN1 Synchronization Enable for n = 2 13 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 SYNCEN2 Synchronization Enable for n = 4 21 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 SYNCEN3 Synchronization Enable for n = 6 29 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 CONF Configuration 0x84 32 read-write n 0x0 0x0 BDMMODE BDM Mode 6 2 read-write GTBEEN Global time base enable 9 1 read-write 0 Use of an external global time base is disabled. #0 1 Use of an external global time base is enabled. #1 GTBEOUT Global time base output 10 1 read-write 0 A global time base signal generation is disabled. #0 1 A global time base signal generation is enabled. #1 NUMTOF TOF Frequency 0 5 read-write RESERVED no description available 5 1 read-only RESERVED no description available 8 1 read-only RESERVED no description available 11 21 read-only DEADTIME Deadtime Insertion Control 0x68 32 read-write n 0x0 0x0 DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the system clock by 1. #0x 10 Divide the system clock by 4. #10 11 Divide the system clock by 16. #11 DTVAL Deadtime Value 0 6 read-write RESERVED no description available 8 24 read-only EXTTRIG FTM External Trigger 0x6C 32 read-write n 0x0 0x0 CH0TRIG Channel 0 Trigger Enable 4 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH1TRIG Channel 1 Trigger Enable 5 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH2TRIG Channel 2 Trigger Enable 0 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH3TRIG Channel 3 Trigger Enable 1 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH4TRIG Channel 4 Trigger Enable 2 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH5TRIG Channel 5 Trigger Enable 3 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 INITTRIGEN Initialization Trigger Enable 6 1 read-write 0 The generation of initialization trigger is disabled. #0 1 The generation of initialization trigger is enabled. #1 RESERVED no description available 8 24 read-write TRIGF Channel Trigger Flag 7 1 read-write 0 No channel trigger was generated. #0 1 A channel trigger was generated. #1 FILTER Input Capture Filter Control 0x78 32 read-write n 0x0 0x0 CH0FVAL Channel 0 Input Filter 0 4 read-write CH1FVAL Channel 1 Input Filter 4 4 read-write CH2FVAL Channel 2 Input Filter 8 4 read-write CH3FVAL Channel 3 Input Filter 12 4 read-write RESERVED no description available 16 16 read-write FLTCTRL Fault Control 0x7C 32 read-write n 0x0 0x0 FAULT0EN Fault Input 0 Enable 0 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT1EN Fault Input 1 Enable 1 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT2EN Fault Input 2 Enable 2 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT3EN Fault Input 3 Enable 3 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FFLTR0EN Fault Input 0 Filter Enable 4 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR1EN Fault Input 1 Filter Enable 5 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR2EN Fault Input 2 Filter Enable 6 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR3EN Fault Input 3 Filter Enable 7 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFVAL Fault Input Filter 8 4 read-write RESERVED no description available 12 20 read-only FLTPOL FTM Fault Input Polarity 0x88 32 read-write n 0x0 0x0 FLT0POL Fault Input 0 Polarity 0 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT1POL Fault Input 1 Polarity 1 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT2POL Fault Input 2 Polarity 2 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT3POL Fault Input 3 Polarity 3 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 RESERVED no description available 4 28 read-only FMS Fault Mode Status 0x74 32 read-write n 0x0 0x0 FAULTF Fault Detection Flag 7 1 read-only 0 No fault condition was detected. #0 1 A fault condition was detected. #1 FAULTF0 Fault Detection Flag 0 0 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF1 Fault Detection Flag 1 1 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF2 Fault Detection Flag 2 2 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF3 Fault Detection Flag 3 3 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTIN Fault Inputs 5 1 read-only 0 The logic OR of the enabled fault inputs is 0. #0 1 The logic OR of the enabled fault inputs is 1. #1 RESERVED no description available 4 1 read-only RESERVED no description available 8 24 read-only WPEN Write Protection Enable 6 1 read-write 0 Write protection is disabled. Write protected bits can be written. #0 1 Write protection is enabled. Write protected bits cannot be written. #1 INVCTRL FTM Inverting Control 0x90 32 read-write n 0x0 0x0 INV0EN Pair Channels 0 Inverting Enable 0 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV1EN Pair Channels 1 Inverting Enable 1 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV2EN Pair Channels 2 Inverting Enable 2 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV3EN Pair Channels 3 Inverting Enable 3 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 RESERVED no description available 4 28 read-only MOD Modulo 0x8 32 read-write n 0x0 0x0 MOD no description available 0 16 read-write RESERVED no description available 16 16 read-write MODE Features Mode Selection 0x54 32 read-write n 0x0 0x0 CAPTEST Capture Test Mode Enable 4 1 read-write 0 Capture test mode is disabled. #0 1 Capture test mode is enabled. #1 FAULTIE Fault Interrupt Enable 7 1 read-write 0 Fault control interrupt is disabled. #0 1 Fault control interrupt is enabled. #1 FAULTM Fault Control Mode 5 2 read-write 00 Fault control is disabled for all channels. #00 01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. #01 10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing. #10 11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. #11 FTMEN FTM Enable 0 1 read-write 0 Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not use the FTM-specific registers. #0 1 All registers including the FTM-specific registers (second set of registers) are available for use with no restrictions. #1 INIT Initialize the Channels Output 1 1 read-write PWMSYNC PWM Synchronization Mode 3 1 read-write 0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. #0 1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. #1 RESERVED no description available 8 24 read-only WPDIS Write Protection Disable 2 1 read-write 0 Write protection is enabled. #0 1 Write protection is disabled. #1 OUTINIT Initial State for Channels Output 0x5C 32 read-write n 0x0 0x0 CH0OI Channel 0 Output Initialization Value 0 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH1OI Channel 1 Output Initialization Value 1 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH2OI Channel 2 Output Initialization Value 2 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH3OI Channel 3 Output Initialization Value 3 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH4OI Channel 4 Output Initialization Value 4 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH5OI Channel 5 Output Initialization Value 5 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH6OI Channel 6 Output Initialization Value 6 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH7OI Channel 7 Output Initialization Value 7 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 RESERVED no description available 8 24 read-only OUTMASK Output Mask 0x60 32 read-write n 0x0 0x0 CH0OM Channel 0 Output Mask 0 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH1OM Channel 1 Output Mask 1 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH2OM Channel 2 Output Mask 2 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH3OM Channel 3 Output Mask 3 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH4OM Channel 4 Output Mask 4 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH5OM Channel 5 Output Mask 5 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH6OM Channel 6 Output Mask 6 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH7OM Channel 7 Output Mask 7 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 RESERVED no description available 8 24 read-only POL Channels Polarity 0x70 32 read-write n 0x0 0x0 POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL4 Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL5 Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL6 Channel 6 Polarity 6 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL7 Channel 7 Polarity 7 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 RESERVED no description available 8 24 read-write PWMLOAD FTM PWM Load 0x98 32 read-write n 0x0 0x0 CH0SEL Channel 0 Select 0 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH1SEL Channel 1 Select 1 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH2SEL Channel 2 Select 2 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH3SEL Channel 3 Select 3 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH4SEL Channel 4 Select 4 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH5SEL Channel 5 Select 5 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH6SEL Channel 6 Select 6 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH7SEL Channel 7 Select 7 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 LDOK Load Enable 9 1 read-write 0 Loading updated values is disabled. #0 1 Loading updated values is enabled. #1 RESERVED no description available 8 1 read-only RESERVED no description available 10 22 read-only QDCTRL Quadrature Decoder Control and Status 0x80 32 read-write n 0x0 0x0 PHAFLTREN Phase A Input Filter Enable 7 1 read-write 0 Phase A input filter is disabled. #0 1 Phase A input filter is enabled. #1 PHAPOL Phase A Input Polarity 5 1 read-write 0 Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal. #1 PHBFLTREN Phase B Input Filter Enable 6 1 read-write 0 Phase B input filter is disabled. #0 1 Phase B input filter is enabled. #1 PHBPOL Phase B Input Polarity 4 1 read-write 0 Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal. #1 QUADEN Quadrature Decoder Mode Enable 0 1 read-write 0 Quadrature decoder mode is disabled. #0 1 Quadrature decoder mode is enabled. #1 QUADIR FTM Counter Direction in Quadrature Decoder Mode 2 1 read-only 0 Counting direction is decreasing (FTM counter decrement). #0 1 Counting direction is increasing (FTM counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase A and phase B encoding mode. #0 1 Count and direction encoding mode. #1 RESERVED no description available 8 24 read-only TOFDIR Timer Overflow Direction in Quadrature Decoder Mode 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register). #1 SC Status and Control 0x0 32 read-write n 0x0 0x0 CLKS Clock Source Selection 3 2 read-write 00 No clock selected (This in effect disables the FTM counter.) #00 01 System clock #01 10 Fixed frequency clock #10 11 External clock #11 CPWMS Center-aligned PWM Select 5 1 read-write 0 FTM counter operates in up counting mode. #0 1 FTM counter operates in up-down counting mode. #1 PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 RESERVED no description available 8 24 read-only TOF Timer Overflow Flag 7 1 read-only 0 FTM counter has not overflowed. #0 1 FTM counter has overflowed. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 STATUS Capture and Compare Status 0x50 32 read-only n 0x0 0x0 CH0F Channel 0 Flag 0 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4F Channel 4 Flag 4 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5F Channel 5 Flag 5 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH6F Channel 6 Flag 6 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH7F Channel 7 Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 RESERVED no description available 8 24 read-only SWOCTRL FTM Software Output Control 0x94 32 read-write n 0x0 0x0 CH0OC Channel 0 Software Output Control Enable 0 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH0OCV Channel 0 Software Output Control Value 8 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH1OC Channel 1 Software Output Control Enable 1 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH1OCV Channel 1 Software Output Control Value 9 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH2OC Channel 2 Software Output Control Enable 2 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH2OCV Channel 2 Software Output Control Value 10 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH3OC Channel 3 Software Output Control Enable 3 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH3OCV Channel 3 Software Output Control Value 11 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH4OC Channel 4 Software Output Control Enable 4 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH4OCV Channel 4 Software Output Control Value 12 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH5OC Channel 5 Software Output Control Enable 5 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH5OCV Channel 5 Software Output Control Value 13 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH6OC Channel 6 Software Output Control Enable 6 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH6OCV Channel 6 Software Output Control Value 14 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH7OC Channel 7 Software Output Control Enable 7 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH7OCV Channel 7 Software Output Control Value 15 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 RESERVED no description available 16 16 read-only SYNC Synchronization 0x58 32 read-write n 0x0 0x0 CNTMAX Maximum loading point enable 1 1 read-write 0 The maximum loading point is disabled. #0 1 The maximum loading point is enabled. #1 CNTMIN Minimum loading point enable 0 1 read-write 0 The minimum loading point is disabled. #0 1 The minimum loading point is enabled. #1 REINIT FTM Counter Reinitialization by Synchronization (FTM Counter Synchronization) 2 1 read-write 0 FTM counter continues to count normally. #0 1 FTM counter is updated with its initial value when the selected trigger is detected. #1 RESERVED no description available 8 24 read-only SWSYNC PWM Synchronization Software Trigger 7 1 read-write 0 Software trigger is not selected. #0 1 Software trigger is selected. #1 SYNCHOM Output Mask Synchronization 3 1 read-write 0 OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. #0 1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization. #1 TRIG0 PWM Synchronization Hardware Trigger 0 4 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG1 PWM Synchronization Hardware Trigger 1 5 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG2 PWM Synchronization Hardware Trigger 2 6 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 SYNCONF Synchronization Configuration 0x8C 32 read-write n 0x0 0x0 CNTINC CNTIN register synchronization 2 1 read-write 0 CNTIN register is updated with its buffer value at all rising edges of system clock. #0 1 CNTIN register is updated with its buffer value by the PWM synchronization. #1 HWINVC no description available 19 1 read-write 0 A hardware trigger does not activate the INVCTRL register synchronization. #0 1 A hardware trigger activates the INVCTRL register synchronization. #1 HWOM no description available 18 1 read-write 0 A hardware trigger does not activate the OUTMASK register synchronization. #0 1 A hardware trigger activates the OUTMASK register synchronization. #1 HWRSTCNT no description available 16 1 read-write 0 A hardware trigger does not activate the FTM counter synchronization. #0 1 A hardware trigger activates the FTM counter synchronization. #1 HWSOC no description available 20 1 read-write 0 A hardware trigger does not activate the SWOCTRL register synchronization. #0 1 A hardware trigger activates the SWOCTRL register synchronization. #1 HWTRIGMODE Hardware Trigger Mode 0 1 read-write 0 FTM clears the TRIGj bit when the hardware trigger j is detected. #0 1 FTM does not clear the TRIGj bit when the hardware trigger j is detected. #1 HWWRBUF no description available 17 1 read-write 0 A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 A hardware trigger activates MOD, CNTIN, and CV registers synchronization. #1 INVC INVCTRL register synchronization 4 1 read-write 0 INVCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 INVCTRL register is updated with its buffer value by the PWM synchronization. #1 RESERVED no description available 1 1 read-only RESERVED no description available 3 1 read-only RESERVED no description available 6 1 read-only RESERVED no description available 13 3 read-only RESERVED no description available 21 11 read-only SWINVC no description available 11 1 read-write 0 The software trigger does not activate the INVCTRL register synchronization. #0 1 The software trigger activates the INVCTRL register synchronization. #1 SWOC SWOCTRL register synchronization 5 1 read-write 0 SWOCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 SWOCTRL register is updated with its buffer value by the PWM synchronization. #1 SWOM no description available 10 1 read-write 0 The software trigger does not activate the OUTMASK register synchronization. #0 1 The software trigger activates the OUTMASK register synchronization. #1 SWRSTCNT no description available 8 1 read-write 0 The software trigger does not activate the FTM counter synchronization. #0 1 The software trigger activates the FTM counter synchronization. #1 SWSOC no description available 12 1 read-write 0 The software trigger does not activate the SWOCTRL register synchronization. #0 1 The software trigger activates the SWOCTRL register synchronization. #1 SWWRBUF no description available 9 1 read-write 0 The software trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 The software trigger activates MOD, CNTIN, and CV registers synchronization. #1 SYNCMODE Synchronization Mode 7 1 read-write 0 Legacy PWM synchronization is selected. #0 1 Enhanced PWM synchronization is selected. #1 FTM3 FlexTimer Module FTM 0x0 0x0 0x9C registers n FTM3 101 INT_FTM3 117 C0SC Channel (n) Status and Control 0x18 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write RESERVED no description available 1 1 read-only RESERVED no description available 8 24 read-only C0V Channel (n) Value 0x20 32 read-write n 0x0 0x0 RESERVED no description available 16 16 read-only VAL Channel Value 0 16 read-write C1SC Channel (n) Status and Control 0x2C 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write RESERVED no description available 1 1 read-only RESERVED no description available 8 24 read-only C1V Channel (n) Value 0x38 32 read-write n 0x0 0x0 RESERVED no description available 16 16 read-only VAL Channel Value 0 16 read-write C2SC Channel (n) Status and Control 0x48 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write RESERVED no description available 1 1 read-only RESERVED no description available 8 24 read-only C2V Channel (n) Value 0x58 32 read-write n 0x0 0x0 RESERVED no description available 16 16 read-only VAL Channel Value 0 16 read-write C3SC Channel (n) Status and Control 0x6C 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write RESERVED no description available 1 1 read-only RESERVED no description available 8 24 read-only C3V Channel (n) Value 0x80 32 read-write n 0x0 0x0 RESERVED no description available 16 16 read-only VAL Channel Value 0 16 read-write C4SC Channel (n) Status and Control 0x98 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write RESERVED no description available 1 1 read-only RESERVED no description available 8 24 read-only C4V Channel (n) Value 0xB0 32 read-write n 0x0 0x0 RESERVED no description available 16 16 read-only VAL Channel Value 0 16 read-write C5SC Channel (n) Status and Control 0xCC 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write RESERVED no description available 1 1 read-only RESERVED no description available 8 24 read-only C5V Channel (n) Value 0xE8 32 read-write n 0x0 0x0 RESERVED no description available 16 16 read-only VAL Channel Value 0 16 read-write C6SC Channel (n) Status and Control 0x108 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write RESERVED no description available 1 1 read-only RESERVED no description available 8 24 read-only C6V Channel (n) Value 0x128 32 read-write n 0x0 0x0 RESERVED no description available 16 16 read-only VAL Channel Value 0 16 read-write C7SC Channel (n) Status and Control 0x14C 32 read-write n 0x0 0x0 CHF Channel Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CHIE Channel Interrupt Enable 6 1 read-write 0 Disable channel interrupts. Use software polling. #0 1 Enable channel interrupts. #1 DMA DMA Enable 0 1 read-write 0 Disable DMA transfers. #0 1 Enable DMA transfers. #1 ELSA Edge or Level Select 2 1 read-write ELSB Edge or Level Select 3 1 read-write MSA Channel Mode Select 4 1 read-write MSB Channel Mode Select 5 1 read-write RESERVED no description available 1 1 read-only RESERVED no description available 8 24 read-only C7V Channel (n) Value 0x170 32 read-write n 0x0 0x0 RESERVED no description available 16 16 read-only VAL Channel Value 0 16 read-write CNT Counter 0x4 32 read-write n 0x0 0x0 COUNT Counter value 0 16 read-write RESERVED no description available 16 16 read-only CNTIN Counter Initial Value 0x4C 32 read-write n 0x0 0x0 INIT no description available 0 16 read-write RESERVED no description available 16 16 read-write COMBINE Function for Linked Channels 0x64 32 read-write n 0x0 0x0 COMBINE0 Combine Channels for n = 0 0 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMBINE1 Combine Channels for n = 2 8 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMBINE2 Combine Channels for n = 4 16 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMBINE3 Combine Channels for n = 6 24 1 read-write 0 Channels (n) and (n+1) are independent. #0 1 Channels (n) and (n+1) are combined. #1 COMP0 Complement of Channel (n) for n = 0 1 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 COMP1 Complement of Channel (n) for n = 2 9 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 COMP2 Complement of Channel (n) for n = 4 17 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 COMP3 Complement of Channel (n) for n = 6 25 1 read-write 0 The channel (n+1) output is the same as the channel (n) output. #0 1 The channel (n+1) output is the complement of the channel (n) output. #1 DECAP0 Dual Edge Capture Mode Captures for n = 0 3 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAP1 Dual Edge Capture Mode Captures for n = 2 11 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAP2 Dual Edge Capture Mode Captures for n = 4 19 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAP3 Dual Edge Capture Mode Captures for n = 6 27 1 read-write 0 The dual edge captures are inactive. #0 1 The dual edge captures are active. #1 DECAPEN0 Dual Edge Capture Mode Enable for n = 0 2 1 read-write 0 The dual edge capture mode in this pair of channels is disabled. #0 1 The dual edge capture mode in this pair of channels is enabled. #1 DECAPEN1 Dual Edge Capture Mode Enable for n = 2 10 1 read-write 0 The dual edge capture mode in this pair of channels is disabled. #0 1 The dual edge capture mode in this pair of channels is enabled. #1 DECAPEN2 Dual Edge Capture Mode Enable for n = 4 18 1 read-write 0 The dual edge capture mode in this pair of channels is disabled. #0 1 The dual edge capture mode in this pair of channels is enabled. #1 DECAPEN3 Dual Edge Capture Mode Enable for n = 6 26 1 read-write 0 The dual edge capture mode in this pair of channels is disabled. #0 1 The dual edge capture mode in this pair of channels is enabled. #1 DTEN0 Deadtime Enable for n = 0 4 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 DTEN1 Deadtime Enable for n = 2 12 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 DTEN2 Deadtime Enable for n = 4 20 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 DTEN3 Deadtime Enable for n = 6 28 1 read-write 0 The deadtime insertion in this pair of channels is disabled. #0 1 The deadtime insertion in this pair of channels is enabled. #1 FAULTEN0 Fault Control Enable for n = 0 6 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 FAULTEN1 Fault Control Enable for n = 2 14 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 FAULTEN2 Fault Control Enable for n = 4 22 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 FAULTEN3 Fault Control Enable for n = 6 30 1 read-write 0 The fault control in this pair of channels is disabled. #0 1 The fault control in this pair of channels is enabled. #1 RESERVED no description available 7 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 31 1 read-only SYNCEN0 Synchronization Enable for n = 0 5 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 SYNCEN1 Synchronization Enable for n = 2 13 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 SYNCEN2 Synchronization Enable for n = 4 21 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 SYNCEN3 Synchronization Enable for n = 6 29 1 read-write 0 The PWM synchronization in this pair of channels is disabled. #0 1 The PWM synchronization in this pair of channels is enabled. #1 CONF Configuration 0x84 32 read-write n 0x0 0x0 BDMMODE BDM Mode 6 2 read-write GTBEEN Global time base enable 9 1 read-write 0 Use of an external global time base is disabled. #0 1 Use of an external global time base is enabled. #1 GTBEOUT Global time base output 10 1 read-write 0 A global time base signal generation is disabled. #0 1 A global time base signal generation is enabled. #1 NUMTOF TOF Frequency 0 5 read-write RESERVED no description available 5 1 read-only RESERVED no description available 8 1 read-only RESERVED no description available 11 21 read-only DEADTIME Deadtime Insertion Control 0x68 32 read-write n 0x0 0x0 DTPS Deadtime Prescaler Value 6 2 read-write 0x Divide the system clock by 1. #0x 10 Divide the system clock by 4. #10 11 Divide the system clock by 16. #11 DTVAL Deadtime Value 0 6 read-write RESERVED no description available 8 24 read-only EXTTRIG FTM External Trigger 0x6C 32 read-write n 0x0 0x0 CH0TRIG Channel 0 Trigger Enable 4 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH1TRIG Channel 1 Trigger Enable 5 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH2TRIG Channel 2 Trigger Enable 0 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH3TRIG Channel 3 Trigger Enable 1 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH4TRIG Channel 4 Trigger Enable 2 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 CH5TRIG Channel 5 Trigger Enable 3 1 read-write 0 The generation of the channel trigger is disabled. #0 1 The generation of the channel trigger is enabled. #1 INITTRIGEN Initialization Trigger Enable 6 1 read-write 0 The generation of initialization trigger is disabled. #0 1 The generation of initialization trigger is enabled. #1 RESERVED no description available 8 24 read-write TRIGF Channel Trigger Flag 7 1 read-write 0 No channel trigger was generated. #0 1 A channel trigger was generated. #1 FILTER Input Capture Filter Control 0x78 32 read-write n 0x0 0x0 CH0FVAL Channel 0 Input Filter 0 4 read-write CH1FVAL Channel 1 Input Filter 4 4 read-write CH2FVAL Channel 2 Input Filter 8 4 read-write CH3FVAL Channel 3 Input Filter 12 4 read-write RESERVED no description available 16 16 read-write FLTCTRL Fault Control 0x7C 32 read-write n 0x0 0x0 FAULT0EN Fault Input 0 Enable 0 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT1EN Fault Input 1 Enable 1 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT2EN Fault Input 2 Enable 2 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FAULT3EN Fault Input 3 Enable 3 1 read-write 0 Fault input is disabled. #0 1 Fault input is enabled. #1 FFLTR0EN Fault Input 0 Filter Enable 4 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR1EN Fault Input 1 Filter Enable 5 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR2EN Fault Input 2 Filter Enable 6 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFLTR3EN Fault Input 3 Filter Enable 7 1 read-write 0 Fault input filter is disabled. #0 1 Fault input filter is enabled. #1 FFVAL Fault Input Filter 8 4 read-write RESERVED no description available 12 20 read-only FLTPOL FTM Fault Input Polarity 0x88 32 read-write n 0x0 0x0 FLT0POL Fault Input 0 Polarity 0 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT1POL Fault Input 1 Polarity 1 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT2POL Fault Input 2 Polarity 2 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 FLT3POL Fault Input 3 Polarity 3 1 read-write 0 The fault input polarity is active high. A one at the fault input indicates a fault. #0 1 The fault input polarity is active low. A zero at the fault input indicates a fault. #1 RESERVED no description available 4 28 read-only FMS Fault Mode Status 0x74 32 read-write n 0x0 0x0 FAULTF Fault Detection Flag 7 1 read-only 0 No fault condition was detected. #0 1 A fault condition was detected. #1 FAULTF0 Fault Detection Flag 0 0 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF1 Fault Detection Flag 1 1 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF2 Fault Detection Flag 2 2 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTF3 Fault Detection Flag 3 3 1 read-only 0 No fault condition was detected at the fault input. #0 1 A fault condition was detected at the fault input. #1 FAULTIN Fault Inputs 5 1 read-only 0 The logic OR of the enabled fault inputs is 0. #0 1 The logic OR of the enabled fault inputs is 1. #1 RESERVED no description available 4 1 read-only RESERVED no description available 8 24 read-only WPEN Write Protection Enable 6 1 read-write 0 Write protection is disabled. Write protected bits can be written. #0 1 Write protection is enabled. Write protected bits cannot be written. #1 INVCTRL FTM Inverting Control 0x90 32 read-write n 0x0 0x0 INV0EN Pair Channels 0 Inverting Enable 0 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV1EN Pair Channels 1 Inverting Enable 1 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV2EN Pair Channels 2 Inverting Enable 2 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 INV3EN Pair Channels 3 Inverting Enable 3 1 read-write 0 Inverting is disabled. #0 1 Inverting is enabled. #1 RESERVED no description available 4 28 read-only MOD Modulo 0x8 32 read-write n 0x0 0x0 MOD no description available 0 16 read-write RESERVED no description available 16 16 read-write MODE Features Mode Selection 0x54 32 read-write n 0x0 0x0 CAPTEST Capture Test Mode Enable 4 1 read-write 0 Capture test mode is disabled. #0 1 Capture test mode is enabled. #1 FAULTIE Fault Interrupt Enable 7 1 read-write 0 Fault control interrupt is disabled. #0 1 Fault control interrupt is enabled. #1 FAULTM Fault Control Mode 5 2 read-write 00 Fault control is disabled for all channels. #00 01 Fault control is enabled for even channels only (channels 0, 2, 4, and 6), and the selected mode is the manual fault clearing. #01 10 Fault control is enabled for all channels, and the selected mode is the manual fault clearing. #10 11 Fault control is enabled for all channels, and the selected mode is the automatic fault clearing. #11 FTMEN FTM Enable 0 1 read-write 0 Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not use the FTM-specific registers. #0 1 All registers including the FTM-specific registers (second set of registers) are available for use with no restrictions. #1 INIT Initialize the Channels Output 1 1 read-write PWMSYNC PWM Synchronization Mode 3 1 read-write 0 No restrictions. Software and hardware triggers can be used by MOD, CnV, OUTMASK, and FTM counter synchronization. #0 1 Software trigger can only be used by MOD and CnV synchronization, and hardware triggers can only be used by OUTMASK and FTM counter synchronization. #1 RESERVED no description available 8 24 read-only WPDIS Write Protection Disable 2 1 read-write 0 Write protection is enabled. #0 1 Write protection is disabled. #1 OUTINIT Initial State for Channels Output 0x5C 32 read-write n 0x0 0x0 CH0OI Channel 0 Output Initialization Value 0 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH1OI Channel 1 Output Initialization Value 1 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH2OI Channel 2 Output Initialization Value 2 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH3OI Channel 3 Output Initialization Value 3 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH4OI Channel 4 Output Initialization Value 4 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH5OI Channel 5 Output Initialization Value 5 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH6OI Channel 6 Output Initialization Value 6 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 CH7OI Channel 7 Output Initialization Value 7 1 read-write 0 The initialization value is 0. #0 1 The initialization value is 1. #1 RESERVED no description available 8 24 read-only OUTMASK Output Mask 0x60 32 read-write n 0x0 0x0 CH0OM Channel 0 Output Mask 0 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH1OM Channel 1 Output Mask 1 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH2OM Channel 2 Output Mask 2 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH3OM Channel 3 Output Mask 3 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH4OM Channel 4 Output Mask 4 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH5OM Channel 5 Output Mask 5 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH6OM Channel 6 Output Mask 6 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 CH7OM Channel 7 Output Mask 7 1 read-write 0 Channel output is not masked. It continues to operate normally. #0 1 Channel output is masked. It is forced to its inactive state. #1 RESERVED no description available 8 24 read-only POL Channels Polarity 0x70 32 read-write n 0x0 0x0 POL0 Channel 0 Polarity 0 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL1 Channel 1 Polarity 1 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL2 Channel 2 Polarity 2 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL3 Channel 3 Polarity 3 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL4 Channel 4 Polarity 4 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL5 Channel 5 Polarity 5 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL6 Channel 6 Polarity 6 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 POL7 Channel 7 Polarity 7 1 read-write 0 The channel polarity is active high. #0 1 The channel polarity is active low. #1 RESERVED no description available 8 24 read-write PWMLOAD FTM PWM Load 0x98 32 read-write n 0x0 0x0 CH0SEL Channel 0 Select 0 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH1SEL Channel 1 Select 1 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH2SEL Channel 2 Select 2 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH3SEL Channel 3 Select 3 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH4SEL Channel 4 Select 4 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH5SEL Channel 5 Select 5 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH6SEL Channel 6 Select 6 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 CH7SEL Channel 7 Select 7 1 read-write 0 Do not include the channel in the matching process. #0 1 Include the channel in the matching process. #1 LDOK Load Enable 9 1 read-write 0 Loading updated values is disabled. #0 1 Loading updated values is enabled. #1 RESERVED no description available 8 1 read-only RESERVED no description available 10 22 read-only QDCTRL Quadrature Decoder Control and Status 0x80 32 read-write n 0x0 0x0 PHAFLTREN Phase A Input Filter Enable 7 1 read-write 0 Phase A input filter is disabled. #0 1 Phase A input filter is enabled. #1 PHAPOL Phase A Input Polarity 5 1 read-write 0 Normal polarity. Phase A input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase A input signal is inverted before identifying the rising and falling edges of this signal. #1 PHBFLTREN Phase B Input Filter Enable 6 1 read-write 0 Phase B input filter is disabled. #0 1 Phase B input filter is enabled. #1 PHBPOL Phase B Input Polarity 4 1 read-write 0 Normal polarity. Phase B input signal is not inverted before identifying the rising and falling edges of this signal. #0 1 Inverted polarity. Phase B input signal is inverted before identifying the rising and falling edges of this signal. #1 QUADEN Quadrature Decoder Mode Enable 0 1 read-write 0 Quadrature decoder mode is disabled. #0 1 Quadrature decoder mode is enabled. #1 QUADIR FTM Counter Direction in Quadrature Decoder Mode 2 1 read-only 0 Counting direction is decreasing (FTM counter decrement). #0 1 Counting direction is increasing (FTM counter increment). #1 QUADMODE Quadrature Decoder Mode 3 1 read-write 0 Phase A and phase B encoding mode. #0 1 Count and direction encoding mode. #1 RESERVED no description available 8 24 read-only TOFDIR Timer Overflow Direction in Quadrature Decoder Mode 1 1 read-only 0 TOF bit was set on the bottom of counting. There was an FTM counter decrement and FTM counter changes from its minimum value (CNTIN register) to its maximum value (MOD register). #0 1 TOF bit was set on the top of counting. There was an FTM counter increment and FTM counter changes from its maximum value (MOD register) to its minimum value (CNTIN register). #1 SC Status and Control 0x0 32 read-write n 0x0 0x0 CLKS Clock Source Selection 3 2 read-write 00 No clock selected (This in effect disables the FTM counter.) #00 01 System clock #01 10 Fixed frequency clock #10 11 External clock #11 CPWMS Center-aligned PWM Select 5 1 read-write 0 FTM counter operates in up counting mode. #0 1 FTM counter operates in up-down counting mode. #1 PS Prescale Factor Selection 0 3 read-write 000 Divide by 1 #000 001 Divide by 2 #001 010 Divide by 4 #010 011 Divide by 8 #011 100 Divide by 16 #100 101 Divide by 32 #101 110 Divide by 64 #110 111 Divide by 128 #111 RESERVED no description available 8 24 read-only TOF Timer Overflow Flag 7 1 read-only 0 FTM counter has not overflowed. #0 1 FTM counter has overflowed. #1 TOIE Timer Overflow Interrupt Enable 6 1 read-write 0 Disable TOF interrupts. Use software polling. #0 1 Enable TOF interrupts. An interrupt is generated when TOF equals one. #1 STATUS Capture and Compare Status 0x50 32 read-only n 0x0 0x0 CH0F Channel 0 Flag 0 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH1F Channel 1 Flag 1 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH2F Channel 2 Flag 2 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH3F Channel 3 Flag 3 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH4F Channel 4 Flag 4 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH5F Channel 5 Flag 5 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH6F Channel 6 Flag 6 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 CH7F Channel 7 Flag 7 1 read-only 0 No channel event has occurred. #0 1 A channel event has occurred. #1 RESERVED no description available 8 24 read-only SWOCTRL FTM Software Output Control 0x94 32 read-write n 0x0 0x0 CH0OC Channel 0 Software Output Control Enable 0 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH0OCV Channel 0 Software Output Control Value 8 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH1OC Channel 1 Software Output Control Enable 1 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH1OCV Channel 1 Software Output Control Value 9 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH2OC Channel 2 Software Output Control Enable 2 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH2OCV Channel 2 Software Output Control Value 10 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH3OC Channel 3 Software Output Control Enable 3 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH3OCV Channel 3 Software Output Control Value 11 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH4OC Channel 4 Software Output Control Enable 4 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH4OCV Channel 4 Software Output Control Value 12 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH5OC Channel 5 Software Output Control Enable 5 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH5OCV Channel 5 Software Output Control Value 13 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH6OC Channel 6 Software Output Control Enable 6 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH6OCV Channel 6 Software Output Control Value 14 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 CH7OC Channel 7 Software Output Control Enable 7 1 read-write 0 The channel output is not affected by software output control. #0 1 The channel output is affected by software output control. #1 CH7OCV Channel 7 Software Output Control Value 15 1 read-write 0 The software output control forces 0 to the channel output. #0 1 The software output control forces 1 to the channel output. #1 RESERVED no description available 16 16 read-only SYNC Synchronization 0x58 32 read-write n 0x0 0x0 CNTMAX Maximum loading point enable 1 1 read-write 0 The maximum loading point is disabled. #0 1 The maximum loading point is enabled. #1 CNTMIN Minimum loading point enable 0 1 read-write 0 The minimum loading point is disabled. #0 1 The minimum loading point is enabled. #1 REINIT FTM Counter Reinitialization by Synchronization (FTM Counter Synchronization) 2 1 read-write 0 FTM counter continues to count normally. #0 1 FTM counter is updated with its initial value when the selected trigger is detected. #1 RESERVED no description available 8 24 read-only SWSYNC PWM Synchronization Software Trigger 7 1 read-write 0 Software trigger is not selected. #0 1 Software trigger is selected. #1 SYNCHOM Output Mask Synchronization 3 1 read-write 0 OUTMASK register is updated with the value of its buffer in all rising edges of the system clock. #0 1 OUTMASK register is updated with the value of its buffer only by the PWM synchronization. #1 TRIG0 PWM Synchronization Hardware Trigger 0 4 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG1 PWM Synchronization Hardware Trigger 1 5 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 TRIG2 PWM Synchronization Hardware Trigger 2 6 1 read-write 0 Trigger is disabled. #0 1 Trigger is enabled. #1 SYNCONF Synchronization Configuration 0x8C 32 read-write n 0x0 0x0 CNTINC CNTIN register synchronization 2 1 read-write 0 CNTIN register is updated with its buffer value at all rising edges of system clock. #0 1 CNTIN register is updated with its buffer value by the PWM synchronization. #1 HWINVC no description available 19 1 read-write 0 A hardware trigger does not activate the INVCTRL register synchronization. #0 1 A hardware trigger activates the INVCTRL register synchronization. #1 HWOM no description available 18 1 read-write 0 A hardware trigger does not activate the OUTMASK register synchronization. #0 1 A hardware trigger activates the OUTMASK register synchronization. #1 HWRSTCNT no description available 16 1 read-write 0 A hardware trigger does not activate the FTM counter synchronization. #0 1 A hardware trigger activates the FTM counter synchronization. #1 HWSOC no description available 20 1 read-write 0 A hardware trigger does not activate the SWOCTRL register synchronization. #0 1 A hardware trigger activates the SWOCTRL register synchronization. #1 HWTRIGMODE Hardware Trigger Mode 0 1 read-write 0 FTM clears the TRIGj bit when the hardware trigger j is detected. #0 1 FTM does not clear the TRIGj bit when the hardware trigger j is detected. #1 HWWRBUF no description available 17 1 read-write 0 A hardware trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 A hardware trigger activates MOD, CNTIN, and CV registers synchronization. #1 INVC INVCTRL register synchronization 4 1 read-write 0 INVCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 INVCTRL register is updated with its buffer value by the PWM synchronization. #1 RESERVED no description available 1 1 read-only RESERVED no description available 3 1 read-only RESERVED no description available 6 1 read-only RESERVED no description available 13 3 read-only RESERVED no description available 21 11 read-only SWINVC no description available 11 1 read-write 0 The software trigger does not activate the INVCTRL register synchronization. #0 1 The software trigger activates the INVCTRL register synchronization. #1 SWOC SWOCTRL register synchronization 5 1 read-write 0 SWOCTRL register is updated with its buffer value at all rising edges of system clock. #0 1 SWOCTRL register is updated with its buffer value by the PWM synchronization. #1 SWOM no description available 10 1 read-write 0 The software trigger does not activate the OUTMASK register synchronization. #0 1 The software trigger activates the OUTMASK register synchronization. #1 SWRSTCNT no description available 8 1 read-write 0 The software trigger does not activate the FTM counter synchronization. #0 1 The software trigger activates the FTM counter synchronization. #1 SWSOC no description available 12 1 read-write 0 The software trigger does not activate the SWOCTRL register synchronization. #0 1 The software trigger activates the SWOCTRL register synchronization. #1 SWWRBUF no description available 9 1 read-write 0 The software trigger does not activate MOD, CNTIN, and CV registers synchronization. #0 1 The software trigger activates MOD, CNTIN, and CV registers synchronization. #1 SYNCMODE Synchronization Mode 7 1 read-write 0 Legacy PWM synchronization is selected. #0 1 Enhanced PWM synchronization is selected. #1 I2C0 Inter-Integrated Circuit I2C 0x0 0x0 0xC registers n I2C0 24 INT_I2C0 40 A1 I2C Address Register 1 0x0 8 read-write n 0x0 0x0 AD Address 1 7 read-write RESERVED no description available 0 1 read-only A2 I2C Address Register 2 0x9 8 read-write n 0x0 0x0 RESERVED no description available 0 1 read-only SAD SMBus address 1 7 read-write C1 I2C Control Register 1 0x2 8 read-write n 0x0 0x0 DMAEN DMA enable 0 1 read-write 0 All DMA signalling disabled. #0 1 DMA transfer is enabled and the following conditions trigger the DMA request: While FACK = 0, a data byte is received, either address or data is transmitted. (ACK/NACK automatic) While FACK = 0, the first byte received matches the A1 register or is general call address. If any address matching occurs, IAAS and TCF are set. If the direction of transfer is known from master to slave, then it is not required to check the SRW. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted. #1 IICEN I2C enable 7 1 read-write 0 Disabled #0 1 Enabled #1 IICIE I2C interrupt enable 6 1 read-write 0 Disabled #0 1 Enabled #1 MST Master mode select 5 1 read-write 0 Slave mode #0 1 Master mode #1 RSTA Repeat START 2 1 write-only TX Transmit mode select 4 1 read-write 0 Receive #0 1 Transmit #1 TXAK Transmit acknowledge enable 3 1 read-write 0 An acknowledge signal is sent to the bus on the following (if FACK is cleared) or current (if FACK is set) receiving byte. #0 1 No acknowledge signal is sent to the bus on the following (if FACK is cleared) or current (if FACK is set) receiving data byte.SCL is held low until TXAK is written. #1 WUEN Wakeup enable 1 1 read-write 0 Normal operation. No interrupt generated when address matching in low power mode. #0 1 Enables the wakeup function in low power mode. #1 C2 I2C Control Register 2 0x5 8 read-write n 0x0 0x0 AD Slave address 0 3 read-write ADEXT Address extension 6 1 read-write 0 7-bit address scheme #0 1 10-bit address scheme #1 GCAEN General call address enable 7 1 read-write 0 Disabled #0 1 Enabled #1 HDRS High drive select 5 1 read-write 0 Normal drive mode #0 1 High drive mode #1 RMEN Range address matching enable 3 1 read-write 0 Range mode disabled. No address match occurs for an address within the range of values of the A1 and RA registers. #0 1 Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers. #1 SBRC Slave baud rate control 4 1 read-write 0 The slave baud rate follows the master baud rate and clock stretching may occur #0 1 Slave baud rate is independent of the master baud rate #1 D I2C Data I/O register 0x4 8 read-write n 0x0 0x0 DATA Data 0 8 read-write F I2C Frequency Divider register 0x1 8 read-write n 0x0 0x0 ICR Clock rate 0 6 read-write MULT no description available 6 2 read-write 00 mul = 1 #00 01 mul = 2 #01 10 mul = 4 #10 11 Reserved #11 FLT I2C Programmable Input Glitch Filter register 0x6 8 read-write n 0x0 0x0 FLT I2C programmable filter factor 0 5 read-write 0 No filter/bypass #0 RESERVED no description available 5 2 read-only RESERVED no description available 7 1 read-only RA I2C Range Address register 0x7 8 read-write n 0x0 0x0 RAD Range slave address 1 7 read-write RESERVED no description available 0 1 read-only S I2C Status Register 0x3 8 read-write n 0x0 0x0 ARBL Arbitration lost 4 1 read-write 0 Standard bus operation. #0 1 Loss of arbitration. #1 BUSY Bus busy 5 1 read-only 0 Bus is idle #0 1 Bus is busy #1 IAAS Addressed as a slave 6 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 IICIF Interrupt flag 1 1 read-write 0 No interrupt pending #0 1 Interrupt pending #1 RAM Range address match 3 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 RXAK Receive acknowledge 0 1 read-only 0 Acknowledge signal was received after the completion of one byte of data transmission on the bus #0 1 No acknowledge signal detected #1 SRW Slave read/write 2 1 read-only 0 Slave receive, master writing to slave #0 1 Slave transmit, master reading from slave #1 TCF Transfer complete flag 7 1 read-only 0 Transfer in progress #0 1 Transfer complete #1 SLTH I2C SCL Low Timeout Register High 0xA 8 read-write n 0x0 0x0 SSLT no description available 0 8 read-write SLTL I2C SCL Low Timeout Register Low 0xB 8 read-write n 0x0 0x0 SSLT no description available 0 8 read-write SMB I2C SMBus Control and Status register 0x8 8 read-write n 0x0 0x0 ALERTEN SMBus alert response address enable 6 1 read-write 0 SMBus alert response address matching is disabled #0 1 SMBus alert response address matching is enabled #1 FACK Fast NACK/ACK enable 7 1 read-write 0 An ACK or NACK is sent on the following receiving data byte #0 1 Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK. #1 SHTF1 SCL high timeout flag 1 2 1 read-only 0 No SCL high and SDA high timeout occurs #0 1 SCL high and SDA high timeout occurs #1 SHTF2 SCL high timeout flag 2 1 1 read-write 0 No SCL high and SDA low timeout occurs #0 1 SCL high and SDA low timeout occurs #1 SHTF2IE SHTF2 interrupt enable 0 1 read-write 0 SHTF2 interrupt is disabled #0 1 SHTF2 interrupt is enabled #1 SIICAEN Second I2C address enable 5 1 read-write 0 I2C address register 2 matching is disabled #0 1 I2C address register 2 matching is enabled #1 SLTF SCL low timeout flag 3 1 read-write 0 No low timeout occurs #0 1 Low timeout occurs #1 TCKSEL Timeout counter clock select 4 1 read-write 0 Timeout counter counts at the frequency of the bus clock / 64 #0 1 Timeout counter counts at the frequency of the bus clock #1 I2C1 Inter-Integrated Circuit I2C 0x0 0x0 0xC registers n I2C1 25 INT_I2C1 41 A1 I2C Address Register 1 0x0 8 read-write n 0x0 0x0 AD Address 1 7 read-write RESERVED no description available 0 1 read-only A2 I2C Address Register 2 0x9 8 read-write n 0x0 0x0 RESERVED no description available 0 1 read-only SAD SMBus address 1 7 read-write C1 I2C Control Register 1 0x2 8 read-write n 0x0 0x0 DMAEN DMA enable 0 1 read-write 0 All DMA signalling disabled. #0 1 DMA transfer is enabled and the following conditions trigger the DMA request: While FACK = 0, a data byte is received, either address or data is transmitted. (ACK/NACK automatic) While FACK = 0, the first byte received matches the A1 register or is general call address. If any address matching occurs, IAAS and TCF are set. If the direction of transfer is known from master to slave, then it is not required to check the SRW. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted. #1 IICEN I2C enable 7 1 read-write 0 Disabled #0 1 Enabled #1 IICIE I2C interrupt enable 6 1 read-write 0 Disabled #0 1 Enabled #1 MST Master mode select 5 1 read-write 0 Slave mode #0 1 Master mode #1 RSTA Repeat START 2 1 write-only TX Transmit mode select 4 1 read-write 0 Receive #0 1 Transmit #1 TXAK Transmit acknowledge enable 3 1 read-write 0 An acknowledge signal is sent to the bus on the following (if FACK is cleared) or current (if FACK is set) receiving byte. #0 1 No acknowledge signal is sent to the bus on the following (if FACK is cleared) or current (if FACK is set) receiving data byte.SCL is held low until TXAK is written. #1 WUEN Wakeup enable 1 1 read-write 0 Normal operation. No interrupt generated when address matching in low power mode. #0 1 Enables the wakeup function in low power mode. #1 C2 I2C Control Register 2 0x5 8 read-write n 0x0 0x0 AD Slave address 0 3 read-write ADEXT Address extension 6 1 read-write 0 7-bit address scheme #0 1 10-bit address scheme #1 GCAEN General call address enable 7 1 read-write 0 Disabled #0 1 Enabled #1 HDRS High drive select 5 1 read-write 0 Normal drive mode #0 1 High drive mode #1 RMEN Range address matching enable 3 1 read-write 0 Range mode disabled. No address match occurs for an address within the range of values of the A1 and RA registers. #0 1 Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers. #1 SBRC Slave baud rate control 4 1 read-write 0 The slave baud rate follows the master baud rate and clock stretching may occur #0 1 Slave baud rate is independent of the master baud rate #1 D I2C Data I/O register 0x4 8 read-write n 0x0 0x0 DATA Data 0 8 read-write F I2C Frequency Divider register 0x1 8 read-write n 0x0 0x0 ICR Clock rate 0 6 read-write MULT no description available 6 2 read-write 00 mul = 1 #00 01 mul = 2 #01 10 mul = 4 #10 11 Reserved #11 FLT I2C Programmable Input Glitch Filter register 0x6 8 read-write n 0x0 0x0 FLT I2C programmable filter factor 0 5 read-write 0 No filter/bypass #0 RESERVED no description available 5 2 read-only RESERVED no description available 7 1 read-only RA I2C Range Address register 0x7 8 read-write n 0x0 0x0 RAD Range slave address 1 7 read-write RESERVED no description available 0 1 read-only S I2C Status Register 0x3 8 read-write n 0x0 0x0 ARBL Arbitration lost 4 1 read-write 0 Standard bus operation. #0 1 Loss of arbitration. #1 BUSY Bus busy 5 1 read-only 0 Bus is idle #0 1 Bus is busy #1 IAAS Addressed as a slave 6 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 IICIF Interrupt flag 1 1 read-write 0 No interrupt pending #0 1 Interrupt pending #1 RAM Range address match 3 1 read-write 0 Not addressed #0 1 Addressed as a slave #1 RXAK Receive acknowledge 0 1 read-only 0 Acknowledge signal was received after the completion of one byte of data transmission on the bus #0 1 No acknowledge signal detected #1 SRW Slave read/write 2 1 read-only 0 Slave receive, master writing to slave #0 1 Slave transmit, master reading from slave #1 TCF Transfer complete flag 7 1 read-only 0 Transfer in progress #0 1 Transfer complete #1 SLTH I2C SCL Low Timeout Register High 0xA 8 read-write n 0x0 0x0 SSLT no description available 0 8 read-write SLTL I2C SCL Low Timeout Register Low 0xB 8 read-write n 0x0 0x0 SSLT no description available 0 8 read-write SMB I2C SMBus Control and Status register 0x8 8 read-write n 0x0 0x0 ALERTEN SMBus alert response address enable 6 1 read-write 0 SMBus alert response address matching is disabled #0 1 SMBus alert response address matching is enabled #1 FACK Fast NACK/ACK enable 7 1 read-write 0 An ACK or NACK is sent on the following receiving data byte #0 1 Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK. #1 SHTF1 SCL high timeout flag 1 2 1 read-only 0 No SCL high and SDA high timeout occurs #0 1 SCL high and SDA high timeout occurs #1 SHTF2 SCL high timeout flag 2 1 1 read-write 0 No SCL high and SDA low timeout occurs #0 1 SCL high and SDA low timeout occurs #1 SHTF2IE SHTF2 interrupt enable 0 1 read-write 0 SHTF2 interrupt is disabled #0 1 SHTF2 interrupt is enabled #1 SIICAEN Second I2C address enable 5 1 read-write 0 I2C address register 2 matching is disabled #0 1 I2C address register 2 matching is enabled #1 SLTF SCL low timeout flag 3 1 read-write 0 No low timeout occurs #0 1 Low timeout occurs #1 TCKSEL Timeout counter clock select 4 1 read-write 0 Timeout counter counts at the frequency of the bus clock / 64 #0 1 Timeout counter counts at the frequency of the bus clock #1 I2S0 Inter-IC Sound / Synchronous Audio Interface I2S 0x0 0x0 0x108 registers n I2S0_Tx 35 I2S0_Rx 36 INT_I2S0_Tx 51 INT_I2S0_Rx 52 MCR SAI MCLK Control Register 0x100 32 read-write n 0x0 0x0 DUF Divider Update Flag 31 1 read-only 0 MCLK Divider ratio is not being updated currently. #0 1 MCLK Divider ratio is updating on-the-fly. Furthur updates to the MCLK Divider ratio are blocked while this flag remains set. #1 MICS MCLK Input Clock Select 24 2 read-write 00 MCLK Divider input clock 0 selected. #00 01 MCLK Divider input clock 1 selected. #01 10 MCLK Divider input clock 2 selected. #10 11 MCLK Divider input clock 3 selected. #11 MOE MCLK Output Enable 30 1 read-write 0 SAI_MCLK pin is configured as an input that bypasses the MCLK Divider. #0 1 SAI_MCLK pin is configured as an output from the MCLK Divider and the MCLK Divider is enabled. #1 RESERVED no description available 0 24 read-only RESERVED no description available 26 4 read-only MDR MCLK Divide Register 0x104 32 read-write n 0x0 0x0 DIVIDE MCLK Divide 0 12 read-write FRACT MCLK Fraction 12 8 read-write RESERVED no description available 20 12 read-only RCR1 SAI Receive Configuration 1 Register 0x84 32 read-write n 0x0 0x0 RESERVED no description available 3 29 read-only RFW Receive FIFO watermark 0 3 read-write RCR2 SAI Receive Configuration 2 Register 0x88 32 read-write n 0x0 0x0 BCD Bit clock direction 24 1 read-write 0 Bit clock is generated externally (slave mode). #0 1 Bit clock is generated internally (master mode). #1 BCI Bit Clock Input 28 1 read-write 0 No effect. #0 1 Internal logic is clocked as if bit clock was externally generated. #1 BCP Bit clock polarity 25 1 read-write 0 Bit Clock is active high (drive outputs on rising edge and sample inputs on falling edge). #0 1 Bit Clock is active low (drive outputs on falling edge and sample inputs on rising edge). #1 BCS Bit Clock Swap 29 1 read-write 0 Use the normal bit clock source. #0 1 Swap the bit clock source. #1 DIV Bit clock divide 0 8 read-write MSEL MCLK Select 26 2 read-write 00 Bus Clock selected. #00 01 Master Clock 1 selected. #01 10 Master Clock 2 selected. #10 11 Master Clock 3 selected. #11 RESERVED no description available 8 16 read-only SYNC Synchronous Mode 30 2 read-write 00 Asynchronous mode. #00 01 Synchronous with transmitter. #01 10 Synchronous with another SAI receiver. #10 11 Synchronous with another SAI transmitter. #11 RCR3 SAI Receive Configuration 3 Register 0x8C 32 read-write n 0x0 0x0 RCE Receive channel enable 16 2 read-write RESERVED no description available 5 11 read-only RESERVED no description available 18 14 read-only WDFL Word flag configuration 0 5 read-write RCR4 SAI Receive Configuration 4 Register 0x90 32 read-write n 0x0 0x0 FRSZ Frame size 16 5 read-write FSD Frame sync direction 0 1 read-write 0 Frame Sync is generated externally (slave mode). #0 1 Frame Sync is generated internally (master mode). #1 FSE Frame sync early 3 1 read-write 0 Frame sync asserts with the first bit of the frame. #0 1 Frame sync asserts one bit before the first bit of the frame. #1 FSP Frame sync polarity 1 1 read-write 0 Frame sync is active high. #0 1 Frame sync is active low. #1 MF MSB first 4 1 read-write 0 LBS is transmitted/received first. #0 1 MBS is transmitted/received first. #1 RESERVED no description available 2 1 read-only RESERVED no description available 5 3 read-only RESERVED no description available 13 3 read-only RESERVED no description available 21 11 read-only SYWD Sync width 8 5 read-write RCR5 SAI Receive Configuration 5 Register 0x94 32 read-write n 0x0 0x0 FBT First bit shifted 8 5 read-write RESERVED no description available 0 8 read-only RESERVED no description available 13 3 read-only RESERVED no description available 21 3 read-only RESERVED no description available 29 3 read-only W0W Word 0 width 16 5 read-write WNW Word N width 24 5 read-write RCSR SAI Receive Control Register 0x80 32 read-write n 0x0 0x0 BCE Bit Clock enable 28 1 read-write 0 Receive bit clock is disabled #0 1 Receive bit clock is enabled #1 DBGE Debug enable 29 1 read-write 0 Receiver is disabled in debug mode, after completing the current frame. #0 1 Receiver is enabled in debug mode. #1 FEF FIFO error flag 18 1 read-write 0 Receive overflow not detected. #0 1 Receive overflow detected. #1 FEIE FIFO error interrupt enable 10 1 read-write 0 Disables the interrupt, #0 1 Enables the interrupt. #1 FR FIFO reset 25 1 write-only 0 No effect. #0 1 FIFO reset. #1 FRDE FIFO request DMA enable 0 1 read-write 0 Disables the DMA request. #0 1 Enables the DMA request. #1 FRF FIFO request flag 16 1 read-only 0 Receive FIFO watermark not reached. #0 1 Receive FIFO watermark has been reached. #1 FRIE FIFO request interrupt enable 8 1 read-write 0 Disables the interrupt. #0 1 Enables the interrupt. #1 FWDE FIFO warning DMA enable 1 1 read-write 0 Disables the DMA request. #0 1 Enables the DMA request. #1 FWF FIFO warning flag 17 1 read-only 0 No enabled receive FIFO is full. #0 1 Enabled receive FIFO is full. #1 FWIE FIFO warning interrupt enable 9 1 read-write 0 Disables the interrupt. #0 1 Enables the interrupt. #1 RE Receiver enable 31 1 read-write 0 Receiver is disabled. #0 1 Receiver is enabled, or receiver has been disabled and not end of frame. #1 RESERVED no description available 2 3 read-only RESERVED no description available 5 3 read-only RESERVED no description available 13 3 read-only RESERVED no description available 21 3 read-only RESERVED no description available 26 2 read-only SEF Sync error flag 19 1 read-write 0 Sync error not detected. #0 1 Frame sync error detected. #1 SEIE Sync error interrupt enable 11 1 read-write 0 Disables interrupt. #0 1 Enables interrupt. #1 SR Software reset 24 1 read-write 0 No effect. #0 1 Software reset. #1 STOPE Stop enable 30 1 read-write 0 Receiver disabled in stop mode. #0 1 Receiver enabled in stop mode. #1 WSF Word start flag 20 1 read-write 0 Start of word not detected. #0 1 Start of word detected. #1 WSIE Word start interrupt enable 12 1 read-write 0 Disables interrupt. #0 1 Enables interrupt. #1 RDR0 SAI Receive Data Register 0x140 32 read-only n 0x0 0x0 RDR Receive data register 0 32 read-only RDR1 SAI Receive Data Register 0x1E4 32 read-only n 0x0 0x0 RDR Receive data register 0 32 read-only RFR0 SAI Receive FIFO Register 0x180 32 read-only n 0x0 0x0 RESERVED no description available 4 12 read-only RESERVED no description available 20 12 read-only RFP Read FIFO pointer 0 4 read-only WFP Write FIFO pointer 16 4 read-only RFR1 SAI Receive FIFO Register 0x244 32 read-only n 0x0 0x0 RESERVED no description available 4 12 read-only RESERVED no description available 20 12 read-only RFP Read FIFO pointer 0 4 read-only WFP Write FIFO pointer 16 4 read-only RMR SAI Receive Mask Register 0xE0 32 read-write n 0x0 0x0 RWM Receive word mask 0 32 read-write 0 Word N is enabled. #0 1 Word N is masked. #1 TCR1 SAI Transmit Configuration 1 Register 0x4 32 read-write n 0x0 0x0 RESERVED no description available 3 29 read-only TFW Transmit FIFO watermark 0 3 read-write TCR2 SAI Transmit Configuration 2 Register 0x8 32 read-write n 0x0 0x0 BCD Bit clock direction 24 1 read-write 0 Bit clock is generated externally (slave mode). #0 1 Bit clock is generated internally (master mode). #1 BCI Bit Clock Input 28 1 read-write 0 No effect. #0 1 Internal logic is clocked by external bit clock. #1 BCP Bit clock polarity 25 1 read-write 0 Bit Clock is active high (drive outputs on rising edge and sample inputs on falling edge). #0 1 Bit Clock is active low (drive outputs on falling edge and sample inputs on rising edge). #1 BCS Bit Clock Swap 29 1 read-write 0 Use the normal bit clock source. #0 1 Swap the bit clock source. #1 DIV Bit clock divide 0 8 read-write MSEL MCLK Select 26 2 read-write 00 Bus Clock selected. #00 01 Master Clock 1 selected. #01 10 Master Clock 2 selected. #10 11 Master Clock 3 selected. #11 RESERVED no description available 8 16 read-only SYNC Synchronous Mode 30 2 read-write 00 Asynchronous mode. #00 01 Synchronous with receiver. #01 10 Synchronous with another SAI transmitter. #10 11 Synchronous with another SAI receiver. #11 TCR3 SAI Transmit Configuration 3 Register 0xC 32 read-write n 0x0 0x0 RESERVED no description available 5 11 read-only RESERVED no description available 18 14 read-only TCE Transmit channel enable 16 2 read-write WDFL Word flag configuration 0 5 read-write TCR4 SAI Transmit Configuration 4 Register 0x10 32 read-write n 0x0 0x0 FRSZ Frame size 16 5 read-write FSD Frame sync direction 0 1 read-write 0 Frame Sync is generated externally (slave mode). #0 1 Frame Sync is generated internally (master mode). #1 FSE Frame sync early 3 1 read-write 0 Frame sync asserts with the first bit of the frame. #0 1 Frame sync asserts one bit before the first bit of the frame. #1 FSP Frame sync polarity 1 1 read-write 0 Frame sync is active high. #0 1 Frame sync is active low. #1 MF MSB first 4 1 read-write 0 LBS is transmitted/received first. #0 1 MBS is transmitted/received first. #1 RESERVED no description available 2 1 read-only RESERVED no description available 5 3 read-only RESERVED no description available 13 3 read-only RESERVED no description available 21 11 read-only SYWD Sync width 8 5 read-write TCR5 SAI Transmit Configuration 5 Register 0x14 32 read-write n 0x0 0x0 FBT First bit shifted 8 5 read-write RESERVED no description available 0 8 read-only RESERVED no description available 13 3 read-only RESERVED no description available 21 3 read-only RESERVED no description available 29 3 read-only W0W Word 0 width 16 5 read-write WNW Word N width 24 5 read-write TCSR SAI Transmit Control Register 0x0 32 read-write n 0x0 0x0 BCE Bit Clock Enable 28 1 read-write 0 Transmit bit clock is disabled #0 1 Transmit bit clock is enabled #1 DBGE Debug enable 29 1 read-write 0 Transmitter is disabled in debug mode, after completing the current frame. #0 1 Transmitter is enabled in debug mode. #1 FEF FIFO error flag 18 1 read-write 0 Transmit underrun not detected. #0 1 Transmit underrun detected. #1 FEIE FIFO error interrupt enable 10 1 read-write 0 Disables the interrupt, #0 1 Enables the interrupt. #1 FR FIFO reset 25 1 write-only 0 No effect. #0 1 FIFO reset. #1 FRDE FIFO request DMA enable 0 1 read-write 0 Disables the DMA request. #0 1 Enables the DMA request. #1 FRF FIFO request flag 16 1 read-only 0 Transmit FIFO watermark not reached. #0 1 Transmit FIFO watermark has been reached. #1 FRIE FIFO request interrupt enable 8 1 read-write 0 Disables the interrupt. #0 1 Enables the interrupt. #1 FWDE FIFO warning DMA enable 1 1 read-write 0 Disables the DMA request. #0 1 Enables the DMA request. #1 FWF FIFO warning flag 17 1 read-only 0 No enabled transmit FIFO is empty. #0 1 Enabled transmit FIFO is empty. #1 FWIE FIFO warning interrupt enable 9 1 read-write 0 Disables the interrupt. #0 1 Enables the interrupt. #1 RESERVED no description available 2 3 read-only RESERVED no description available 5 3 read-only RESERVED no description available 13 3 read-only RESERVED no description available 21 3 read-only RESERVED no description available 26 2 read-only SEF Sync error flag 19 1 read-write 0 Sync error not detected. #0 1 Frame sync error detected. #1 SEIE Sync error interrupt enable 11 1 read-write 0 Disables interrupt. #0 1 Enables interrupt. #1 SR Software reset 24 1 read-write 0 No effect. #0 1 Software reset. #1 STOPE Stop enable 30 1 read-write 0 Transmitter disabled in stop mode. #0 1 Transmitter enabled in stop mode. #1 TE Transmitter enable 31 1 read-write 0 Transmitter is disabled. #0 1 Transmitter is enabled, or transmitter has been disabled and not end of frame. #1 WSF Word start flag 20 1 read-write 0 Start of word not detected. #0 1 Start of word detected. #1 WSIE Word start interrupt enable 12 1 read-write 0 Disables interrupt. #0 1 Enables interrupt. #1 TDR0 SAI Transmit Data Register 0x40 32 write-only n 0x0 0x0 TDR Transmit data register 0 32 write-only TDR1 SAI Transmit Data Register 0x64 32 write-only n 0x0 0x0 TDR Transmit data register 0 32 write-only TFR0 SAI Transmit FIFO Register 0x80 32 read-only n 0x0 0x0 RESERVED no description available 4 12 read-only RESERVED no description available 20 12 read-only RFP Read FIFO pointer 0 4 read-only WFP Write FIFO pointer 16 4 read-only TFR1 SAI Transmit FIFO Register 0xC4 32 read-only n 0x0 0x0 RESERVED no description available 4 12 read-only RESERVED no description available 20 12 read-only RFP Read FIFO pointer 0 4 read-only WFP Write FIFO pointer 16 4 read-only TMR SAI Transmit Mask Register 0x60 32 read-write n 0x0 0x0 TWM Transmit word mask 0 32 read-write 0 Word N is enabled. #0 1 Word N is masked. The transmit data pins are tri-stated when masked. #1 I2S1 Inter-IC Sound / Synchronous Audio Interface I2S 0x0 0x0 0x108 registers n I2S1_Tx 104 I2S1_Rx 105 INT_I2S1_Tx 120 INT_I2S1_Rx 121 MCR SAI MCLK Control Register 0x100 32 read-write n 0x0 0x0 DUF Divider Update Flag 31 1 read-only 0 MCLK Divider ratio is not being updated currently. #0 1 MCLK Divider ratio is updating on-the-fly. Furthur updates to the MCLK Divider ratio are blocked while this flag remains set. #1 MICS MCLK Input Clock Select 24 2 read-write 00 MCLK Divider input clock 0 selected. #00 01 MCLK Divider input clock 1 selected. #01 10 MCLK Divider input clock 2 selected. #10 11 MCLK Divider input clock 3 selected. #11 MOE MCLK Output Enable 30 1 read-write 0 SAI_MCLK pin is configured as an input that bypasses the MCLK Divider. #0 1 SAI_MCLK pin is configured as an output from the MCLK Divider and the MCLK Divider is enabled. #1 RESERVED no description available 0 24 read-only RESERVED no description available 26 4 read-only MDR MCLK Divide Register 0x104 32 read-write n 0x0 0x0 DIVIDE MCLK Divide 0 12 read-write FRACT MCLK Fraction 12 8 read-write RESERVED no description available 20 12 read-only RCR1 SAI Receive Configuration 1 Register 0x84 32 read-write n 0x0 0x0 RESERVED no description available 3 29 read-only RFW Receive FIFO watermark 0 3 read-write RCR2 SAI Receive Configuration 2 Register 0x88 32 read-write n 0x0 0x0 BCD Bit clock direction 24 1 read-write 0 Bit clock is generated externally (slave mode). #0 1 Bit clock is generated internally (master mode). #1 BCI Bit Clock Input 28 1 read-write 0 No effect. #0 1 Internal logic is clocked as if bit clock was externally generated. #1 BCP Bit clock polarity 25 1 read-write 0 Bit Clock is active high (drive outputs on rising edge and sample inputs on falling edge). #0 1 Bit Clock is active low (drive outputs on falling edge and sample inputs on rising edge). #1 BCS Bit Clock Swap 29 1 read-write 0 Use the normal bit clock source. #0 1 Swap the bit clock source. #1 DIV Bit clock divide 0 8 read-write MSEL MCLK Select 26 2 read-write 00 Bus Clock selected. #00 01 Master Clock 1 selected. #01 10 Master Clock 2 selected. #10 11 Master Clock 3 selected. #11 RESERVED no description available 8 16 read-only SYNC Synchronous Mode 30 2 read-write 00 Asynchronous mode. #00 01 Synchronous with transmitter. #01 10 Synchronous with another SAI receiver. #10 11 Synchronous with another SAI transmitter. #11 RCR3 SAI Receive Configuration 3 Register 0x8C 32 read-write n 0x0 0x0 RCE Receive channel enable 16 2 read-write RESERVED no description available 5 11 read-only RESERVED no description available 18 14 read-only WDFL Word flag configuration 0 5 read-write RCR4 SAI Receive Configuration 4 Register 0x90 32 read-write n 0x0 0x0 FRSZ Frame size 16 5 read-write FSD Frame sync direction 0 1 read-write 0 Frame Sync is generated externally (slave mode). #0 1 Frame Sync is generated internally (master mode). #1 FSE Frame sync early 3 1 read-write 0 Frame sync asserts with the first bit of the frame. #0 1 Frame sync asserts one bit before the first bit of the frame. #1 FSP Frame sync polarity 1 1 read-write 0 Frame sync is active high. #0 1 Frame sync is active low. #1 MF MSB first 4 1 read-write 0 LBS is transmitted/received first. #0 1 MBS is transmitted/received first. #1 RESERVED no description available 2 1 read-only RESERVED no description available 5 3 read-only RESERVED no description available 13 3 read-only RESERVED no description available 21 11 read-only SYWD Sync width 8 5 read-write RCR5 SAI Receive Configuration 5 Register 0x94 32 read-write n 0x0 0x0 FBT First bit shifted 8 5 read-write RESERVED no description available 0 8 read-only RESERVED no description available 13 3 read-only RESERVED no description available 21 3 read-only RESERVED no description available 29 3 read-only W0W Word 0 width 16 5 read-write WNW Word N width 24 5 read-write RCSR SAI Receive Control Register 0x80 32 read-write n 0x0 0x0 BCE Bit Clock enable 28 1 read-write 0 Receive bit clock is disabled #0 1 Receive bit clock is enabled #1 DBGE Debug enable 29 1 read-write 0 Receiver is disabled in debug mode, after completing the current frame. #0 1 Receiver is enabled in debug mode. #1 FEF FIFO error flag 18 1 read-write 0 Receive overflow not detected. #0 1 Receive overflow detected. #1 FEIE FIFO error interrupt enable 10 1 read-write 0 Disables the interrupt, #0 1 Enables the interrupt. #1 FR FIFO reset 25 1 write-only 0 No effect. #0 1 FIFO reset. #1 FRDE FIFO request DMA enable 0 1 read-write 0 Disables the DMA request. #0 1 Enables the DMA request. #1 FRF FIFO request flag 16 1 read-only 0 Receive FIFO watermark not reached. #0 1 Receive FIFO watermark has been reached. #1 FRIE FIFO request interrupt enable 8 1 read-write 0 Disables the interrupt. #0 1 Enables the interrupt. #1 FWDE FIFO warning DMA enable 1 1 read-write 0 Disables the DMA request. #0 1 Enables the DMA request. #1 FWF FIFO warning flag 17 1 read-only 0 No enabled receive FIFO is full. #0 1 Enabled receive FIFO is full. #1 FWIE FIFO warning interrupt enable 9 1 read-write 0 Disables the interrupt. #0 1 Enables the interrupt. #1 RE Receiver enable 31 1 read-write 0 Receiver is disabled. #0 1 Receiver is enabled, or receiver has been disabled and not end of frame. #1 RESERVED no description available 2 3 read-only RESERVED no description available 5 3 read-only RESERVED no description available 13 3 read-only RESERVED no description available 21 3 read-only RESERVED no description available 26 2 read-only SEF Sync error flag 19 1 read-write 0 Sync error not detected. #0 1 Frame sync error detected. #1 SEIE Sync error interrupt enable 11 1 read-write 0 Disables interrupt. #0 1 Enables interrupt. #1 SR Software reset 24 1 read-write 0 No effect. #0 1 Software reset. #1 STOPE Stop enable 30 1 read-write 0 Receiver disabled in stop mode. #0 1 Receiver enabled in stop mode. #1 WSF Word start flag 20 1 read-write 0 Start of word not detected. #0 1 Start of word detected. #1 WSIE Word start interrupt enable 12 1 read-write 0 Disables interrupt. #0 1 Enables interrupt. #1 RDR0 SAI Receive Data Register 0x140 32 read-only n 0x0 0x0 RDR Receive data register 0 32 read-only RDR1 SAI Receive Data Register 0x1E4 32 read-only n 0x0 0x0 RDR Receive data register 0 32 read-only RFR0 SAI Receive FIFO Register 0x180 32 read-only n 0x0 0x0 RESERVED no description available 4 12 read-only RESERVED no description available 20 12 read-only RFP Read FIFO pointer 0 4 read-only WFP Write FIFO pointer 16 4 read-only RFR1 SAI Receive FIFO Register 0x244 32 read-only n 0x0 0x0 RESERVED no description available 4 12 read-only RESERVED no description available 20 12 read-only RFP Read FIFO pointer 0 4 read-only WFP Write FIFO pointer 16 4 read-only RMR SAI Receive Mask Register 0xE0 32 read-write n 0x0 0x0 RWM Receive word mask 0 32 read-write 0 Word N is enabled. #0 1 Word N is masked. #1 TCR1 SAI Transmit Configuration 1 Register 0x4 32 read-write n 0x0 0x0 RESERVED no description available 3 29 read-only TFW Transmit FIFO watermark 0 3 read-write TCR2 SAI Transmit Configuration 2 Register 0x8 32 read-write n 0x0 0x0 BCD Bit clock direction 24 1 read-write 0 Bit clock is generated externally (slave mode). #0 1 Bit clock is generated internally (master mode). #1 BCI Bit Clock Input 28 1 read-write 0 No effect. #0 1 Internal logic is clocked by external bit clock. #1 BCP Bit clock polarity 25 1 read-write 0 Bit Clock is active high (drive outputs on rising edge and sample inputs on falling edge). #0 1 Bit Clock is active low (drive outputs on falling edge and sample inputs on rising edge). #1 BCS Bit Clock Swap 29 1 read-write 0 Use the normal bit clock source. #0 1 Swap the bit clock source. #1 DIV Bit clock divide 0 8 read-write MSEL MCLK Select 26 2 read-write 00 Bus Clock selected. #00 01 Master Clock 1 selected. #01 10 Master Clock 2 selected. #10 11 Master Clock 3 selected. #11 RESERVED no description available 8 16 read-only SYNC Synchronous Mode 30 2 read-write 00 Asynchronous mode. #00 01 Synchronous with receiver. #01 10 Synchronous with another SAI transmitter. #10 11 Synchronous with another SAI receiver. #11 TCR3 SAI Transmit Configuration 3 Register 0xC 32 read-write n 0x0 0x0 RESERVED no description available 5 11 read-only RESERVED no description available 18 14 read-only TCE Transmit channel enable 16 2 read-write WDFL Word flag configuration 0 5 read-write TCR4 SAI Transmit Configuration 4 Register 0x10 32 read-write n 0x0 0x0 FRSZ Frame size 16 5 read-write FSD Frame sync direction 0 1 read-write 0 Frame Sync is generated externally (slave mode). #0 1 Frame Sync is generated internally (master mode). #1 FSE Frame sync early 3 1 read-write 0 Frame sync asserts with the first bit of the frame. #0 1 Frame sync asserts one bit before the first bit of the frame. #1 FSP Frame sync polarity 1 1 read-write 0 Frame sync is active high. #0 1 Frame sync is active low. #1 MF MSB first 4 1 read-write 0 LBS is transmitted/received first. #0 1 MBS is transmitted/received first. #1 RESERVED no description available 2 1 read-only RESERVED no description available 5 3 read-only RESERVED no description available 13 3 read-only RESERVED no description available 21 11 read-only SYWD Sync width 8 5 read-write TCR5 SAI Transmit Configuration 5 Register 0x14 32 read-write n 0x0 0x0 FBT First bit shifted 8 5 read-write RESERVED no description available 0 8 read-only RESERVED no description available 13 3 read-only RESERVED no description available 21 3 read-only RESERVED no description available 29 3 read-only W0W Word 0 width 16 5 read-write WNW Word N width 24 5 read-write TCSR SAI Transmit Control Register 0x0 32 read-write n 0x0 0x0 BCE Bit Clock Enable 28 1 read-write 0 Transmit bit clock is disabled #0 1 Transmit bit clock is enabled #1 DBGE Debug enable 29 1 read-write 0 Transmitter is disabled in debug mode, after completing the current frame. #0 1 Transmitter is enabled in debug mode. #1 FEF FIFO error flag 18 1 read-write 0 Transmit underrun not detected. #0 1 Transmit underrun detected. #1 FEIE FIFO error interrupt enable 10 1 read-write 0 Disables the interrupt, #0 1 Enables the interrupt. #1 FR FIFO reset 25 1 write-only 0 No effect. #0 1 FIFO reset. #1 FRDE FIFO request DMA enable 0 1 read-write 0 Disables the DMA request. #0 1 Enables the DMA request. #1 FRF FIFO request flag 16 1 read-only 0 Transmit FIFO watermark not reached. #0 1 Transmit FIFO watermark has been reached. #1 FRIE FIFO request interrupt enable 8 1 read-write 0 Disables the interrupt. #0 1 Enables the interrupt. #1 FWDE FIFO warning DMA enable 1 1 read-write 0 Disables the DMA request. #0 1 Enables the DMA request. #1 FWF FIFO warning flag 17 1 read-only 0 No enabled transmit FIFO is empty. #0 1 Enabled transmit FIFO is empty. #1 FWIE FIFO warning interrupt enable 9 1 read-write 0 Disables the interrupt. #0 1 Enables the interrupt. #1 RESERVED no description available 2 3 read-only RESERVED no description available 5 3 read-only RESERVED no description available 13 3 read-only RESERVED no description available 21 3 read-only RESERVED no description available 26 2 read-only SEF Sync error flag 19 1 read-write 0 Sync error not detected. #0 1 Frame sync error detected. #1 SEIE Sync error interrupt enable 11 1 read-write 0 Disables interrupt. #0 1 Enables interrupt. #1 SR Software reset 24 1 read-write 0 No effect. #0 1 Software reset. #1 STOPE Stop enable 30 1 read-write 0 Transmitter disabled in stop mode. #0 1 Transmitter enabled in stop mode. #1 TE Transmitter enable 31 1 read-write 0 Transmitter is disabled. #0 1 Transmitter is enabled, or transmitter has been disabled and not end of frame. #1 WSF Word start flag 20 1 read-write 0 Start of word not detected. #0 1 Start of word detected. #1 WSIE Word start interrupt enable 12 1 read-write 0 Disables interrupt. #0 1 Enables interrupt. #1 TDR0 SAI Transmit Data Register 0x40 32 write-only n 0x0 0x0 TDR Transmit data register 0 32 write-only TDR1 SAI Transmit Data Register 0x64 32 write-only n 0x0 0x0 TDR Transmit data register 0 32 write-only TFR0 SAI Transmit FIFO Register 0x80 32 read-only n 0x0 0x0 RESERVED no description available 4 12 read-only RESERVED no description available 20 12 read-only RFP Read FIFO pointer 0 4 read-only WFP Write FIFO pointer 16 4 read-only TFR1 SAI Transmit FIFO Register 0xC4 32 read-only n 0x0 0x0 RESERVED no description available 4 12 read-only RESERVED no description available 20 12 read-only RFP Read FIFO pointer 0 4 read-only WFP Write FIFO pointer 16 4 read-only TMR SAI Transmit Mask Register 0x60 32 read-write n 0x0 0x0 TWM Transmit word mask 0 32 read-write 0 Word N is enabled. #0 1 Word N is masked. The transmit data pins are tri-stated when masked. #1 LLWU Low leakage wakeup unit LLWU 0x0 0x0 0xB registers n LLW 21 INT_LLW 37 F1 LLWU Flag 1 Register 0x5 8 read-write n 0x0 0x0 WUF0 Wakeup Flag for LLWU_P0 0 1 read-write 0 LLWU_P0 input was not a wakeup source #0 1 LLWU_P0 input was a wakeup source #1 WUF1 Wakeup Flag for LLWU_P1 1 1 read-write 0 LLWU_P1 input was not a wakeup source #0 1 LLWU_P1 input was a wakeup source #1 WUF2 Wakeup Flag for LLWU_P2 2 1 read-write 0 LLWU_P2 input was not a wakeup source #0 1 LLWU_P2 input was a wakeup source #1 WUF3 Wakeup Flag for LLWU_P3 3 1 read-write 0 LLWU_P3 input was not a wakeup source #0 1 LLWU_P3 input was a wakeup source #1 WUF4 Wakeup Flag for LLWU_P4 4 1 read-write 0 LLWU_P4 input was not a wakeup source #0 1 LLWU_P4 input was a wakeup source #1 WUF5 Wakeup Flag for LLWU_P5 5 1 read-write 0 LLWU_P5 input was not a wakeup source #0 1 LLWU_P5 input was a wakeup source #1 WUF6 Wakeup Flag for LLWU_P6 6 1 read-write 0 LLWU_P6 input was not a wakeup source #0 1 LLWU_P6 input was a wakeup source #1 WUF7 Wakeup Flag for LLWU_P7 7 1 read-write 0 LLWU_P7 input was not a wakeup source #0 1 LLWU_P7 input was a wakeup source #1 F2 LLWU Flag 2 Register 0x6 8 read-write n 0x0 0x0 WUF10 Wakeup Flag for LLWU_P10 2 1 read-write 0 LLWU_P10 input was not a wakeup source #0 1 LLWU_P10 input was a wakeup source #1 WUF11 Wakeup Flag for LLWU_P11 3 1 read-write 0 LLWU_P11 input was not a wakeup source #0 1 LLWU_P11 input was a wakeup source #1 WUF12 Wakeup Flag for LLWU_P12 4 1 read-write 0 LLWU_P12 input was not a wakeup source #0 1 LLWU_P12 input was a wakeup source #1 WUF13 Wakeup Flag for LLWU_P13 5 1 read-write 0 LLWU_P13 input was not a wakeup source #0 1 LLWU_P13 input was a wakeup source #1 WUF14 Wakeup Flag for LLWU_P14 6 1 read-write 0 LLWU_P14 input was not a wakeup source #0 1 LLWU_P14 input was a wakeup source #1 WUF15 Wakeup Flag for LLWU_P15 7 1 read-write 0 LLWU_P15 input was not a wakeup source #0 1 LLWU_P15 input was a wakeup source #1 WUF8 Wakeup Flag for LLWU_P8 0 1 read-write 0 LLWU_P8 input was not a wakeup source #0 1 LLWU_P8 input was a wakeup source #1 WUF9 Wakeup Flag for LLWU_P9 1 1 read-write 0 LLWU_P9 input was not a wakeup source #0 1 LLWU_P9 input was a wakeup source #1 F3 LLWU Flag 3 Register 0x7 8 read-only n 0x0 0x0 MWUF0 Wakeup flag for module 0 0 1 read-only 0 Module 0 input was not a wakeup source #0 1 Module 0 input was a wakeup source #1 MWUF1 Wakeup flag for module 1 1 1 read-only 0 Module 1 input was not a wakeup source #0 1 Module 1 input was a wakeup source #1 MWUF2 Wakeup flag for module 2 2 1 read-only 0 Module 2 input was not a wakeup source #0 1 Module 2 input was a wakeup source #1 MWUF3 Wakeup flag for module 3 3 1 read-only 0 Module 3 input was not a wakeup source #0 1 Module 3 input was a wakeup source #1 MWUF4 Wakeup flag for module 4 4 1 read-only 0 Module 4 input was not a wakeup source #0 1 Module 4 input was a wakeup source #1 MWUF5 Wakeup flag for module 5 5 1 read-only 0 Module 5 input was not a wakeup source #0 1 Module 5 input was a wakeup source #1 MWUF6 Wakeup flag for module 6 6 1 read-only 0 Module 6 input was not a wakeup source #0 1 Module 6 input was a wakeup source #1 MWUF7 Wakeup flag for module 7 7 1 read-only 0 Module 7 input was not a wakeup source #0 1 Module 7 input was a wakeup source #1 FILT1 LLWU Pin Filter 1 Register 0x8 8 read-write n 0x0 0x0 FILTE Digital Filter on External Pin 5 2 read-write 00 Filter disabled #00 01 Filter posedge detect enabled #01 10 Filter negedge detect enabled #10 11 Filter any edge detect enabled #11 FILTF Filter Detect Flag 7 1 read-write 0 Pin Filter 1 was not a wakeup source #0 1 Pin Filter 1 was a wakeup source #1 FILTSEL Filter pin select 0 4 read-write 0000 Select LLWU_P0 for filter #0000 1111 Select LLWU_P15 for filter #1111 RESERVED no description available 4 1 read-only FILT2 LLWU Pin Filter 2 Register 0x9 8 read-write n 0x0 0x0 FILTE Digital Filter on External Pin 5 2 read-write 00 Filter disabled #00 01 Filter posedge detect enabled #01 10 Filter negedge detect enabled #10 11 Filter any edge detect enabled #11 FILTF Filter Detect Flag 7 1 read-write 0 Pin Filter 2 was not a wakeup source #0 1 Pin Filter 2 was a wakeup source #1 FILTSEL Filter pin select 0 4 read-write 0000 Select LLWU_P0 for filter #0000 1111 Select LLWU_P15 for filter #1111 RESERVED no description available 4 1 read-only ME LLWU Module Enable Register 0x4 8 read-write n 0x0 0x0 WUME0 Wakeup Module Enable for Module 0 0 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME1 Wakeup Module Enable for Module 1 1 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME2 Wakeup Module Enable for Module 2 2 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME3 Wakeup Module Enable for Module 3 3 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME4 Wakeup Module Enable for Module 4 4 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME5 Wakeup Module Enable for Module 5 5 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME6 Wakeup Module Enable for Module 6 6 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 WUME7 Wakeup Module Enable for Module 7 7 1 read-write 0 Internal module flag not used as wakeup source #0 1 Internal module flag used as wakeup source #1 PE1 LLWU Pin Enable 1 Register 0x0 8 read-write n 0x0 0x0 WUPE0 Wakeup Pin Enable for LLWU_P0 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE1 Wakeup Pin Enable for LLWU_P1 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE2 Wakeup Pin Enable for LLWU_P2 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE3 Wakeup Pin Enable for LLWU_P3 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE2 LLWU Pin Enable 2 Register 0x1 8 read-write n 0x0 0x0 WUPE4 Wakeup Pin Enable for LLWU_P4 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE5 Wakeup Pin Enable for LLWU_P5 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE6 Wakeup Pin Enable for LLWU_P6 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE7 Wakeup Pin Enable for LLWU_P7 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE3 LLWU Pin Enable 3 Register 0x2 8 read-write n 0x0 0x0 WUPE10 Wakeup Pin Enable for LLWU_P10 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE11 Wakeup Pin Enable for LLWU_P11 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE8 Wakeup Pin Enable for LLWU_P8 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE9 Wakeup Pin Enable for LLWU_P9 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 PE4 LLWU Pin Enable 4 Register 0x3 8 read-write n 0x0 0x0 WUPE12 Wakeup Pin Enable for LLWU_P12 0 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE13 Wakeup Pin Enable for LLWU_P13 2 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE14 Wakeup Pin Enable for LLWU_P14 4 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 WUPE15 Wakeup Pin Enable for LLWU_P15 6 2 read-write 00 External input pin disabled as wakeup input #00 01 External input pin enabled with rising edge detection #01 10 External input pin enabled with falling edge detection #10 11 External input pin enabled with any change detection #11 RST LLWU Reset Enable Register 0xA 8 read-write n 0x0 0x0 LLRSTE Low Leakage mode RESET enable 1 1 read-write 0 RESET pin not enabled as a leakage mode exit source #0 1 RESET pin enabled as a low leakage mode exit source #1 RESERVED no description available 2 6 read-only RSTFILT Digital Filter on RESET Pin 0 1 read-write 0 Filter not enabled #0 1 Filter enabled #1 LMEM Local Memory Controller LMEM 0x0 0x0 0x824 registers n PCCCR Cache control register 0x0 32 read-write n 0x0 0x0 ENCACHE Cache enable 0 1 read-write 0 Cache disabled #0 1 Cache enabled #1 ENWRBUF Enable Write Buffer 1 1 read-write 0 Write buffer disabled #0 1 Write buffer enabled #1 GO Initiate Cache Command 31 1 read-write 0 Write: no effect. Read: no cache command active. #0 1 Write: initiate command indicated by bits 27-24. Read: cache command active. #1 INVW0 Invalidate Way 0 24 1 read-write 0 No operation #0 1 When setting the GO bit, invalidate all lines in way 0. #1 INVW1 Invalidate Way 1 26 1 read-write 0 No operation #0 1 When setting the GO bit, invalidate all lines in way 1 #1 PUSHW0 Push Way 0 25 1 read-write 0 No operation #0 1 When setting the GO bit, push all modified lines in way 0 #1 PUSHW1 Push Way 1 27 1 read-write 0 No operation #0 1 When setting the GO bit, push all modified lines in way 1 #1 RESERVED no description available 2 22 read-only RESERVED no description available 28 3 read-only PCCCVR Cache read/write value register 0xC 32 read-write n 0x0 0x0 DATA Cache read/write Data 0 32 read-write PCCLCR Cache line control register 0x4 32 read-write n 0x0 0x0 CACHEADDR Cache address 2 10 read-write LACC Line access type 27 1 read-write 0 Read #0 1 Write #1 LADSEL Line Address Select 26 1 read-write 0 Cache address #0 1 Physical address #1 LCIMB Line Command Initial Modified Bit 21 1 read-only LCIVB Line Command Initial Valid Bit 20 1 read-only LCMD Line Command 24 2 read-write 00 Search and read or write #00 01 Invalidate #01 10 Push #10 11 Clear #11 LCWAY Line Command Way 22 1 read-only LGO Initiate Cache Line Command 0 1 read-write 0 Write: no effect. Read: no line command active. #0 1 Write: initiate line command indicated by bits 27-24. Read: line command active. #1 RESERVED no description available 1 1 read-only RESERVED no description available 12 2 read-only RESERVED no description available 15 1 read-only RESERVED no description available 17 3 read-only RESERVED no description available 23 1 read-only RESERVED no description available 28 4 read-only TDSEL Tag/Data Select 16 1 read-write 0 Data #0 1 Tag #1 WSEL Way select 14 1 read-write 0 Way 0 #0 1 Way 1 #1 PCCRMR Cache regions mode register 0x20 32 read-write n 0x0 0x0 R0 Region 0 mode 30 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R1 Region 1 mode 28 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R10 Region 10 mode 10 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R11 Region 11 mode 8 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R12 Region 12 mode 6 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R13 Region 13 mode 4 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R14 Region 14 mode 2 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R15 Region 15 mode 0 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R2 Region 2 mode 26 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R3 Region 3 mode 24 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R4 Region 4 mode 22 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R5 Region 5 mode 20 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R6 Region 6 mode 18 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R7 Region 7 mode 16 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R8 Region 8 mode 14 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R9 Region 9 mode 12 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 PCCSAR Cache search address register 0x8 32 read-write n 0x0 0x0 LGO Initiate Cache Line Command 0 1 read-write 0 Write: no effect. Read: no line command active. #0 1 Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active. #1 PHYADDR Physical Address 2 30 read-write RESERVED no description available 1 1 read-only PSCCR Cache control register 0x800 32 read-write n 0x0 0x0 ENCACHE Cache enable 0 1 read-write 0 Cache disabled #0 1 Cache enabled #1 ENWRBUF Enable Write Buffer 1 1 read-write 0 Write buffer disabled #0 1 Write buffer enabled #1 GO Initiate Cache Command 31 1 read-write 0 Write: no effect. Read: no cache command active. #0 1 Write: initiate command indicated by bits 27-24. Read: cache command active. #1 INVW0 Invalidate Way 0 24 1 read-write 0 No operation #0 1 When setting the GO bit, invalidate all lines in way 0. #1 INVW1 Invalidate Way 1 26 1 read-write 0 No operation #0 1 When setting the GO bit, invalidate all lines in way 1 #1 PUSHW0 Push Way 0 25 1 read-write 0 No operation #0 1 When setting the GO bit, push all modified lines in way 0 #1 PUSHW1 Push Way 1 27 1 read-write 0 No operation #0 1 When setting the GO bit, push all modified lines in way 1 #1 RESERVED no description available 2 22 read-only RESERVED no description available 28 3 read-only PSCCVR Cache read/write value register 0x80C 32 read-write n 0x0 0x0 DATA Cache read/write Data 0 32 read-write PSCLCR Cache line control register 0x804 32 read-write n 0x0 0x0 CACHEADDR Cache address 2 10 read-write LACC Line access type 27 1 read-write 0 Read #0 1 Write #1 LADSEL Line Address Select 26 1 read-write 0 Cache address #0 1 Physical address #1 LCIMB Line Command Initial Modified Bit 21 1 read-only LCIVB Line Command Initial Valid Bit 20 1 read-only LCMD Line Command 24 2 read-write 00 Search and read or write #00 01 Invalidate #01 10 Push #10 11 Clear #11 LCWAY Line Command Way 22 1 read-only LGO Initiate Cache Line Command 0 1 read-write 0 Write: no effect. Read: no line command active. #0 1 Write: initiate line command indicated by bits 27-24. Read: line command active. #1 RESERVED no description available 1 1 read-only RESERVED no description available 12 2 read-only RESERVED no description available 15 1 read-only RESERVED no description available 17 3 read-only RESERVED no description available 23 1 read-only RESERVED no description available 28 4 read-only TDSEL Tag/Data Select 16 1 read-write 0 Data #0 1 Tag #1 WSEL Way select 14 1 read-write 0 Way 0 #0 1 Way 1 #1 PSCRMR Cache regions mode register 0x820 32 read-write n 0x0 0x0 R0 Region 0 mode 30 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R1 Region 1 mode 28 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R10 Region 10 mode 10 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R11 Region 11 mode 8 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R12 Region 12 mode 6 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R13 Region 13 mode 4 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R14 Region 14 mode 2 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R15 Region 15 mode 0 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R2 Region 2 mode 26 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R3 Region 3 mode 24 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R4 Region 4 mode 22 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R5 Region 5 mode 20 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R6 Region 6 mode 18 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R7 Region 7 mode 16 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R8 Region 8 mode 14 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 R9 Region 9 mode 12 2 read-write 00 Non-cacheable #00 01 Non-cacheable #01 10 Write-through #10 11 Write-back #11 PSCSAR Cache search address register 0x808 32 read-write n 0x0 0x0 LGO Initiate Cache Line Command 0 1 read-write 0 Write: no effect. Read: no line command active. #0 1 Write: initiate line command indicated by bits CLCR[27:24]. Read: line command active. #1 PHYADDR Physical Address 2 30 read-write RESERVED no description available 1 1 read-only LPTMR0 Low Power Timer LPTMR0 0x0 0x0 0x10 registers n LPTimer 85 INT_LPTimer 101 CMR Low Power Timer Compare Register 0x8 32 read-write n 0x0 0x0 COMPARE Compare Value 0 16 read-write RESERVED no description available 16 16 read-only CNR Low Power Timer Counter Register 0xC 32 read-only n 0x0 0x0 COUNTER Counter Value 0 16 read-only RESERVED no description available 16 16 read-only CSR Low Power Timer Control Status Register 0x0 32 read-write n 0x0 0x0 RESERVED no description available 8 24 read-only TCF Timer Compare Flag 7 1 read-write 0 The value of CNR is not equal to CMR and increments. #0 1 The value of CNR is equal to CMR and increments. #1 TEN Timer Enable 0 1 read-write 0 LPTMR is disabled and internal logic is reset. #0 1 LPTMR is enabled. #1 TFC Timer Free-Running Counter 2 1 read-write 0 CNR is reset whenever TCF is set. #0 1 CNR is reset on overflow. #1 TIE Timer Interrupt Enable 6 1 read-write 0 Timer interrupt disabled. #0 1 Timer interrupt enabled. #1 TMS Timer Mode Select 1 1 read-write 0 Time Counter mode. #0 1 Pulse Counter mode. #1 TPP Timer Pin Polarity 3 1 read-write 0 Pulse Counter input source is active-high, and the CNR will increment on the rising-edge. #0 1 Pulse Counter input source is active-low, and the CNR will increment on the falling-edge. #1 TPS Timer Pin Select 4 2 read-write 00 Pulse counter input 0 is selected. #00 01 Pulse counter input 1 is selected. #01 10 Pulse counter input 2 is selected. #10 11 Pulse counter input 3 is selected. #11 PSR Low Power Timer Prescale Register 0x4 32 read-write n 0x0 0x0 PBYP Prescaler Bypass 2 1 read-write 0 Prescaler/glitch filter is enabled. #0 1 Prescaler/glitch filter is bypassed. #1 PCS Prescaler Clock Select 0 2 read-write 00 Prescaler/glitch filter clock 0 selected. #00 01 Prescaler/glitch filter clock 1 selected. #01 10 Prescaler/glitch filter clock 2 selected. #10 11 Prescaler/glitch filter clock 3 selected. #11 PRESCALE Prescale Value 3 4 read-write 0000 Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration. #0000 0001 Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges. #0001 0010 Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges. #0010 0011 Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges. #0011 0100 Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges. #0100 0101 Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges. #0101 0110 Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges. #0110 0111 Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges. #0111 1000 Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges. #1000 1001 Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges. #1001 1010 Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges. #1010 1011 Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges. #1011 1100 Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges. #1100 1101 Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges. #1101 1110 Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges. #1110 1111 Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges. #1111 RESERVED no description available 7 25 read-only MCG Multipurpose Clock Generator module MCG 0x0 0x0 0x13 registers n ATCVH MCG Auto Trim Compare Value High Register 0xA 8 read-write n 0x0 0x0 ATCVH ATM Compare Value High 0 8 read-write ATCVL MCG Auto Trim Compare Value Low Register 0xB 8 read-write n 0x0 0x0 ATCVL ATM Compare Value Low 0 8 read-write C1 MCG Control 1 Register 0x0 8 read-write n 0x0 0x0 CLKS Clock Source Select 6 2 read-write 00 Encoding 0 - Output of FLL or PLLCS is selected (depends on PLLS control bit). #00 01 Encoding 1 - Internal reference clock is selected. #01 10 Encoding 2 - External reference clock is selected. #10 11 Encoding 3 - Reserved. #11 FRDIV FLL External Reference Divider 3 3 read-write 000 If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 1; for all other RANGE 0 values, Divide Factor is 32. #000 001 If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 2; for all other RANGE 0 values, Divide Factor is 64. #001 010 If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 4; for all other RANGE 0 values, Divide Factor is 128. #010 011 If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 8; for all other RANGE 0 values, Divide Factor is 256. #011 100 If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 16; for all other RANGE 0 values, Divide Factor is 512. #100 101 If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 32; for all other RANGE 0 values, Divide Factor is 1024. #101 110 If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 64; for all other RANGE 0 values, Divide Factor is Reserved . #110 111 If RANGE 0 = 0 or OSCSEL=1 , Divide Factor is 128; for all other RANGE 0 values, Divide Factor is Reserved . #111 IRCLKEN Internal Reference Clock Enable 1 1 read-write 0 MCGIRCLK inactive. #0 1 MCGIRCLK active. #1 IREFS Internal Reference Select 2 1 read-write 0 External reference clock is selected. #0 1 The slow internal reference clock is selected. #1 IREFSTEN Internal Reference Stop Enable 0 1 read-write 0 Internal reference clock is disabled in Stop mode. #0 1 Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode. #1 C10 MCG Control 10 Register 0xF 8 read-write n 0x0 0x0 EREFS1 External Reference Select 2 1 read-write 0 External reference clock requested. #0 1 Oscillator requested. #1 HGO1 High Gain Oscillator1 Select 3 1 read-write 0 Configure crystal oscillator for low-power operation. #0 1 Configure crystal oscillator for high-gain operation. #1 LOCRE2 OSC1 Loss of Clock Reset Enable 7 1 read-write 0 Interrupt request is generated on a loss of OSC1 external reference clock. #0 1 Reset request is generated on a loss of OSC1 external reference clock. #1 RANGE1 Frequency Range1 Select 4 2 read-write 00 Encoding 0 - Low frequency range selected for the crystal oscillator . #00 01 Encoding 1 - High frequency range selected for the crystal oscillator . #01 RESERVED no description available 0 2 read-only RESERVED no description available 6 1 read-only C11 MCG Control 11 Register 0x10 8 read-write n 0x0 0x0 PLLCLKEN1 PLL1 Clock Enable 6 1 read-write 0 MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X are inactive #0 1 MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X are active unless MCG is in a bypass mode with LP=1 (BLPI or BLPE). #1 PLLCS PLL Clock Select 4 1 read-write 0 PLL0 output clock is selected. #0 1 PLL1 output clock is selected. #1 PLLREFSEL1 PLL1 External Reference Select 7 1 read-write 0 Selects OSC0 clock source as its external reference clock. #0 1 Selects OSC1 clock source as its external reference clock. #1 PLLSTEN1 PLL1 Stop Enable 5 1 read-write 0 PLL1 clocks (MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X) are disabled in any of the Stop modes. #0 1 PLL1 and its clocks (MCGPLL1CLK, MCGPLL1CLK2X, and MCGDDRCLK2X) are enabled if system is in Normal Stop mode. #1 PRDIV1 PLL1 External Reference Divider 0 3 read-write RESERVED no description available 3 1 read-only C12 MCG Control 12 Register 0x11 8 read-write n 0x0 0x0 CME2 Clock Monitor Enable2 5 1 read-write 0 External clock monitor for OSC1 is disabled. #0 1 Generate a reset request on loss of external clock on OSC1. #1 LOLIE1 PLL1 Loss of Lock Interrupt Enable 7 1 read-write 0 No interrupt request is generated on loss of lock on PLL1. #0 1 Generate an interrupt request on loss of lock on PLL1. #1 RESERVED Reserved 6 1 read-only VDIV1 VCO1 Divider 0 5 read-write C2 MCG Control 2 Register 0x1 8 read-write n 0x0 0x0 EREFS0 External Reference Select 2 1 read-write 0 External reference clock requested. #0 1 Oscillator requested. #1 HGO0 High Gain Oscillator Select 3 1 read-write 0 Configure crystal oscillator for low-power operation. #0 1 Configure crystal oscillator for high-gain operation. #1 IRCS Internal Reference Clock Select 0 1 read-write 0 Slow internal reference clock selected. #0 1 Fast internal reference clock selected. #1 LOCRE0 Loss of Clock Reset Enable 7 1 read-write 0 Interrupt request is generated on a loss of OSC0 external reference clock. #0 1 Generate a reset request on a loss of OSC0 external reference clock #1 LP Low Power Select 1 1 read-write 0 FLL (or PLL) is not disabled in bypass modes. #0 1 FLL (or PLL) is disabled in bypass modes (lower power) #1 RANGE0 Frequency Range Select 4 2 read-write 00 Encoding 0 - Low frequency range selected for the crystal oscillator . #00 01 Encoding 1 - High frequency range selected for the crystal oscillator . #01 RESERVED no description available 6 1 read-only C3 MCG Control 3 Register 0x2 8 read-write n 0x0 0x0 SCTRIM Slow Internal Reference Clock Trim Setting 0 8 read-write C4 MCG Control 4 Register 0x3 8 read-write n 0x0 0x0 DMX32 DCO Maximum Frequency with 32.768 kHz Reference 7 1 read-write 0 DCO has a default range of 25%. #0 1 DCO is fine-tuned for maximum frequency with 32.768 kHz reference. #1 DRST_DRS DCO Range Select 5 2 read-write 00 Encoding 0 - Low range (reset default). #00 01 Encoding 1 - Mid range. #01 10 Encoding 2 - Mid-high range. #10 11 Encoding 3 - High range. #11 FCTRIM Fast Internal Reference Clock Trim Setting 1 4 read-write SCFTRIM Slow Internal Reference Clock Fine Trim 0 1 read-write C5 MCG Control 5 Register 0x4 8 read-write n 0x0 0x0 PLLCLKEN0 PLL Clock Enable 6 1 read-write 0 MCGPLL0CLK and MCGPLL0CLK2X are inactive. #0 1 MCGPLL0CLK and MCGPLL0CLK2X are active. #1 PLLREFSEL0 PLL0 External Reference Select 7 1 read-write 0 Selects OSC0 clock source as its external reference clock. #0 1 Selects OSC1 clock source as its external reference clock. #1 PLLSTEN0 PLL0 Stop Enable 5 1 read-write 0 MCGPLL0CLK and MCGPLL0CLK2X are disabled in any of the Stop modes. #0 1 MCGPLL0CLK and MCGPLL0CLK2X are enabled if system is in Normal Stop mode. #1 PRDIV0 PLL0 External Reference Divider 0 3 read-write RESERVED Reserved 3 2 read-only C6 MCG Control 6 Register 0x5 8 read-write n 0x0 0x0 CME0 Clock Monitor Enable 5 1 read-write 0 External clock monitor is disabled for OSC0. #0 1 External clock monitor is enabled for OSC0. #1 LOLIE0 Loss of Lock Interrrupt Enable 7 1 read-write 0 No interrupt request is generated on loss of lock. #0 1 Generate an interrupt request on loss of lock. #1 PLLS PLL Select 6 1 read-write 0 FLL is selected. #0 1 PLLCS output clock is selected (PRDIV0 bits of PLL in control need to be programmed to the correct divider to generate a PLL reference clock in the range of 1 - 32 MHz prior to setting the PLLS bit). #1 VDIV0 VCO0 Divider 0 5 read-write C7 MCG Control 7 Register 0xC 8 read-write n 0x0 0x0 OSCSEL MCG OSC Clock Select 0 1 read-write 0 Selects System Oscillator (OSCCLK). #0 1 Selects 32 kHz RTC Oscillator. #1 RESERVED no description available 1 7 read-only C8 MCG Control 8 Register 0xD 8 read-write n 0x0 0x0 CME1 Clock Monitor Enable1 5 1 read-write 0 External clock monitor is disabled for RTC clock. #0 1 External clock monitor is enabled for RTC clock. #1 LOCRE1 Loss of Clock Reset Enable 7 1 read-write 0 Interrupt request is generated on a loss of RTC external reference clock. #0 1 Generate a reset request on a loss of RTC external reference clock #1 LOCS1 RTC Loss of Clock Status 0 1 read-only 0 Loss of RTC has not occur. #0 1 Loss of RTC has occur #1 RESERVED no description available 1 4 read-only RESERVED no description available 6 1 read-only S MCG Status Register 0x6 8 read-only n 0x0 0x0 CLKST Clock Mode Status 2 2 read-only 00 Encoding 0 - Output of the FLL is selected (reset default). #00 01 Encoding 1 - Internal reference clock is selected. #01 10 Encoding 2 - External reference clock is selected. #10 11 Encoding 3 - Output of the PLL is selected. #11 IRCST Internal Reference Clock Status 0 1 read-only 0 Source of internal reference clock is the slow clock (32 kHz IRC). #0 1 Source of internal reference clock is the fast clock (2 MHz IRC). #1 IREFST Internal Reference Status 4 1 read-only 0 Source of FLL reference clock is the external reference clock. #0 1 Source of FLL reference clock is the internal reference clock. #1 LOCK0 Lock Status 6 1 read-only 0 PLL is currently unlocked. #0 1 PLL is currently locked. #1 LOLS0 Loss of Lock Status 7 1 read-only 0 PLL has not lost lock since LOLS 0 was last cleared. #0 1 PLL has lost lock since LOLS 0 was last cleared. #1 OSCINIT0 OSC Initialization 1 1 read-only PLLST PLL Select Status 5 1 read-only 0 Source of PLLS clock is FLL clock. #0 1 Source of PLLS clock is PLLCS output clock. #1 S2 MCG Status 2 Register 0x12 8 read-only n 0x0 0x0 LOCK1 Lock1 Status 6 1 read-only 0 PLL1 is currently unlocked. #0 1 PLL1 is currently locked. #1 LOCS2 OSC1 Loss of Clock Status 0 1 read-only 0 No loss of OSC1 external reference clock has occurred. #0 1 Loss of OSC1 external reference clock has occurred. #1 LOLS1 Loss of Lock2 Status 7 1 read-only 0 PLL1 has not lost lock since LOLS1 was last cleared. #0 1 PLL1 has lost lock since LOLS1 was last cleared. #1 OSCINIT1 OSC1 Initialization 1 1 read-only PLLCST PLL Clock Select Status 4 1 read-only 0 Source of PLLCS is PLL0 clock. #0 1 Source of PLLCS is PLL1 clock. #1 RESERVED no description available 2 2 read-only RESERVED no description available 5 1 read-only SC MCG Status and Control Register 0x8 8 read-write n 0x0 0x0 ATME Automatic Trim Machine Enable 7 1 read-write 0 Auto Trim Machine disabled. #0 1 Auto Trim Machine enabled. #1 ATMF Automatic Trim machine Fail Flag 5 1 read-only 0 Automatic Trim Machine completed normally. #0 1 Automatic Trim Machine failed. #1 ATMS Automatic Trim Machine Select 6 1 read-write 0 32 kHz Internal Reference Clock selected. #0 1 4 MHz Internal Reference Clock selected. #1 FCRDIV Fast Clock Internal Reference Divider 1 3 read-write 000 Divide Factor is 1 #000 001 Divide Factor is 2. #001 010 Divide Factor is 4. #010 011 Divide Factor is 8. #011 100 Divide Factor is 16 #100 101 Divide Factor is 32 #101 110 Divide Factor is 64 #110 111 Divide Factor is 128. #111 FLTPRSRV FLL Filter Preserve Enable 4 1 read-write 0 FLL filter and FLL frequency will reset on changes to currect clock mode. #0 1 Fll filter and FLL frequency retain their previous values during new clock mode change. #1 LOCS0 OSC0 Loss of Clock Status 0 1 read-only 0 Loss of OSC0 has not occurred. #0 1 Loss of OSC0 has occurred. #1 MCM Core Platform Miscellaneous Control Module MCM 0x0 0x8 0x2C registers n CR Control Register 0xC 32 read-write n 0x0 0x0 RESERVED no description available 0 9 read-only RESERVED no description available 9 1 read-only RESERVED no description available 10 14 read-only RESERVED no description available 27 1 read-only RESERVED no description available 31 1 read-only SRAMLAP SRAM_L arbitration priority 28 2 read-write 00 Round robin #00 01 Special round robin (favors SRAM backoor accesses over the processor) #01 10 Fixed priority. Processor has highest, backdoor has lowest #10 11 Fixed priority. Backdoor has highest, processor has lowest #11 SRAMLWP SRAM_L Write Protect 30 1 read-write SRAMUAP SRAM_U arbitration priority 24 2 read-write 00 Round robin #00 01 Special round robin (favors SRAM backoor accesses over the processor) #01 10 Fixed priority. Processor has highest, backdoor has lowest #10 11 Fixed priority. Backdoor has highest, processor has lowest #11 SRAMUWP SRAM_U write protect 26 1 read-write ETBCC ETB Counter Control register 0x14 32 read-write n 0x0 0x0 CNTEN Counter Enable 0 1 read-write 0 ETB counter disabled #0 1 ETB counter enabled #1 ETDIS ETM-To-TPIU Disable 4 1 read-write 0 ETM-to-TPIU trace path enabled #0 1 ETM-to-TPIU trace path disabled #1 ITDIS ITM-To-TPIU Disable 5 1 read-write 0 ITM-to-TPIU trace path enabled #0 1 ITM-to-TPIU trace path disabled #1 RESERVED no description available 6 26 read-only RLRQ Reload Request 3 1 read-write 0 No effect #0 1 Clears pending debug halt, NMI, or IRQ interrupt requests #1 RSPT Response Type 1 2 read-write 00 No response when the ETB count expires #00 01 Generate a normal interrupt when the ETB count expires #01 10 Generate an NMI when the ETB count expires #10 11 Generate a debug halt when the ETB count expires #11 ETBCNT ETB Counter Value register 0x1C 32 read-only n 0x0 0x0 COUNTER Byte Count Counter Value 0 11 read-only RESERVED no description available 11 21 read-only ETBRL ETB Reload register 0x18 32 read-write n 0x0 0x0 RELOAD Byte Count Reload Value 0 11 read-write RESERVED no description available 11 21 read-only FADR Fault address register 0x20 32 read-only n 0x0 0x0 ADDRESS Fault address 0 32 read-only FATR Fault attributes register 0x24 32 read-only n 0x0 0x0 BEDA Bus error access type 0 1 read-only 0 Instruction #0 1 Data #1 BEMD Bus error privilege level 1 1 read-only 0 User mode #0 1 Supervisor/privileged mode #1 BEMN Bus error master number 8 4 read-only BEOVR Bus error overrun 31 1 read-only 0 No bus error overrun #0 1 Bus error overrun occurred. The FADR and FDR registers and the other FATR bits are not updated to reflect this new bus error. #1 BESZ Bus error size 4 2 read-only 00 8-bit access #00 01 16-bit access #01 10 32-bit access #10 11 Reserved #11 BEWT Bus error write 7 1 read-only 0 Read access #0 1 Write access #1 RESERVED no description available 2 2 read-only RESERVED no description available 6 1 read-only RESERVED no description available 12 19 read-only FDR Fault data register 0x28 32 read-only n 0x0 0x0 DATA Fault data 0 32 read-only ISCR Interrupt Status and control Register 0x10 32 read-write n 0x0 0x0 CWBEE Cache write buffer error enable 20 1 read-write 0 Disable error interrupt #0 1 Enable error interrupt #1 CWBER Cache write buffer error status 4 1 read-write 0 No error #0 1 Error occurred #1 DHREQ Debug Halt Request Indicator 3 1 read-only 0 No debug halt request #0 1 Debug halt request initiated #1 FDZC FPU divide-by-zero interrupt status 9 1 read-only 0 No interrupt #0 1 Interrupt occurred #1 FDZCE FPU divide-by-zero interrupt enable 25 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 FIDC FPU input denormal interrupt status 15 1 read-only 0 No interrupt #0 1 Interrupt occurred #1 FIDCE FPU input denormal interrupt enable 31 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 FIOC FPU invalid operation interrupt status 8 1 read-only 0 No interrupt #0 1 Interrupt occurred #1 FIOCE FPU invalid operation interrupt enable 24 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 FIXC FPU inexact interrupt status 12 1 read-only 0 No interrupt #0 1 Interrupt occurred #1 FIXCE FPU inexact interrupt enable 28 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 FOFC FPU overflow interrupt status 10 1 read-only 0 No interrupt #0 1 Interrupt occurred #1 FOFCE FPU overflow interrupt enable 26 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 FUFC FPU underflow interrupt status 11 1 read-only 0 No interrupt #0 1 Interrupt occurred #1 FUFCE FPU underflow interrupt enable 27 1 read-write 0 Disable interrupt #0 1 Enable interrupt #1 IRQ Normal Interrupt Pending 1 1 read-write 0 No pending interrupt #0 1 Due to the ETB counter expiring, a normal interrupt is pending #1 NMI Nonmaskable Interrupt Pending 2 1 read-write 0 No pending NMI #0 1 Due to the ETB counter expiring, an NMI is pending #1 RESERVED no description available 0 1 read-only RESERVED no description available 5 3 read-only RESERVED no description available 13 2 read-only RESERVED no description available 16 4 read-only RESERVED no description available 21 3 read-only RESERVED no description available 29 2 read-only PID Process ID register 0x30 32 read-write n 0x0 0x0 PID M0_PID and M1_PID for MPU 0 8 read-write RESERVED no description available 8 24 read-only PLAMC Crossbar Switch (AXBS) Master Configuration 0xA 16 read-only n 0x0 0x0 AMC Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port. 0 8 read-only 0 A bus master connection to AXBS input port n is absent #0 1 A bus master connection to AXBS input port n is present #1 RESERVED no description available 8 8 read-only PLASC Crossbar Switch (AXBS) Slave Configuration 0x8 16 read-only n 0x0 0x0 ASC Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port. 0 8 read-only 0 A bus slave connection to AXBS input port n is absent #0 1 A bus slave connection to AXBS input port n is present #1 RESERVED no description available 8 8 read-only MPU Memory protection unit MPU 0x0 0x0 0x830 registers n 0x0 0x840 registers n CESR Control/Error Status Register 0x0 32 read-write n 0x0 0x0 HRL Hardware revision level 16 4 read-only NRGD Number of region descriptors 8 4 read-only 0000 8 region descriptors #0000 0001 12 region descriptors #0001 0010 16 region descriptors #0010 NSP Number of slave ports 12 4 read-only RESERVED no description available 1 7 read-only RESERVED no description available 20 3 read-only RESERVED no description available 23 1 read-only SPERR Slave port n error 24 8 read-write 0 No error has occurred for slave port n. #0 1 An error has occurred for slave port n. #1 VLD Valid (global enable/disable for the MPU) 0 1 read-write 0 MPU is disabled. All accesses from all bus masters are allowed. #0 1 MPU is enabled #1 EAR0 Error Address Register, Slave Port n 0x20 32 read-only n 0x0 0x0 EADDR Error address 0 32 read-only EAR1 Error Address Register, Slave Port n 0x38 32 read-only n 0x0 0x0 EADDR Error address 0 32 read-only EAR2 Error Address Register, Slave Port n 0x58 32 read-only n 0x0 0x0 EADDR Error address 0 32 read-only EAR3 Error Address Register, Slave Port n 0x80 32 read-only n 0x0 0x0 EADDR Error address 0 32 read-only EAR4 Error Address Register, Slave Port n 0xB0 32 read-only n 0x0 0x0 EADDR Error address 0 32 read-only EDR0 Error Detail Register, Slave Port n 0x28 32 read-only n 0x0 0x0 EACD Error access control detail 16 16 read-only EATTR Error attributes 1 3 read-only 000 User mode, instruction access #000 001 User mode, data access #001 010 Supervisor mode, instruction access #010 011 Supervisor mode, data access #011 EMN Error master number 4 4 read-only EPID Error process identification 8 8 read-only ERW Error read/write 0 1 read-only 0 Read #0 1 Write #1 EDR1 Error Detail Register, Slave Port n 0x44 32 read-only n 0x0 0x0 EACD Error access control detail 16 16 read-only EATTR Error attributes 1 3 read-only 000 User mode, instruction access #000 001 User mode, data access #001 010 Supervisor mode, instruction access #010 011 Supervisor mode, data access #011 EMN Error master number 4 4 read-only EPID Error process identification 8 8 read-only ERW Error read/write 0 1 read-only 0 Read #0 1 Write #1 EDR2 Error Detail Register, Slave Port n 0x68 32 read-only n 0x0 0x0 EACD Error access control detail 16 16 read-only EATTR Error attributes 1 3 read-only 000 User mode, instruction access #000 001 User mode, data access #001 010 Supervisor mode, instruction access #010 011 Supervisor mode, data access #011 EMN Error master number 4 4 read-only EPID Error process identification 8 8 read-only ERW Error read/write 0 1 read-only 0 Read #0 1 Write #1 EDR3 Error Detail Register, Slave Port n 0x94 32 read-only n 0x0 0x0 EACD Error access control detail 16 16 read-only EATTR Error attributes 1 3 read-only 000 User mode, instruction access #000 001 User mode, data access #001 010 Supervisor mode, instruction access #010 011 Supervisor mode, data access #011 EMN Error master number 4 4 read-only EPID Error process identification 8 8 read-only ERW Error read/write 0 1 read-only 0 Read #0 1 Write #1 EDR4 Error Detail Register, Slave Port n 0xC8 32 read-only n 0x0 0x0 EACD Error access control detail 16 16 read-only EATTR Error attributes 1 3 read-only 000 User mode, instruction access #000 001 User mode, data access #001 010 Supervisor mode, instruction access #010 011 Supervisor mode, data access #011 EMN Error master number 4 4 read-only EPID Error process identification 8 8 read-only ERW Error read/write 0 1 read-only 0 Read #0 1 Write #1 RGD0_WORD0 Region Descriptor n, Word 0 0x800 32 read-write n 0x0 0x0 RESERVED no description available 0 5 read-only SRTADDR Start address 5 27 read-write RGD0_WORD1 Region Descriptor n, Word 1 0x808 32 read-write n 0x0 0x0 ENDADDR End address 5 27 read-write RESERVED no description available 0 5 read-only RGD0_WORD2 Region Descriptor n, Word 2 0x810 32 read-write n 0x0 0x0 M0PE Bus master 0 process identifier enable 5 1 read-write M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1PE Bus master 1 process identifier enable 11 1 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2PE Bus master 2 process identifier enable 17 1 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3PE Bus master 3 process identifier enable. 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation #1 M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD0_WORD3 Region Descriptor n, Word 3 0x818 32 read-write n 0x0 0x0 PID Process identifier 24 8 read-write PIDMASK Process identifier mask 16 8 read-write RESERVED no description available 1 15 read-only VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD10_WORD0 Region Descriptor n, Word 0 0x3370 32 read-write n 0x0 0x0 RESERVED no description available 0 5 read-only SRTADDR Start address 5 27 read-write RGD10_WORD1 Region Descriptor n, Word 1 0x33A0 32 read-write n 0x0 0x0 ENDADDR End address 5 27 read-write RESERVED no description available 0 5 read-only RGD10_WORD2 Region Descriptor n, Word 2 0x33D0 32 read-write n 0x0 0x0 M0PE Bus master 0 process identifier enable 5 1 read-write M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1PE Bus master 1 process identifier enable 11 1 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2PE Bus master 2 process identifier enable 17 1 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3PE Bus master 3 process identifier enable. 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation #1 M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD10_WORD3 Region Descriptor n, Word 3 0x3400 32 read-write n 0x0 0x0 PID Process identifier 24 8 read-write PIDMASK Process identifier mask 16 8 read-write RESERVED no description available 1 15 read-only VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD11_WORD0 Region Descriptor n, Word 0 0x3820 32 read-write n 0x0 0x0 RESERVED no description available 0 5 read-only SRTADDR Start address 5 27 read-write RGD11_WORD1 Region Descriptor n, Word 1 0x3854 32 read-write n 0x0 0x0 ENDADDR End address 5 27 read-write RESERVED no description available 0 5 read-only RGD11_WORD2 Region Descriptor n, Word 2 0x3888 32 read-write n 0x0 0x0 M0PE Bus master 0 process identifier enable 5 1 read-write M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1PE Bus master 1 process identifier enable 11 1 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2PE Bus master 2 process identifier enable 17 1 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3PE Bus master 3 process identifier enable. 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation #1 M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD11_WORD3 Region Descriptor n, Word 3 0x38BC 32 read-write n 0x0 0x0 PID Process identifier 24 8 read-write PIDMASK Process identifier mask 16 8 read-write RESERVED no description available 1 15 read-only VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD12_WORD0 Region Descriptor n, Word 0 0x3CE0 32 read-write n 0x0 0x0 SRTADDR Start address 5 27 read-write RGD12_WORD1 Region Descriptor n, Word 1 0x3D18 32 read-write n 0x0 0x0 ENDADDR End address 5 27 read-write RGD12_WORD2 Region Descriptor n, Word 2 0x3D50 32 read-write n 0x0 0x0 M0PE Bus master 0 process identifier enable 5 1 read-write M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1PE Bus master 1 process identifier enable 11 1 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2PE Bus master 2 process identifier enable 17 1 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3PE Bus master 3 process identifier enable. 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation #1 M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD12_WORD3 Region Descriptor n, Word 3 0x3D88 32 read-write n 0x0 0x0 PID Process identifier 24 8 read-write PIDMASK Process identifier mask 16 8 read-write VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD13_WORD0 Region Descriptor n, Word 0 0x41B0 32 read-write n 0x0 0x0 SRTADDR Start address 5 27 read-write RGD13_WORD1 Region Descriptor n, Word 1 0x41EC 32 read-write n 0x0 0x0 ENDADDR End address 5 27 read-write RGD13_WORD2 Region Descriptor n, Word 2 0x4228 32 read-write n 0x0 0x0 M0PE Bus master 0 process identifier enable 5 1 read-write M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1PE Bus master 1 process identifier enable 11 1 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2PE Bus master 2 process identifier enable 17 1 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3PE Bus master 3 process identifier enable. 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation #1 M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD13_WORD3 Region Descriptor n, Word 3 0x4264 32 read-write n 0x0 0x0 PID Process identifier 24 8 read-write PIDMASK Process identifier mask 16 8 read-write VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD14_WORD0 Region Descriptor n, Word 0 0x4690 32 read-write n 0x0 0x0 SRTADDR Start address 5 27 read-write RGD14_WORD1 Region Descriptor n, Word 1 0x46D0 32 read-write n 0x0 0x0 ENDADDR End address 5 27 read-write RGD14_WORD2 Region Descriptor n, Word 2 0x4710 32 read-write n 0x0 0x0 M0PE Bus master 0 process identifier enable 5 1 read-write M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1PE Bus master 1 process identifier enable 11 1 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2PE Bus master 2 process identifier enable 17 1 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3PE Bus master 3 process identifier enable. 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation #1 M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD14_WORD3 Region Descriptor n, Word 3 0x4750 32 read-write n 0x0 0x0 PID Process identifier 24 8 read-write PIDMASK Process identifier mask 16 8 read-write VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD15_WORD0 Region Descriptor n, Word 0 0x4B80 32 read-write n 0x0 0x0 SRTADDR Start address 5 27 read-write RGD15_WORD1 Region Descriptor n, Word 1 0x4BC4 32 read-write n 0x0 0x0 ENDADDR End address 5 27 read-write RGD15_WORD2 Region Descriptor n, Word 2 0x4C08 32 read-write n 0x0 0x0 M0PE Bus master 0 process identifier enable 5 1 read-write M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1PE Bus master 1 process identifier enable 11 1 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2PE Bus master 2 process identifier enable 17 1 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3PE Bus master 3 process identifier enable. 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation #1 M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD15_WORD3 Region Descriptor n, Word 3 0x4C4C 32 read-write n 0x0 0x0 PID Process identifier 24 8 read-write PIDMASK Process identifier mask 16 8 read-write VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD1_WORD0 Region Descriptor n, Word 0 0xC10 32 read-write n 0x0 0x0 RESERVED no description available 0 5 read-only SRTADDR Start address 5 27 read-write RGD1_WORD1 Region Descriptor n, Word 1 0xC1C 32 read-write n 0x0 0x0 ENDADDR End address 5 27 read-write RESERVED no description available 0 5 read-only RGD1_WORD2 Region Descriptor n, Word 2 0xC28 32 read-write n 0x0 0x0 M0PE Bus master 0 process identifier enable 5 1 read-write M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1PE Bus master 1 process identifier enable 11 1 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2PE Bus master 2 process identifier enable 17 1 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3PE Bus master 3 process identifier enable. 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation #1 M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD1_WORD3 Region Descriptor n, Word 3 0xC34 32 read-write n 0x0 0x0 PID Process identifier 24 8 read-write PIDMASK Process identifier mask 16 8 read-write RESERVED no description available 1 15 read-only VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD2_WORD0 Region Descriptor n, Word 0 0x1030 32 read-write n 0x0 0x0 RESERVED no description available 0 5 read-only SRTADDR Start address 5 27 read-write RGD2_WORD1 Region Descriptor n, Word 1 0x1040 32 read-write n 0x0 0x0 ENDADDR End address 5 27 read-write RESERVED no description available 0 5 read-only RGD2_WORD2 Region Descriptor n, Word 2 0x1050 32 read-write n 0x0 0x0 M0PE Bus master 0 process identifier enable 5 1 read-write M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1PE Bus master 1 process identifier enable 11 1 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2PE Bus master 2 process identifier enable 17 1 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3PE Bus master 3 process identifier enable. 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation #1 M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD2_WORD3 Region Descriptor n, Word 3 0x1060 32 read-write n 0x0 0x0 PID Process identifier 24 8 read-write PIDMASK Process identifier mask 16 8 read-write RESERVED no description available 1 15 read-only VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD3_WORD0 Region Descriptor n, Word 0 0x1460 32 read-write n 0x0 0x0 RESERVED no description available 0 5 read-only SRTADDR Start address 5 27 read-write RGD3_WORD1 Region Descriptor n, Word 1 0x1474 32 read-write n 0x0 0x0 ENDADDR End address 5 27 read-write RESERVED no description available 0 5 read-only RGD3_WORD2 Region Descriptor n, Word 2 0x1488 32 read-write n 0x0 0x0 M0PE Bus master 0 process identifier enable 5 1 read-write M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1PE Bus master 1 process identifier enable 11 1 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2PE Bus master 2 process identifier enable 17 1 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3PE Bus master 3 process identifier enable. 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation #1 M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD3_WORD3 Region Descriptor n, Word 3 0x149C 32 read-write n 0x0 0x0 PID Process identifier 24 8 read-write PIDMASK Process identifier mask 16 8 read-write RESERVED no description available 1 15 read-only VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD4_WORD0 Region Descriptor n, Word 0 0x18A0 32 read-write n 0x0 0x0 RESERVED no description available 0 5 read-only SRTADDR Start address 5 27 read-write RGD4_WORD1 Region Descriptor n, Word 1 0x18B8 32 read-write n 0x0 0x0 ENDADDR End address 5 27 read-write RESERVED no description available 0 5 read-only RGD4_WORD2 Region Descriptor n, Word 2 0x18D0 32 read-write n 0x0 0x0 M0PE Bus master 0 process identifier enable 5 1 read-write M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1PE Bus master 1 process identifier enable 11 1 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2PE Bus master 2 process identifier enable 17 1 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3PE Bus master 3 process identifier enable. 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation #1 M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD4_WORD3 Region Descriptor n, Word 3 0x18E8 32 read-write n 0x0 0x0 PID Process identifier 24 8 read-write PIDMASK Process identifier mask 16 8 read-write RESERVED no description available 1 15 read-only VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD5_WORD0 Region Descriptor n, Word 0 0x1CF0 32 read-write n 0x0 0x0 RESERVED no description available 0 5 read-only SRTADDR Start address 5 27 read-write RGD5_WORD1 Region Descriptor n, Word 1 0x1D0C 32 read-write n 0x0 0x0 ENDADDR End address 5 27 read-write RESERVED no description available 0 5 read-only RGD5_WORD2 Region Descriptor n, Word 2 0x1D28 32 read-write n 0x0 0x0 M0PE Bus master 0 process identifier enable 5 1 read-write M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1PE Bus master 1 process identifier enable 11 1 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2PE Bus master 2 process identifier enable 17 1 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3PE Bus master 3 process identifier enable. 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation #1 M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD5_WORD3 Region Descriptor n, Word 3 0x1D44 32 read-write n 0x0 0x0 PID Process identifier 24 8 read-write PIDMASK Process identifier mask 16 8 read-write RESERVED no description available 1 15 read-only VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD6_WORD0 Region Descriptor n, Word 0 0x2150 32 read-write n 0x0 0x0 RESERVED no description available 0 5 read-only SRTADDR Start address 5 27 read-write RGD6_WORD1 Region Descriptor n, Word 1 0x2170 32 read-write n 0x0 0x0 ENDADDR End address 5 27 read-write RESERVED no description available 0 5 read-only RGD6_WORD2 Region Descriptor n, Word 2 0x2190 32 read-write n 0x0 0x0 M0PE Bus master 0 process identifier enable 5 1 read-write M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1PE Bus master 1 process identifier enable 11 1 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2PE Bus master 2 process identifier enable 17 1 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3PE Bus master 3 process identifier enable. 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation #1 M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD6_WORD3 Region Descriptor n, Word 3 0x21B0 32 read-write n 0x0 0x0 PID Process identifier 24 8 read-write PIDMASK Process identifier mask 16 8 read-write RESERVED no description available 1 15 read-only VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD7_WORD0 Region Descriptor n, Word 0 0x25C0 32 read-write n 0x0 0x0 RESERVED no description available 0 5 read-only SRTADDR Start address 5 27 read-write RGD7_WORD1 Region Descriptor n, Word 1 0x25E4 32 read-write n 0x0 0x0 ENDADDR End address 5 27 read-write RESERVED no description available 0 5 read-only RGD7_WORD2 Region Descriptor n, Word 2 0x2608 32 read-write n 0x0 0x0 M0PE Bus master 0 process identifier enable 5 1 read-write M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1PE Bus master 1 process identifier enable 11 1 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2PE Bus master 2 process identifier enable 17 1 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3PE Bus master 3 process identifier enable. 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation #1 M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD7_WORD3 Region Descriptor n, Word 3 0x262C 32 read-write n 0x0 0x0 PID Process identifier 24 8 read-write PIDMASK Process identifier mask 16 8 read-write RESERVED no description available 1 15 read-only VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD8_WORD0 Region Descriptor n, Word 0 0x2A40 32 read-write n 0x0 0x0 RESERVED no description available 0 5 read-only SRTADDR Start address 5 27 read-write RGD8_WORD1 Region Descriptor n, Word 1 0x2A68 32 read-write n 0x0 0x0 ENDADDR End address 5 27 read-write RESERVED no description available 0 5 read-only RGD8_WORD2 Region Descriptor n, Word 2 0x2A90 32 read-write n 0x0 0x0 M0PE Bus master 0 process identifier enable 5 1 read-write M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1PE Bus master 1 process identifier enable 11 1 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2PE Bus master 2 process identifier enable 17 1 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3PE Bus master 3 process identifier enable. 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation #1 M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD8_WORD3 Region Descriptor n, Word 3 0x2AB8 32 read-write n 0x0 0x0 PID Process identifier 24 8 read-write PIDMASK Process identifier mask 16 8 read-write RESERVED no description available 1 15 read-only VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGD9_WORD0 Region Descriptor n, Word 0 0x2ED0 32 read-write n 0x0 0x0 RESERVED no description available 0 5 read-only SRTADDR Start address 5 27 read-write RGD9_WORD1 Region Descriptor n, Word 1 0x2EFC 32 read-write n 0x0 0x0 ENDADDR End address 5 27 read-write RESERVED no description available 0 5 read-only RGD9_WORD2 Region Descriptor n, Word 2 0x2F28 32 read-write n 0x0 0x0 M0PE Bus master 0 process identifier enable 5 1 read-write M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1PE Bus master 1 process identifier enable 11 1 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2PE Bus master 2 process identifier enable 17 1 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3PE Bus master 3 process identifier enable. 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation #1 M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGD9_WORD3 Region Descriptor n, Word 3 0x2F54 32 read-write n 0x0 0x0 PID Process identifier 24 8 read-write PIDMASK Process identifier mask 16 8 read-write RESERVED no description available 1 15 read-only VLD Valid 0 1 read-write 0 Region descriptor is invalid #0 1 Region descriptor is valid #1 RGDAAC0 Region Descriptor Alternate Access Control n 0x1000 32 read-write n 0x0 0x0 M0PE Bus master 0 process identifier enable 5 1 read-write M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1PE Bus master 1 process identifier enable 11 1 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2PE Bus master 2 process identifier enable 17 1 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3PE Bus master 3 process identifier enable. 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC1 Region Descriptor Alternate Access Control n 0x1804 32 read-write n 0x0 0x0 M0PE Bus master 0 process identifier enable 5 1 read-write M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1PE Bus master 1 process identifier enable 11 1 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2PE Bus master 2 process identifier enable 17 1 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3PE Bus master 3 process identifier enable. 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC10 Region Descriptor Alternate Access Control n 0x60DC 32 read-write n 0x0 0x0 M0PE Bus master 0 process identifier enable 5 1 read-write M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1PE Bus master 1 process identifier enable 11 1 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2PE Bus master 2 process identifier enable 17 1 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3PE Bus master 3 process identifier enable. 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC11 Region Descriptor Alternate Access Control n 0x6908 32 read-write n 0x0 0x0 M0PE Bus master 0 process identifier enable 5 1 read-write M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1PE Bus master 1 process identifier enable 11 1 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2PE Bus master 2 process identifier enable 17 1 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3PE Bus master 3 process identifier enable. 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC12 Region Descriptor Alternate Access Control n 0x7138 32 read-write n 0x0 0x0 M0PE Bus master 0 process identifier enable 5 1 read-write M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1PE Bus master 1 process identifier enable 11 1 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2PE Bus master 2 process identifier enable 17 1 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3PE Bus master 3 process identifier enable. 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC13 Region Descriptor Alternate Access Control n 0x796C 32 read-write n 0x0 0x0 M0PE Bus master 0 process identifier enable 5 1 read-write M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1PE Bus master 1 process identifier enable 11 1 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2PE Bus master 2 process identifier enable 17 1 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3PE Bus master 3 process identifier enable. 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC14 Region Descriptor Alternate Access Control n 0x81A4 32 read-write n 0x0 0x0 M0PE Bus master 0 process identifier enable 5 1 read-write M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1PE Bus master 1 process identifier enable 11 1 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2PE Bus master 2 process identifier enable 17 1 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3PE Bus master 3 process identifier enable. 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC15 Region Descriptor Alternate Access Control n 0x89E0 32 read-write n 0x0 0x0 M0PE Bus master 0 process identifier enable 5 1 read-write M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1PE Bus master 1 process identifier enable 11 1 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2PE Bus master 2 process identifier enable 17 1 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3PE Bus master 3 process identifier enable. 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC2 Region Descriptor Alternate Access Control n 0x200C 32 read-write n 0x0 0x0 M0PE Bus master 0 process identifier enable 5 1 read-write M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1PE Bus master 1 process identifier enable 11 1 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2PE Bus master 2 process identifier enable 17 1 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3PE Bus master 3 process identifier enable. 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC3 Region Descriptor Alternate Access Control n 0x2818 32 read-write n 0x0 0x0 M0PE Bus master 0 process identifier enable 5 1 read-write M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1PE Bus master 1 process identifier enable 11 1 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2PE Bus master 2 process identifier enable 17 1 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3PE Bus master 3 process identifier enable. 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC4 Region Descriptor Alternate Access Control n 0x3028 32 read-write n 0x0 0x0 M0PE Bus master 0 process identifier enable 5 1 read-write M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1PE Bus master 1 process identifier enable 11 1 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2PE Bus master 2 process identifier enable 17 1 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3PE Bus master 3 process identifier enable. 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC5 Region Descriptor Alternate Access Control n 0x383C 32 read-write n 0x0 0x0 M0PE Bus master 0 process identifier enable 5 1 read-write M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1PE Bus master 1 process identifier enable 11 1 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2PE Bus master 2 process identifier enable 17 1 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3PE Bus master 3 process identifier enable. 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC6 Region Descriptor Alternate Access Control n 0x4054 32 read-write n 0x0 0x0 M0PE Bus master 0 process identifier enable 5 1 read-write M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1PE Bus master 1 process identifier enable 11 1 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2PE Bus master 2 process identifier enable 17 1 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3PE Bus master 3 process identifier enable. 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC7 Region Descriptor Alternate Access Control n 0x4870 32 read-write n 0x0 0x0 M0PE Bus master 0 process identifier enable 5 1 read-write M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1PE Bus master 1 process identifier enable 11 1 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2PE Bus master 2 process identifier enable 17 1 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3PE Bus master 3 process identifier enable. 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC8 Region Descriptor Alternate Access Control n 0x5090 32 read-write n 0x0 0x0 M0PE Bus master 0 process identifier enable 5 1 read-write M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1PE Bus master 1 process identifier enable 11 1 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2PE Bus master 2 process identifier enable 17 1 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3PE Bus master 3 process identifier enable. 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 RGDAAC9 Region Descriptor Alternate Access Control n 0x58B4 32 read-write n 0x0 0x0 M0PE Bus master 0 process identifier enable 5 1 read-write M0SM Bus master 0 supervisor mode access control 3 2 read-write M0UM Bus master 0 user mode access control 0 3 read-write M1PE Bus master 1 process identifier enable 11 1 read-write M1SM Bus master 1 supervisor mode access control 9 2 read-write M1UM Bus master 1 user mode access control 6 3 read-write M2PE Bus master 2 process identifier enable 17 1 read-write M2SM Bus master 2 supervisor mode access control 15 2 read-write M2UM Bus master 2 user mode access control 12 3 read-write M3PE Bus master 3 process identifier enable. 23 1 read-write 0 Do not include the process identifier in the evaluation #0 1 Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation #1 M3SM Bus master 3 supervisor mode access control 21 2 read-write 00 r/w/x; read, write and execute allowed #00 01 r/x; read and execute allowed, but no write #01 10 r/w; read and write allowed, but no execute #10 11 Same as user mode defined in M3UM #11 M3UM Bus master 3 user mode access control 18 3 read-write 0 An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed. #0 1 Allows the given access type to occur #1 M4RE Bus master 4 read enable. 25 1 read-write 0 Bus master 4 reads terminate with an access error and the read is not performed #0 1 Bus master 4 reads allowed #1 M4WE Bus master 4 write enable 24 1 read-write 0 Bus master 4 writes terminate with an access error and the write is not performed #0 1 Bus master 4 writes allowed #1 M5RE Bus master 5 read enable. 27 1 read-write 0 Bus master 5 reads terminate with an access error and the read is not performed #0 1 Bus master 5 reads allowed #1 M5WE Bus master 5 write enable 26 1 read-write 0 Bus master 5 writes terminate with an access error and the write is not performed #0 1 Bus master 5 writes allowed #1 M6RE Bus master 6 read enable. 29 1 read-write 0 Bus master 6 reads terminate with an access error and the read is not performed #0 1 Bus master 6 reads allowed #1 M6WE Bus master 6 write enable 28 1 read-write 0 Bus master 6 writes terminate with an access error and the write is not performed #0 1 Bus master 6 writes allowed #1 M7RE Bus master 7 read enable. 31 1 read-write 0 Bus master 7 reads terminate with an access error and the read is not performed #0 1 Bus master 7 reads allowed #1 M7WE Bus master 7 write enable 30 1 read-write 0 Bus master 7 writes terminate with an access error and the write is not performed #0 1 Bus master 7 writes allowed #1 NFC NAND flash controller NFC 0x0 0x3F00 0x3C registers n NFC 95 INT_NFC 111 CAR Column address 0x3F08 32 read-write n 0x0 0x0 BYTE1 First byte of column address 0 8 read-write BYTE2 Second byte of column address 8 8 read-write RESERVED no description available 16 16 read-only CFG Flash configuration 0x3F30 32 read-write n 0x0 0x0 AIAD no description available 5 1 read-write 0 Do not auto-increment flash row address #0 1 Auto-increment flash row address #1 AIBN no description available 4 1 read-write 0 Do not auto-increment buffer number #0 1 Auto-increment buffer number #1 BITWIDTH no description available 7 1 read-write 0 8-bit wide flash mode #0 1 16-bit wide flash mode #1 DMAREQ no description available 20 1 read-write 0 Do not transfer sector after ECC done #0 1 After ECC done, transfer sector using DMA #1 ECCAD Byte address in SRAM where ECC status is written. 22 9 read-write ECCMODE no description available 17 3 read-write 000 No correction, ECC bypass #000 001 4-error correction (8 ECC bytes) #001 010 6-error correction (12 ECC bytes) #010 011 8-error correction (15 ECC bytes) #011 100 12-error correction (23 ECC bytes) #100 101 16-error correction (30 ECC bytes) #101 110 24-error correction (45 ECC bytes) #110 111 32-error correction (60 ECC bytes) #111 ECCSRAM no description available 21 1 read-write 0 Do not write ECC status to SRAM #0 1 Write ECC status to SRAM #1 FAST See the "Fast Flash Configuration for EDO" section for more details. 16 1 read-write 0 Slow flash timing. Clock in read data on rising edge of read strobe #0 1 Fast flash timing. Clock in read data a half clock later than rising edge of read strobe #1 IDCNT Number of bytes that are read for the read id command. 13 3 read-write PAGECNT Number of virtual pages (in one physical flash page) to be programmed or read, etc. 0 4 read-write RESERVED no description available 6 1 read-only STOPWERR no description available 31 1 read-write 0 No stop on write error #0 1 Auto-sequencer stops on a write error #1 TIMEOUT no description available 8 5 read-write CMD1 Flash command 1 0x3F00 32 read-write n 0x0 0x0 BYTE2 Second command byte that may be sent to the flash device 24 8 read-write BYTE3 Third command byte that may be sent to the flash device 16 8 read-write RESERVED no description available 0 16 read-only CMD2 Flash command 2 0x3F04 32 read-write n 0x0 0x0 BUFNO Internal buffer number used for this command 1 2 read-write BUSY_START Busy indicator and start command 0 1 read-write 0 During reads, flash controller is idle and it is okay to send next command. During writes, no action. #0 1 During reads, command execution is busy. During writes, start command execution. #1 BYTE1 First command byte that may be sent to the flash device 24 8 read-write CODE User-defined flash operation sequencer 8 16 read-write RESERVED no description available 3 5 read-only DMA1 DMA channel 1 address 0x3F20 32 read-write n 0x0 0x0 ADDRESS DMA channel 1 address. DMA channel 1 address, it is 8-byte aligned. 0 32 read-write DMA2 DMA channel 2 address 0x3F34 32 read-write n 0x0 0x0 ADDRESS DMA channel 2 address. DMA channel 2 address, it is 8-byte aligned. 0 32 read-write DMACFG DMA configuration 0x3F24 32 read-write n 0x0 0x0 ACT1 DMA channel 1 status 1 1 read-write 0 Inactive #0 1 Active, and transfers to memory when triggered #1 ACT2 DMA channel 2 status 0 1 read-write 0 Inactive #0 1 Active, and transfers to memory when triggered #1 COUNT1 Number of bytes to be transferred by DMA channel 1. It should be multiple of 8 bytes. 20 12 read-write COUNT2 Number of bytes to be transferred by DMA channel 2. It should be multiple of 8 bytes. 13 7 read-write OFFSET2 256-byte offset for DMA channel 2. DMA channel 2 transfer starts at this offset count x 256 bytes. For example, if OFFSET2 = 0x2, DMA channel 2 transfer starts at 0x200. 9 4 read-write RESERVED no description available 2 7 read-only ISR Interrupt status 0x3F38 32 read-write n 0x0 0x0 CMDBUSY Command busy 26 1 read-only DMABN DMA buffer number 0 2 read-only DMABUSY DMA engine busy 23 1 read-only DONE Done interrupt 30 1 read-only DONECLR no description available 18 1 read-write DONEEN no description available 21 1 read-write ECCBN ECC buffer number 2 2 read-only ECCBUSY ECC engine busy 24 1 read-only IDLE Command idle interrupt 29 1 read-only IDLECLR no description available 17 1 read-write IDLEEN no description available 20 1 read-write RESBN Residue buffer number 4 2 read-only RESBUSY Residue engine busy 25 1 read-only RESERVED no description available 6 11 read-only RESERVED no description available 28 1 read-only WERR Write error interrupt 31 1 read-only WERRCLR no description available 19 1 read-write WERREN no description available 22 1 read-write WERRNS Write error status 27 1 read-only RAI Row address increment 0x3F14 32 read-write n 0x0 0x0 INC1 Increment for the first byte of row address 0 8 read-write INC2 Increment for the second byte of row address 8 8 read-write INC3 Increment for the third byte of row address 16 8 read-write RESERVED no description available 24 8 read-only RAR Row address 0x3F0C 32 read-write n 0x0 0x0 BYTE1 First byte of row address 0 8 read-write BYTE2 Second byte of row address 8 8 read-write BYTE3 Third byte of row address 16 8 read-write CS0 Chip select 0 enable 28 1 read-write 0 NFC_CE0 is disabled #0 1 NFC_CE0 is enabled #1 CS1 Chip select 1 enable 29 1 read-write 0 NFC_CE1 is disabled #0 1 NFC_CE1 is enabled #1 RB0 Ready/busy 0 enable 24 1 read-write 0 NFC_R/ B 0 is disabled #0 1 NFC_R/ B 0 is enabled #1 RB1 Ready/busy 1 enable 25 1 read-write 0 NFC_R/ B 1 is disabled #0 1 NFC_R/ B 1 is enabled #1 RESERVED no description available 26 2 read-only RESERVED no description available 30 2 read-only RPT Flash command repeat 0x3F10 32 read-write n 0x0 0x0 COUNT 16-bit repeat count 0 16 read-write RESERVED no description available 16 16 read-only SECSZ Sector size 0x3F2C 32 read-write n 0x0 0x0 RESERVED no description available 13 19 read-only SIZE Size in bytes of one elementary transfer unit 0 13 read-write SR1 Flash status 1 0x3F18 32 read-only n 0x0 0x0 ID1 First byte returned by read ID command 24 8 read-only ID2 Second byte returned by read ID command 16 8 read-only ID3 Third byte returned by read ID command 8 8 read-only ID4 Fourth byte returned by read ID command 0 8 read-only SR2 Flash status 2 0x3F1C 32 read-only n 0x0 0x0 ID5 Fifth byte returned by read ID command 24 8 read-only RESERVED no description available 8 16 read-only STATUS1 Byte returned by read status command 0 8 read-only SWAP Cach swap 0x3F28 32 read-write n 0x0 0x0 ADDR1 Lower swap address 17 11 read-write ADDR2 Upper swap address 1 11 read-write RESERVED no description available 0 1 read-only RESERVED no description available 12 5 read-only RESERVED no description available 28 4 read-only NVIC Nested Vectored Interrupt Controller NVIC 0x0 0x0 0xE04 registers n NVICIABR0 Interrupt Active bit Register n 0x200 32 read-write n 0x0 0x0 ACTIVE Interrupt active flags 0 32 read-write NVICIABR1 Interrupt Active bit Register n 0x204 32 read-write n 0x0 0x0 ACTIVE Interrupt active flags 0 32 read-write NVICIABR2 Interrupt Active bit Register n 0x208 32 read-write n 0x0 0x0 ACTIVE Interrupt active flags 0 32 read-write NVICIABR3 Interrupt Active bit Register n 0x20C 32 read-write n 0x0 0x0 ACTIVE Interrupt active flags 0 32 read-write NVICICER0 Interrupt Clear Enable Register n 0x80 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 32 read-write NVICICER1 Interrupt Clear Enable Register n 0x84 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 32 read-write NVICICER2 Interrupt Clear Enable Register n 0x88 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 32 read-write NVICICER3 Interrupt Clear Enable Register n 0x8C 32 read-write n 0x0 0x0 CLRENA Interrupt clear-enable bits 0 32 read-write NVICICPR0 Interrupt Clear Pending Register n 0x180 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 32 read-write NVICICPR1 Interrupt Clear Pending Register n 0x184 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 32 read-write NVICICPR2 Interrupt Clear Pending Register n 0x188 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 32 read-write NVICICPR3 Interrupt Clear Pending Register n 0x18C 32 read-write n 0x0 0x0 CLRPEND Interrupt clear-pending bits 0 32 read-write NVICIP0 Interrupt Priority Register n 0x300 8 read-write n 0x0 0x0 PRI0 Priority of interrupt 0 0 8 read-write NVICIP1 Interrupt Priority Register n 0x301 8 read-write n 0x0 0x0 PRI1 Priority of interrupt 1 0 8 read-write NVICIP10 Interrupt Priority Register n 0x30A 8 read-write n 0x0 0x0 PRI10 Priority of interrupt 10 0 8 read-write NVICIP100 Interrupt Priority Register n 0x364 8 read-write n 0x0 0x0 PRI100 Priority of interrupt 100 0 8 read-write NVICIP101 Interrupt Priority Register n 0x365 8 read-write n 0x0 0x0 PRI101 Priority of interrupt 101 0 8 read-write NVICIP102 Interrupt Priority Register n 0x366 8 read-write n 0x0 0x0 PRI102 Priority of interrupt 102 0 8 read-write NVICIP103 Interrupt Priority Register n 0x367 8 read-write n 0x0 0x0 PRI103 Priority of interrupt 103 0 8 read-write NVICIP104 Interrupt Priority Register n 0x368 8 read-write n 0x0 0x0 PRI104 Priority of interrupt 104 0 8 read-write NVICIP105 Interrupt Priority Register n 0x369 8 read-write n 0x0 0x0 PRI105 Priority of interrupt 105 0 8 read-write NVICIP11 Interrupt Priority Register n 0x30B 8 read-write n 0x0 0x0 PRI11 Priority of interrupt 11 0 8 read-write NVICIP12 Interrupt Priority Register n 0x30C 8 read-write n 0x0 0x0 PRI12 Priority of interrupt 12 0 8 read-write NVICIP13 Interrupt Priority Register n 0x30D 8 read-write n 0x0 0x0 PRI13 Priority of interrupt 13 0 8 read-write NVICIP14 Interrupt Priority Register n 0x30E 8 read-write n 0x0 0x0 PRI14 Priority of interrupt 14 0 8 read-write NVICIP15 Interrupt Priority Register n 0x30F 8 read-write n 0x0 0x0 PRI15 Priority of interrupt 15 0 8 read-write NVICIP16 Interrupt Priority Register n 0x310 8 read-write n 0x0 0x0 PRI16 Priority of interrupt 16 0 8 read-write NVICIP17 Interrupt Priority Register n 0x311 8 read-write n 0x0 0x0 PRI17 Priority of interrupt 17 0 8 read-write NVICIP18 Interrupt Priority Register n 0x312 8 read-write n 0x0 0x0 PRI18 Priority of interrupt 18 0 8 read-write NVICIP19 Interrupt Priority Register n 0x313 8 read-write n 0x0 0x0 PRI19 Priority of interrupt 19 0 8 read-write NVICIP2 Interrupt Priority Register n 0x302 8 read-write n 0x0 0x0 PRI2 Priority of interrupt 2 0 8 read-write NVICIP20 Interrupt Priority Register n 0x314 8 read-write n 0x0 0x0 PRI20 Priority of interrupt 20 0 8 read-write NVICIP21 Interrupt Priority Register n 0x315 8 read-write n 0x0 0x0 PRI21 Priority of interrupt 21 0 8 read-write NVICIP22 Interrupt Priority Register n 0x316 8 read-write n 0x0 0x0 PRI22 Priority of interrupt 22 0 8 read-write NVICIP23 Interrupt Priority Register n 0x317 8 read-write n 0x0 0x0 PRI23 Priority of interrupt 23 0 8 read-write NVICIP24 Interrupt Priority Register n 0x318 8 read-write n 0x0 0x0 PRI24 Priority of interrupt 24 0 8 read-write NVICIP25 Interrupt Priority Register n 0x319 8 read-write n 0x0 0x0 PRI25 Priority of interrupt 25 0 8 read-write NVICIP26 Interrupt Priority Register n 0x31A 8 read-write n 0x0 0x0 PRI26 Priority of interrupt 26 0 8 read-write NVICIP27 Interrupt Priority Register n 0x31B 8 read-write n 0x0 0x0 PRI27 Priority of interrupt 27 0 8 read-write NVICIP28 Interrupt Priority Register n 0x31C 8 read-write n 0x0 0x0 PRI28 Priority of interrupt 28 0 8 read-write NVICIP29 Interrupt Priority Register n 0x31D 8 read-write n 0x0 0x0 PRI29 Priority of interrupt 29 0 8 read-write NVICIP3 Interrupt Priority Register n 0x303 8 read-write n 0x0 0x0 PRI3 Priority of interrupt 3 0 8 read-write NVICIP30 Interrupt Priority Register n 0x31E 8 read-write n 0x0 0x0 PRI30 Priority of interrupt 30 0 8 read-write NVICIP31 Interrupt Priority Register n 0x31F 8 read-write n 0x0 0x0 PRI31 Priority of interrupt 31 0 8 read-write NVICIP32 Interrupt Priority Register n 0x320 8 read-write n 0x0 0x0 PRI32 Priority of interrupt 32 0 8 read-write NVICIP33 Interrupt Priority Register n 0x321 8 read-write n 0x0 0x0 PRI33 Priority of interrupt 33 0 8 read-write NVICIP34 Interrupt Priority Register n 0x322 8 read-write n 0x0 0x0 PRI34 Priority of interrupt 34 0 8 read-write NVICIP35 Interrupt Priority Register n 0x323 8 read-write n 0x0 0x0 PRI35 Priority of interrupt 35 0 8 read-write NVICIP36 Interrupt Priority Register n 0x324 8 read-write n 0x0 0x0 PRI36 Priority of interrupt 36 0 8 read-write NVICIP37 Interrupt Priority Register n 0x325 8 read-write n 0x0 0x0 PRI37 Priority of interrupt 37 0 8 read-write NVICIP38 Interrupt Priority Register n 0x326 8 read-write n 0x0 0x0 PRI38 Priority of interrupt 38 0 8 read-write NVICIP39 Interrupt Priority Register n 0x327 8 read-write n 0x0 0x0 PRI39 Priority of interrupt 39 0 8 read-write NVICIP4 Interrupt Priority Register n 0x304 8 read-write n 0x0 0x0 PRI4 Priority of interrupt 4 0 8 read-write NVICIP40 Interrupt Priority Register n 0x328 8 read-write n 0x0 0x0 PRI40 Priority of interrupt 40 0 8 read-write NVICIP41 Interrupt Priority Register n 0x329 8 read-write n 0x0 0x0 PRI41 Priority of interrupt 41 0 8 read-write NVICIP42 Interrupt Priority Register n 0x32A 8 read-write n 0x0 0x0 PRI42 Priority of interrupt 42 0 8 read-write NVICIP43 Interrupt Priority Register n 0x32B 8 read-write n 0x0 0x0 PRI43 Priority of interrupt 43 0 8 read-write NVICIP44 Interrupt Priority Register n 0x32C 8 read-write n 0x0 0x0 PRI44 Priority of interrupt 44 0 8 read-write NVICIP45 Interrupt Priority Register n 0x32D 8 read-write n 0x0 0x0 PRI45 Priority of interrupt 45 0 8 read-write NVICIP46 Interrupt Priority Register n 0x32E 8 read-write n 0x0 0x0 PRI46 Priority of interrupt 46 0 8 read-write NVICIP47 Interrupt Priority Register n 0x32F 8 read-write n 0x0 0x0 PRI47 Priority of interrupt 47 0 8 read-write NVICIP48 Interrupt Priority Register n 0x330 8 read-write n 0x0 0x0 PRI48 Priority of interrupt 48 0 8 read-write NVICIP49 Interrupt Priority Register n 0x331 8 read-write n 0x0 0x0 PRI49 Priority of interrupt 49 0 8 read-write NVICIP5 Interrupt Priority Register n 0x305 8 read-write n 0x0 0x0 PRI5 Priority of interrupt 5 0 8 read-write NVICIP50 Interrupt Priority Register n 0x332 8 read-write n 0x0 0x0 PRI50 Priority of interrupt 50 0 8 read-write NVICIP51 Interrupt Priority Register n 0x333 8 read-write n 0x0 0x0 PRI51 Priority of interrupt 51 0 8 read-write NVICIP52 Interrupt Priority Register n 0x334 8 read-write n 0x0 0x0 PRI52 Priority of interrupt 52 0 8 read-write NVICIP53 Interrupt Priority Register n 0x335 8 read-write n 0x0 0x0 PRI53 Priority of interrupt 53 0 8 read-write NVICIP54 Interrupt Priority Register n 0x336 8 read-write n 0x0 0x0 PRI54 Priority of interrupt 54 0 8 read-write NVICIP55 Interrupt Priority Register n 0x337 8 read-write n 0x0 0x0 PRI55 Priority of interrupt 55 0 8 read-write NVICIP56 Interrupt Priority Register n 0x338 8 read-write n 0x0 0x0 PRI56 Priority of interrupt 56 0 8 read-write NVICIP57 Interrupt Priority Register n 0x339 8 read-write n 0x0 0x0 PRI57 Priority of interrupt 57 0 8 read-write NVICIP58 Interrupt Priority Register n 0x33A 8 read-write n 0x0 0x0 PRI58 Priority of interrupt 58 0 8 read-write NVICIP59 Interrupt Priority Register n 0x33B 8 read-write n 0x0 0x0 PRI59 Priority of interrupt 59 0 8 read-write NVICIP6 Interrupt Priority Register n 0x306 8 read-write n 0x0 0x0 PRI6 Priority of interrupt 6 0 8 read-write NVICIP60 Interrupt Priority Register n 0x33C 8 read-write n 0x0 0x0 PRI60 Priority of interrupt 60 0 8 read-write NVICIP61 Interrupt Priority Register n 0x33D 8 read-write n 0x0 0x0 PRI61 Priority of interrupt 61 0 8 read-write NVICIP62 Interrupt Priority Register n 0x33E 8 read-write n 0x0 0x0 PRI62 Priority of interrupt 62 0 8 read-write NVICIP63 Interrupt Priority Register n 0x33F 8 read-write n 0x0 0x0 PRI63 Priority of interrupt 63 0 8 read-write NVICIP64 Interrupt Priority Register n 0x340 8 read-write n 0x0 0x0 PRI64 Priority of interrupt 64 0 8 read-write NVICIP65 Interrupt Priority Register n 0x341 8 read-write n 0x0 0x0 PRI65 Priority of interrupt 65 0 8 read-write NVICIP66 Interrupt Priority Register n 0x342 8 read-write n 0x0 0x0 PRI66 Priority of interrupt 66 0 8 read-write NVICIP67 Interrupt Priority Register n 0x343 8 read-write n 0x0 0x0 PRI67 Priority of interrupt 67 0 8 read-write NVICIP68 Interrupt Priority Register n 0x344 8 read-write n 0x0 0x0 PRI68 Priority of interrupt 68 0 8 read-write NVICIP69 Interrupt Priority Register n 0x345 8 read-write n 0x0 0x0 PRI69 Priority of interrupt 69 0 8 read-write NVICIP7 Interrupt Priority Register n 0x307 8 read-write n 0x0 0x0 PRI7 Priority of interrupt 7 0 8 read-write NVICIP70 Interrupt Priority Register n 0x346 8 read-write n 0x0 0x0 PRI70 Priority of interrupt 70 0 8 read-write NVICIP71 Interrupt Priority Register n 0x347 8 read-write n 0x0 0x0 PRI71 Priority of interrupt 71 0 8 read-write NVICIP72 Interrupt Priority Register n 0x348 8 read-write n 0x0 0x0 PRI72 Priority of interrupt 72 0 8 read-write NVICIP73 Interrupt Priority Register n 0x349 8 read-write n 0x0 0x0 PRI73 Priority of interrupt 73 0 8 read-write NVICIP74 Interrupt Priority Register n 0x34A 8 read-write n 0x0 0x0 PRI74 Priority of interrupt 74 0 8 read-write NVICIP75 Interrupt Priority Register n 0x34B 8 read-write n 0x0 0x0 PRI75 Priority of interrupt 75 0 8 read-write NVICIP76 Interrupt Priority Register n 0x34C 8 read-write n 0x0 0x0 PRI76 Priority of interrupt 76 0 8 read-write NVICIP77 Interrupt Priority Register n 0x34D 8 read-write n 0x0 0x0 PRI77 Priority of interrupt 77 0 8 read-write NVICIP78 Interrupt Priority Register n 0x34E 8 read-write n 0x0 0x0 PRI78 Priority of interrupt 78 0 8 read-write NVICIP79 Interrupt Priority Register n 0x34F 8 read-write n 0x0 0x0 PRI79 Priority of interrupt 79 0 8 read-write NVICIP8 Interrupt Priority Register n 0x308 8 read-write n 0x0 0x0 PRI8 Priority of interrupt 8 0 8 read-write NVICIP80 Interrupt Priority Register n 0x350 8 read-write n 0x0 0x0 PRI80 Priority of interrupt 80 0 8 read-write NVICIP81 Interrupt Priority Register n 0x351 8 read-write n 0x0 0x0 PRI81 Priority of interrupt 81 0 8 read-write NVICIP82 Interrupt Priority Register n 0x352 8 read-write n 0x0 0x0 PRI82 Priority of interrupt 82 0 8 read-write NVICIP83 Interrupt Priority Register n 0x353 8 read-write n 0x0 0x0 PRI83 Priority of interrupt 83 0 8 read-write NVICIP84 Interrupt Priority Register n 0x354 8 read-write n 0x0 0x0 PRI84 Priority of interrupt 84 0 8 read-write NVICIP85 Interrupt Priority Register n 0x355 8 read-write n 0x0 0x0 PRI85 Priority of interrupt 85 0 8 read-write NVICIP86 Interrupt Priority Register n 0x356 8 read-write n 0x0 0x0 PRI86 Priority of interrupt 86 0 8 read-write NVICIP87 Interrupt Priority Register n 0x357 8 read-write n 0x0 0x0 PRI87 Priority of interrupt 87 0 8 read-write NVICIP88 Interrupt Priority Register n 0x358 8 read-write n 0x0 0x0 PRI88 Priority of interrupt 88 0 8 read-write NVICIP89 Interrupt Priority Register n 0x359 8 read-write n 0x0 0x0 PRI89 Priority of interrupt 89 0 8 read-write NVICIP9 Interrupt Priority Register n 0x309 8 read-write n 0x0 0x0 PRI9 Priority of interrupt 9 0 8 read-write NVICIP90 Interrupt Priority Register n 0x35A 8 read-write n 0x0 0x0 PRI90 Priority of interrupt 90 0 8 read-write NVICIP91 Interrupt Priority Register n 0x35B 8 read-write n 0x0 0x0 PRI91 Priority of interrupt 91 0 8 read-write NVICIP92 Interrupt Priority Register n 0x35C 8 read-write n 0x0 0x0 PRI92 Priority of interrupt 92 0 8 read-write NVICIP93 Interrupt Priority Register n 0x35D 8 read-write n 0x0 0x0 PRI93 Priority of interrupt 93 0 8 read-write NVICIP94 Interrupt Priority Register n 0x35E 8 read-write n 0x0 0x0 PRI94 Priority of interrupt 94 0 8 read-write NVICIP95 Interrupt Priority Register n 0x35F 8 read-write n 0x0 0x0 PRI95 Priority of interrupt 95 0 8 read-write NVICIP96 Interrupt Priority Register n 0x360 8 read-write n 0x0 0x0 PRI96 Priority of interrupt 96 0 8 read-write NVICIP97 Interrupt Priority Register n 0x361 8 read-write n 0x0 0x0 PRI97 Priority of interrupt 97 0 8 read-write NVICIP98 Interrupt Priority Register n 0x362 8 read-write n 0x0 0x0 PRI98 Priority of interrupt 98 0 8 read-write NVICIP99 Interrupt Priority Register n 0x363 8 read-write n 0x0 0x0 PRI99 Priority of interrupt 99 0 8 read-write NVICISER0 Interrupt Set Enable Register n 0x0 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 32 read-write NVICISER1 Interrupt Set Enable Register n 0x4 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 32 read-write NVICISER2 Interrupt Set Enable Register n 0x8 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 32 read-write NVICISER3 Interrupt Set Enable Register n 0xC 32 read-write n 0x0 0x0 SETENA Interrupt set enable bits 0 32 read-write NVICISPR0 Interrupt Set Pending Register n 0x100 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 32 read-write NVICISPR1 Interrupt Set Pending Register n 0x104 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 32 read-write NVICISPR2 Interrupt Set Pending Register n 0x108 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 32 read-write NVICISPR3 Interrupt Set Pending Register n 0x10C 32 read-write n 0x0 0x0 SETPEND Interrupt set-pending bits 0 32 read-write NVICSTIR Software Trigger Interrupt Register 0xE00 32 read-write n 0x0 0x0 INTID Interrupt ID of the interrupt to trigger, in the range 0-239. For example, a value of 0x03 specifies interrupt IRQ3. 0 9 read-write RESERVED no description available 30 1 read-write RESERVED no description available 10 1 read-write RESERVED no description available 11 1 read-write RESERVED no description available 12 1 read-write RESERVED no description available 13 1 read-write RESERVED no description available 14 1 read-write RESERVED no description available 15 1 read-write RESERVED no description available 16 1 read-write RESERVED no description available 17 1 read-write RESERVED no description available 18 1 read-write RESERVED no description available 19 1 read-write RESERVED no description available 20 1 read-write RESERVED no description available 21 1 read-write RESERVED no description available 22 1 read-write RESERVED no description available 23 1 read-write RESERVED no description available 24 1 read-write RESERVED no description available 25 1 read-write RESERVED no description available 26 1 read-write RESERVED no description available 27 1 read-write RESERVED no description available 28 1 read-write RESERVED no description available 29 1 read-write RESERVED no description available 30 1 read-write RESERVED no description available 31 1 read-write OSC0 Oscillator OSC 0x0 0x0 0x1 registers n CR OSC Control Register 0x0 8 read-write n 0x0 0x0 ERCLKEN External Reference Enable 7 1 read-write 0 External reference clock is inactive. #0 1 External reference clock is enabled. #1 EREFSTEN External Reference Stop Enable 5 1 read-write 0 External reference clock is disabled in Stop mode. #0 1 External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode. #1 RESERVED no description available 4 1 read-only RESERVED no description available 6 1 read-only SC16P Oscillator 16 pF Capacitor Load Configure 0 1 read-write 0 Disable the selection. #0 1 Add 16 pF capacitor to the oscillator load. #1 SC2P Oscillator 2 pF Capacitor Load Configure 3 1 read-write 0 Disable the selection. #0 1 Add 2 pF capacitor to the oscillator load. #1 SC4P Oscillator 4 pF Capacitor Load Configure 2 1 read-write 0 Disable the selection. #0 1 Add 4 pF capacitor to the oscillator load. #1 SC8P Oscillator 8 pF Capacitor Load Configure 1 1 read-write 0 Disable the selection. #0 1 Add 8 pF capacitor to the oscillator load. #1 OSC1 Oscillator OSC 0x0 0x0 0x1 registers n CR OSC Control Register 0x0 8 read-write n 0x0 0x0 ERCLKEN External Reference Enable 7 1 read-write 0 External reference clock is inactive. #0 1 External reference clock is enabled. #1 EREFSTEN External Reference Stop Enable 5 1 read-write 0 External reference clock is disabled in Stop mode. #0 1 External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode. #1 RESERVED no description available 4 1 read-only RESERVED no description available 6 1 read-only SC16P Oscillator 16 pF Capacitor Load Configure 0 1 read-write 0 Disable the selection. #0 1 Add 16 pF capacitor to the oscillator load. #1 SC2P Oscillator 2 pF Capacitor Load Configure 3 1 read-write 0 Disable the selection. #0 1 Add 2 pF capacitor to the oscillator load. #1 SC4P Oscillator 4 pF Capacitor Load Configure 2 1 read-write 0 Disable the selection. #0 1 Add 4 pF capacitor to the oscillator load. #1 SC8P Oscillator 8 pF Capacitor Load Configure 1 1 read-write 0 Disable the selection. #0 1 Add 8 pF capacitor to the oscillator load. #1 PDB0 Programmable Delay Block PDB0 0x0 0x0 0x1A4 registers n PDB0 72 INT_PDB0 88 CH0C1 Channel n Control Register 1 0x20 32 read-write n 0x0 0x0 BB PDB Channel Pre-Trigger Back-to-Back Operation Enable 16 8 read-write 0 PDB channel's corresponding pre-trigger back-to-back operation disabled. #0 1 PDB channel's corresponding pre-trigger back-to-back operation enabled. #1 EN PDB Channel Pre-Trigger Enable 0 8 read-write 0 PDB channel's corresponding pre-trigger disabled. #0 1 PDB channel's corresponding pre-trigger enabled. #1 RESERVED no description available 24 8 read-only TOS PDB Channel Pre-Trigger Output Select 8 8 read-write 0 PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. #0 1 PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register plus one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1. #1 CH0DLY0 Channel n Delay 0 Register 0x30 32 read-write n 0x0 0x0 DLY PDB Channel Delay 0 16 read-write RESERVED no description available 16 16 read-only CH0DLY1 Channel n Delay 1 Register 0x38 32 read-write n 0x0 0x0 DLY PDB Channel Delay 0 16 read-write RESERVED no description available 16 16 read-only CH0S Channel n Status Register 0x28 32 read-write n 0x0 0x0 CF PDB Channel Flags 16 8 read-write ERR PDB Channel Sequence Error Flags 0 8 read-write 0 Sequence error not detected on PDB channel's corresponding pre-trigger. #0 1 Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 1's to clear the sequence error flags. #1 RESERVED no description available 8 8 read-only RESERVED no description available 24 8 read-only CH1C1 Channel n Control Register 1 0x58 32 read-write n 0x0 0x0 BB PDB Channel Pre-Trigger Back-to-Back Operation Enable 16 8 read-write 0 PDB channel's corresponding pre-trigger back-to-back operation disabled. #0 1 PDB channel's corresponding pre-trigger back-to-back operation enabled. #1 EN PDB Channel Pre-Trigger Enable 0 8 read-write 0 PDB channel's corresponding pre-trigger disabled. #0 1 PDB channel's corresponding pre-trigger enabled. #1 RESERVED no description available 24 8 read-only TOS PDB Channel Pre-Trigger Output Select 8 8 read-write 0 PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. #0 1 PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register plus one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1. #1 CH1DLY0 Channel n Delay 0 Register 0x70 32 read-write n 0x0 0x0 DLY PDB Channel Delay 0 16 read-write RESERVED no description available 16 16 read-only CH1DLY1 Channel n Delay 1 Register 0x7C 32 read-write n 0x0 0x0 DLY PDB Channel Delay 0 16 read-write RESERVED no description available 16 16 read-only CH1S Channel n Status Register 0x64 32 read-write n 0x0 0x0 CF PDB Channel Flags 16 8 read-write ERR PDB Channel Sequence Error Flags 0 8 read-write 0 Sequence error not detected on PDB channel's corresponding pre-trigger. #0 1 Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 1's to clear the sequence error flags. #1 RESERVED no description available 8 8 read-only RESERVED no description available 24 8 read-only CH2C1 Channel n Control Register 1 0xB8 32 read-write n 0x0 0x0 BB PDB Channel Pre-Trigger Back-to-Back Operation Enable 16 8 read-write 0 PDB channel's corresponding pre-trigger back-to-back operation disabled. #0 1 PDB channel's corresponding pre-trigger back-to-back operation enabled. #1 EN PDB Channel Pre-Trigger Enable 0 8 read-write 0 PDB channel's corresponding pre-trigger disabled. #0 1 PDB channel's corresponding pre-trigger enabled. #1 RESERVED no description available 24 8 read-only TOS PDB Channel Pre-Trigger Output Select 8 8 read-write 0 PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. #0 1 PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register plus one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1. #1 CH2DLY0 Channel n Delay 0 Register 0xD8 32 read-write n 0x0 0x0 DLY PDB Channel Delay 0 16 read-write RESERVED no description available 16 16 read-only CH2DLY1 Channel n Delay 1 Register 0xE8 32 read-write n 0x0 0x0 DLY PDB Channel Delay 0 16 read-write RESERVED no description available 16 16 read-only CH2S Channel n Status Register 0xC8 32 read-write n 0x0 0x0 CF PDB Channel Flags 16 8 read-write ERR PDB Channel Sequence Error Flags 0 8 read-write 0 Sequence error not detected on PDB channel's corresponding pre-trigger. #0 1 Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 1's to clear the sequence error flags. #1 RESERVED no description available 8 8 read-only RESERVED no description available 24 8 read-only CH3C1 Channel n Control Register 1 0x140 32 read-write n 0x0 0x0 BB PDB Channel Pre-Trigger Back-to-Back Operation Enable 16 8 read-write 0 PDB channel's corresponding pre-trigger back-to-back operation disabled. #0 1 PDB channel's corresponding pre-trigger back-to-back operation enabled. #1 EN PDB Channel Pre-Trigger Enable 0 8 read-write 0 PDB channel's corresponding pre-trigger disabled. #0 1 PDB channel's corresponding pre-trigger enabled. #1 RESERVED no description available 24 8 read-only TOS PDB Channel Pre-Trigger Output Select 8 8 read-write 0 PDB channel's corresponding pre-trigger is in bypassed mode. The pre-trigger asserts one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. #0 1 PDB channel's corresponding pre-trigger asserts when the counter reaches the channel delay register plus one peripheral clock cycle after a rising edge is detected on selected trigger input source or software trigger is selected and SETRIG is written with 1. #1 CH3DLY0 Channel n Delay 0 Register 0x168 32 read-write n 0x0 0x0 DLY PDB Channel Delay 0 16 read-write RESERVED no description available 16 16 read-only CH3DLY1 Channel n Delay 1 Register 0x17C 32 read-write n 0x0 0x0 DLY PDB Channel Delay 0 16 read-write RESERVED no description available 16 16 read-only CH3S Channel n Status Register 0x154 32 read-write n 0x0 0x0 CF PDB Channel Flags 16 8 read-write ERR PDB Channel Sequence Error Flags 0 8 read-write 0 Sequence error not detected on PDB channel's corresponding pre-trigger. #0 1 Sequence error detected on PDB channel's corresponding pre-trigger. ADCn block can be triggered for a conversion by one pre-trigger from PDB channel n. When one conversion, which is triggered by one of the pre-triggers from PDB channel n, is in progress, new trigger from PDB channel's corresponding pre-trigger m cannot be accepted by ADCn, and ERR[m] is set. Writing 1's to clear the sequence error flags. #1 RESERVED no description available 8 8 read-only RESERVED no description available 24 8 read-only CNT Counter Register 0x8 32 read-only n 0x0 0x0 CNT PDB Counter 0 16 read-only RESERVED no description available 16 16 read-only DACINT0 DAC Interval n Register 0x2A8 32 read-write n 0x0 0x0 INT DAC Interval 0 16 read-write RESERVED no description available 16 16 read-only DACINT1 DAC Interval n Register 0x404 32 read-write n 0x0 0x0 INT DAC Interval 0 16 read-write RESERVED no description available 16 16 read-only DACINTC0 DAC Interval Trigger n Control Register 0x2A0 32 read-write n 0x0 0x0 EXT DAC External Trigger Input Enable 1 1 read-write 0 DAC external trigger input disabled. DAC interval counter is reset and started counting when a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. #0 1 DAC external trigger input enabled. DAC interval counter is bypassed and DAC external trigger input triggers the DAC interval trigger. #1 RESERVED no description available 2 30 read-only TOE DAC Interval Trigger Enable 0 1 read-write 0 DAC interval trigger disabled. #0 1 DAC interval trigger enabled. #1 DACINTC1 DAC Interval Trigger n Control Register 0x3F8 32 read-write n 0x0 0x0 EXT DAC External Trigger Input Enable 1 1 read-write 0 DAC external trigger input disabled. DAC interval counter is reset and started counting when a rising edge is detected on selected trigger input source or software trigger is selected and SWTRIG is written with 1. #0 1 DAC external trigger input enabled. DAC interval counter is bypassed and DAC external trigger input triggers the DAC interval trigger. #1 RESERVED no description available 2 30 read-only TOE DAC Interval Trigger Enable 0 1 read-write 0 DAC interval trigger disabled. #0 1 DAC interval trigger enabled. #1 IDLY Interrupt Delay Register 0xC 32 read-write n 0x0 0x0 IDLY PDB Interrupt Delay 0 16 read-write RESERVED no description available 16 16 read-only MOD Modulus Register 0x4 32 read-write n 0x0 0x0 MOD PDB Modulus. 0 16 read-write RESERVED no description available 16 16 read-only PO0DLY Pulse-Out n Delay Register 0x328 32 read-write n 0x0 0x0 DLY1 PDB Pulse-Out Delay 1 16 16 read-write DLY2 PDB Pulse-Out Delay 2 0 16 read-write PO1DLY Pulse-Out n Delay Register 0x4C0 32 read-write n 0x0 0x0 DLY1 PDB Pulse-Out Delay 1 16 16 read-write DLY2 PDB Pulse-Out Delay 2 0 16 read-write PO2DLY Pulse-Out n Delay Register 0x65C 32 read-write n 0x0 0x0 DLY1 PDB Pulse-Out Delay 1 16 16 read-write DLY2 PDB Pulse-Out Delay 2 0 16 read-write PO3DLY Pulse-Out n Delay Register 0x7FC 32 read-write n 0x0 0x0 DLY1 PDB Pulse-Out Delay 1 16 16 read-write DLY2 PDB Pulse-Out Delay 2 0 16 read-write POEN Pulse-Out n Enable Register 0x190 32 read-write n 0x0 0x0 POEN PDB Pulse-Out Enable 0 8 read-write 0 PDB Pulse-Out disabled #0 1 PDB Pulse-Out enabled #1 RESERVED no description available 8 24 read-only SC Status and Control Register 0x0 32 read-write n 0x0 0x0 CONT Continuous Mode Enable 1 1 read-write 0 PDB operation in One-Shot mode #0 1 PDB operation in Continuous mode #1 DMAEN DMA Enable 15 1 read-write 0 DMA disabled #0 1 DMA enabled #1 LDMOD Load Mode Select 18 2 read-write 00 The internal registers are loaded with the values from their buffers immediately after 1 is written to LDOK. #00 01 The internal registers are loaded with the values from their buffers when the PDB counter reaches the MOD register value after 1 is written to LDOK. #01 10 The internal registers are loaded with the values from their buffers when a trigger input event is detected after 1 is written to LDOK. #10 11 The internal registers are loaded with the values from their buffers when either the PDB counter reaches the MOD register value or a trigger input event is detected, after 1 is written to LDOK. #11 LDOK Load OK 0 1 read-write MULT Multiplication Factor Select for Prescaler 2 2 read-write 00 Multiplication factor is 1 #00 01 Multiplication factor is 10 #01 10 Multiplication factor is 20 #10 11 Multiplication factor is 40 #11 PDBEIE PDB Sequence Error Interrupt Enable 17 1 read-write 0 PDB sequence error interrupt disabled. #0 1 PDB sequence error interrupt enabled. #1 PDBEN PDB Enable 7 1 read-write 0 PDB disabled. Counter is off. #0 1 PDB enabled #1 PDBIE PDB Interrupt Enable. 5 1 read-write 0 PDB interrupt disabled #0 1 PDB interrupt enabled #1 PDBIF PDB Interrupt Flag 6 1 read-write PRESCALER Prescaler Divider Select 12 3 read-write 000 Counting uses the peripheral clock divided by multiplication factor selected by MULT. #000 001 Counting uses the peripheral clock divided by twice of the multiplication factor selected by MULT. #001 010 Counting uses the peripheral clock divided by four times of the multiplication factor selected by MULT. #010 011 Counting uses the peripheral clock divided by eight times of the multiplication factor selected by MULT. #011 100 Counting uses the peripheral clock divided by 16 times of the multiplication factor selected by MULT. #100 101 Counting uses the peripheral clock divided by 32 times of the multiplication factor selected by MULT. #101 110 Counting uses the peripheral clock divided by 64 times of the multiplication factor selected by MULT. #110 111 Counting uses the peripheral clock divided by 128 times of the multiplication factor selected by MULT. #111 RESERVED no description available 4 1 read-only RESERVED no description available 20 12 read-only SWTRIG Software Trigger 16 1 write-only TRGSEL Trigger Input Source Select 8 4 read-write 0000 Trigger-In 0 is selected #0000 0001 Trigger-In 1 is selected #0001 0010 Trigger-In 2 is selected #0010 0011 Trigger-In 3 is selected #0011 0100 Trigger-In 4 is selected #0100 0101 Trigger-In 5 is selected #0101 0110 Trigger-In 6 is selected #0110 0111 Trigger-In 7 is selected #0111 1000 Trigger-In 8 is selected #1000 1001 Trigger-In 9 is selected #1001 1010 Trigger-In 10 is selected #1010 1011 Trigger-In 11 is selected #1011 1100 Trigger-In 12 is selected #1100 1101 Trigger-In 13 is selected #1101 1110 Trigger-In 14 is selected #1110 1111 Software trigger is selected #1111 PIT Periodic Interrupt Timer PIT 0x0 0x0 0x140 registers n PIT0 68 PIT1 69 PIT2 70 PIT3 71 INT_PIT0 84 INT_PIT1 85 INT_PIT2 86 INT_PIT3 87 CVAL0 Current Timer Value Register 0x208 32 read-only n 0x0 0x0 TVL Current Timer Value 0 32 read-only CVAL1 Current Timer Value Register 0x31C 32 read-only n 0x0 0x0 TVL Current Timer Value 0 32 read-only CVAL2 Current Timer Value Register 0x440 32 read-only n 0x0 0x0 TVL Current Timer Value 0 32 read-only CVAL3 Current Timer Value Register 0x574 32 read-only n 0x0 0x0 TVL Current Timer Value 0 32 read-only LDVAL0 Timer Load Value Register 0x200 32 read-write n 0x0 0x0 TSV Timer Start Value Bits 0 32 read-write LDVAL1 Timer Load Value Register 0x310 32 read-write n 0x0 0x0 TSV Timer Start Value Bits 0 32 read-write LDVAL2 Timer Load Value Register 0x430 32 read-write n 0x0 0x0 TSV Timer Start Value Bits 0 32 read-write LDVAL3 Timer Load Value Register 0x560 32 read-write n 0x0 0x0 TSV Timer Start Value Bits 0 32 read-write MCR PIT Module Control Register 0x0 32 read-write n 0x0 0x0 FRZ Freeze 0 1 read-write 0 Timers continue to run in debug mode. #0 1 Timers are stopped in debug mode. #1 MDIS Module Disable 1 1 read-write 0 Clock for PIT Timers is enabled. #0 1 Clock for PIT Timers is disabled. #1 RESERVED no description available 2 30 read-only TCTRL0 Timer Control Register 0x210 32 read-write n 0x0 0x0 RESERVED no description available 2 30 read-only TEN Timer Enable Bit. 0 1 read-write 0 Timer n is disabled. #0 1 Timer n is active. #1 TIE Timer Interrupt Enable Bit. 1 1 read-write 0 Interrupt requests from Timer n are disabled. #0 1 Interrupt will be requested whenever TIF is set. #1 TCTRL1 Timer Control Register 0x328 32 read-write n 0x0 0x0 RESERVED no description available 2 30 read-only TEN Timer Enable Bit. 0 1 read-write 0 Timer n is disabled. #0 1 Timer n is active. #1 TIE Timer Interrupt Enable Bit. 1 1 read-write 0 Interrupt requests from Timer n are disabled. #0 1 Interrupt will be requested whenever TIF is set. #1 TCTRL2 Timer Control Register 0x450 32 read-write n 0x0 0x0 RESERVED no description available 2 30 read-only TEN Timer Enable Bit. 0 1 read-write 0 Timer n is disabled. #0 1 Timer n is active. #1 TIE Timer Interrupt Enable Bit. 1 1 read-write 0 Interrupt requests from Timer n are disabled. #0 1 Interrupt will be requested whenever TIF is set. #1 TCTRL3 Timer Control Register 0x588 32 read-write n 0x0 0x0 RESERVED no description available 2 30 read-only TEN Timer Enable Bit. 0 1 read-write 0 Timer n is disabled. #0 1 Timer n is active. #1 TIE Timer Interrupt Enable Bit. 1 1 read-write 0 Interrupt requests from Timer n are disabled. #0 1 Interrupt will be requested whenever TIF is set. #1 TFLG0 Timer Flag Register 0x218 32 read-write n 0x0 0x0 RESERVED no description available 1 31 read-only TIF Timer Interrupt Flag. 0 1 read-write 0 Time-out has not yet occurred. #0 1 Time-out has occurred. #1 TFLG1 Timer Flag Register 0x334 32 read-write n 0x0 0x0 RESERVED no description available 1 31 read-only TIF Timer Interrupt Flag. 0 1 read-write 0 Time-out has not yet occurred. #0 1 Time-out has occurred. #1 TFLG2 Timer Flag Register 0x460 32 read-write n 0x0 0x0 RESERVED no description available 1 31 read-only TIF Timer Interrupt Flag. 0 1 read-write 0 Time-out has not yet occurred. #0 1 Time-out has occurred. #1 TFLG3 Timer Flag Register 0x59C 32 read-write n 0x0 0x0 RESERVED no description available 1 31 read-only TIF Timer Interrupt Flag. 0 1 read-write 0 Time-out has not yet occurred. #0 1 Time-out has occurred. #1 PMC Power Management Controller PMC 0x0 0x0 0x3 registers n LVD_LVW 20 INT_LVD_LVW 36 LVDSC1 Low Voltage Detect Status and Control 1 Register 0x0 8 read-write n 0x0 0x0 LVDACK Low-Voltage Detect Acknowledge 6 1 write-only LVDF Low-Voltage Detect Flag 7 1 read-only 0 Low-voltage event not detected #0 1 Low-voltage event detected #1 LVDIE Low-Voltage Detect Interrupt Enable 5 1 read-write 0 Hardware interrupt disabled (use polling) #0 1 Request a hardware interrupt when LVDF = 1. #1 LVDRE Low-Voltage Detect Reset Enable 4 1 read-write 0 LVDF does not generate hardware resets #0 1 Force an MCU reset when LVDF = 1 #1 LVDV Low-Voltage Detect Voltage Select 0 2 read-write 00 Low trip point selected (V LVD = V LVDL ) #00 01 High trip point selected (V LVD = V LVDH ) #01 10 Reserved #10 11 Reserved #11 RESERVED no description available 2 2 read-only LVDSC2 Low Voltage Detect Status and Control 2 Register 0x1 8 read-write n 0x0 0x0 LVWACK Low-Voltage Warning Acknowledge 6 1 write-only LVWF Low-Voltage Warning Flag 7 1 read-only 0 Low-voltage warning event not detected #0 1 Low-voltage warning event detected #1 LVWIE Low-Voltage Warning Interrupt Enable 5 1 read-write 0 Hardware interrupt disabled (use polling) #0 1 Request a hardware interrupt when LVWF = 1. #1 LVWV Low-Voltage Warning Voltage Select 0 2 read-write 00 Low trip point selected (V LVW = V LVW1 ) #00 01 Mid 1 trip point selected (V LVW = V LVW2 ) #01 10 Mid 2 trip point selected (V LVW = V LVW3 ) #10 11 High trip point selected (V LVW = V LVW4 ) #11 RESERVED no description available 2 3 read-only REGSC Regulator Status and Control Register 0x2 8 read-write n 0x0 0x0 ACKISO Acknowledge Isolation 3 1 read-write 0 Peripherals and I/O pads are in normal run state #0 1 Certain peripherals and I/O pads are in an isolated and latched state #1 BGBE Bandgap Buffer Enable 0 1 read-write 0 Bandgap buffer not enabled #0 1 Bandgap buffer enabled #1 REGONS Regulator in Run Regulation Status 2 1 read-only 0 Regulator is in stop regulation or in transition to/from it #0 1 Regulator is in run regulation #1 RESERVED no description available 1 1 read-write RESERVED no description available 4 4 read-only PORTA Pin Control and Interrupts PORT 0x0 0x0 0xCC registers n PORTA 87 DFCR Digital Filter Clock Register 0xC4 32 read-write n 0x0 0x0 CS Clock Source 0 1 read-write 0 Digital Filters are clocked by the bus clock. #0 1 Digital Filters are clocked by the 1 kHz LPO clock. #1 RESERVED no description available 1 31 read-only DFER Digital Filter Enable Register 0xC0 32 read-write n 0x0 0x0 DFE Digital Filter Enable 0 32 read-write 0 Digital Filter is disabled on the corresponding pin and output of the digital filter is reset to zero.Each bit in the field enables the digital filter of the same number as the bit. #0 1 Digital Filter is enabled on the corresponding pin, provided pin is configured as a digital input. #1 DFWR Digital Filter Width Register 0xC8 32 read-write n 0x0 0x0 FILT Filter Length 0 5 read-write RESERVED no description available 5 27 read-only GPCHR Global Pin Control High Register 0x84 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only GPCLR Global Pin Control Low Register 0x80 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only ISFR Interrupt Status Flag Register 0xA0 32 read-write n 0x0 0x0 ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to the flag. If configured for a level sensitive interrupt and the pin remains asserted then the flag will set again immediately after it is cleared. #1 PCR0 Pin Control Register n 0x0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR1 Pin Control Register n 0x4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR10 Pin Control Register n 0xDC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR11 Pin Control Register n 0x108 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR12 Pin Control Register n 0x138 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR13 Pin Control Register n 0x16C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR14 Pin Control Register n 0x1A4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR15 Pin Control Register n 0x1E0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR16 Pin Control Register n 0x220 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR17 Pin Control Register n 0x264 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR18 Pin Control Register n 0x2AC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR19 Pin Control Register n 0x2F8 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR2 Pin Control Register n 0xC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR20 Pin Control Register n 0x348 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR21 Pin Control Register n 0x39C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR22 Pin Control Register n 0x3F4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR23 Pin Control Register n 0x450 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR24 Pin Control Register n 0x4B0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR25 Pin Control Register n 0x514 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR26 Pin Control Register n 0x57C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR27 Pin Control Register n 0x5E8 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR28 Pin Control Register n 0x658 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR29 Pin Control Register n 0x6CC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR3 Pin Control Register n 0x18 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR30 Pin Control Register n 0x744 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR31 Pin Control Register n 0x7C0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR4 Pin Control Register n 0x28 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR5 Pin Control Register n 0x3C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR6 Pin Control Register n 0x54 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR7 Pin Control Register n 0x70 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR8 Pin Control Register n 0x90 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR9 Pin Control Register n 0xB4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PORTB Pin Control and Interrupts PORT 0x0 0x0 0xCC registers n PORTB 88 DFCR Digital Filter Clock Register 0xC4 32 read-write n 0x0 0x0 CS Clock Source 0 1 read-write 0 Digital Filters are clocked by the bus clock. #0 1 Digital Filters are clocked by the 1 kHz LPO clock. #1 RESERVED no description available 1 31 read-only DFER Digital Filter Enable Register 0xC0 32 read-write n 0x0 0x0 DFE Digital Filter Enable 0 32 read-write 0 Digital Filter is disabled on the corresponding pin and output of the digital filter is reset to zero.Each bit in the field enables the digital filter of the same number as the bit. #0 1 Digital Filter is enabled on the corresponding pin, provided pin is configured as a digital input. #1 DFWR Digital Filter Width Register 0xC8 32 read-write n 0x0 0x0 FILT Filter Length 0 5 read-write RESERVED no description available 5 27 read-only GPCHR Global Pin Control High Register 0x84 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only GPCLR Global Pin Control Low Register 0x80 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only ISFR Interrupt Status Flag Register 0xA0 32 read-write n 0x0 0x0 ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to the flag. If configured for a level sensitive interrupt and the pin remains asserted then the flag will set again immediately after it is cleared. #1 PCR0 Pin Control Register n 0x0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR1 Pin Control Register n 0x4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR10 Pin Control Register n 0xDC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR11 Pin Control Register n 0x108 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR12 Pin Control Register n 0x138 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR13 Pin Control Register n 0x16C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR14 Pin Control Register n 0x1A4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR15 Pin Control Register n 0x1E0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR16 Pin Control Register n 0x220 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR17 Pin Control Register n 0x264 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR18 Pin Control Register n 0x2AC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR19 Pin Control Register n 0x2F8 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR2 Pin Control Register n 0xC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR20 Pin Control Register n 0x348 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR21 Pin Control Register n 0x39C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR22 Pin Control Register n 0x3F4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR23 Pin Control Register n 0x450 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR24 Pin Control Register n 0x4B0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR25 Pin Control Register n 0x514 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR26 Pin Control Register n 0x57C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR27 Pin Control Register n 0x5E8 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR28 Pin Control Register n 0x658 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR29 Pin Control Register n 0x6CC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR3 Pin Control Register n 0x18 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR30 Pin Control Register n 0x744 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR31 Pin Control Register n 0x7C0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR4 Pin Control Register n 0x28 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR5 Pin Control Register n 0x3C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR6 Pin Control Register n 0x54 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR7 Pin Control Register n 0x70 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR8 Pin Control Register n 0x90 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR9 Pin Control Register n 0xB4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PORTC Pin Control and Interrupts PORT 0x0 0x0 0xCC registers n PORTC 89 DFCR Digital Filter Clock Register 0xC4 32 read-write n 0x0 0x0 CS Clock Source 0 1 read-write 0 Digital Filters are clocked by the bus clock. #0 1 Digital Filters are clocked by the 1 kHz LPO clock. #1 RESERVED no description available 1 31 read-only DFER Digital Filter Enable Register 0xC0 32 read-write n 0x0 0x0 DFE Digital Filter Enable 0 32 read-write 0 Digital Filter is disabled on the corresponding pin and output of the digital filter is reset to zero.Each bit in the field enables the digital filter of the same number as the bit. #0 1 Digital Filter is enabled on the corresponding pin, provided pin is configured as a digital input. #1 DFWR Digital Filter Width Register 0xC8 32 read-write n 0x0 0x0 FILT Filter Length 0 5 read-write RESERVED no description available 5 27 read-only GPCHR Global Pin Control High Register 0x84 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only GPCLR Global Pin Control Low Register 0x80 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only ISFR Interrupt Status Flag Register 0xA0 32 read-write n 0x0 0x0 ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to the flag. If configured for a level sensitive interrupt and the pin remains asserted then the flag will set again immediately after it is cleared. #1 PCR0 Pin Control Register n 0x0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR1 Pin Control Register n 0x4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR10 Pin Control Register n 0xDC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR11 Pin Control Register n 0x108 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR12 Pin Control Register n 0x138 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR13 Pin Control Register n 0x16C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR14 Pin Control Register n 0x1A4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR15 Pin Control Register n 0x1E0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR16 Pin Control Register n 0x220 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR17 Pin Control Register n 0x264 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR18 Pin Control Register n 0x2AC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR19 Pin Control Register n 0x2F8 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR2 Pin Control Register n 0xC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR20 Pin Control Register n 0x348 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR21 Pin Control Register n 0x39C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR22 Pin Control Register n 0x3F4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR23 Pin Control Register n 0x450 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR24 Pin Control Register n 0x4B0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR25 Pin Control Register n 0x514 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR26 Pin Control Register n 0x57C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR27 Pin Control Register n 0x5E8 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR28 Pin Control Register n 0x658 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR29 Pin Control Register n 0x6CC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR3 Pin Control Register n 0x18 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR30 Pin Control Register n 0x744 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR31 Pin Control Register n 0x7C0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR4 Pin Control Register n 0x28 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR5 Pin Control Register n 0x3C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR6 Pin Control Register n 0x54 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR7 Pin Control Register n 0x70 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR8 Pin Control Register n 0x90 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR9 Pin Control Register n 0xB4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PORTD Pin Control and Interrupts PORT 0x0 0x0 0xCC registers n PORTD 90 DFCR Digital Filter Clock Register 0xC4 32 read-write n 0x0 0x0 CS Clock Source 0 1 read-write 0 Digital Filters are clocked by the bus clock. #0 1 Digital Filters are clocked by the 1 kHz LPO clock. #1 RESERVED no description available 1 31 read-only DFER Digital Filter Enable Register 0xC0 32 read-write n 0x0 0x0 DFE Digital Filter Enable 0 32 read-write 0 Digital Filter is disabled on the corresponding pin and output of the digital filter is reset to zero.Each bit in the field enables the digital filter of the same number as the bit. #0 1 Digital Filter is enabled on the corresponding pin, provided pin is configured as a digital input. #1 DFWR Digital Filter Width Register 0xC8 32 read-write n 0x0 0x0 FILT Filter Length 0 5 read-write RESERVED no description available 5 27 read-only GPCHR Global Pin Control High Register 0x84 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only GPCLR Global Pin Control Low Register 0x80 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only ISFR Interrupt Status Flag Register 0xA0 32 read-write n 0x0 0x0 ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to the flag. If configured for a level sensitive interrupt and the pin remains asserted then the flag will set again immediately after it is cleared. #1 PCR0 Pin Control Register n 0x0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR1 Pin Control Register n 0x4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR10 Pin Control Register n 0xDC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR11 Pin Control Register n 0x108 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR12 Pin Control Register n 0x138 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR13 Pin Control Register n 0x16C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR14 Pin Control Register n 0x1A4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR15 Pin Control Register n 0x1E0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR16 Pin Control Register n 0x220 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR17 Pin Control Register n 0x264 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR18 Pin Control Register n 0x2AC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR19 Pin Control Register n 0x2F8 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR2 Pin Control Register n 0xC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR20 Pin Control Register n 0x348 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR21 Pin Control Register n 0x39C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR22 Pin Control Register n 0x3F4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR23 Pin Control Register n 0x450 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR24 Pin Control Register n 0x4B0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR25 Pin Control Register n 0x514 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR26 Pin Control Register n 0x57C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR27 Pin Control Register n 0x5E8 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR28 Pin Control Register n 0x658 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR29 Pin Control Register n 0x6CC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR3 Pin Control Register n 0x18 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR30 Pin Control Register n 0x744 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR31 Pin Control Register n 0x7C0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR4 Pin Control Register n 0x28 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR5 Pin Control Register n 0x3C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR6 Pin Control Register n 0x54 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR7 Pin Control Register n 0x70 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR8 Pin Control Register n 0x90 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR9 Pin Control Register n 0xB4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PORTE Pin Control and Interrupts PORT 0x0 0x0 0xCC registers n PORTE 91 DFCR Digital Filter Clock Register 0xC4 32 read-write n 0x0 0x0 CS Clock Source 0 1 read-write 0 Digital Filters are clocked by the bus clock. #0 1 Digital Filters are clocked by the 1 kHz LPO clock. #1 RESERVED no description available 1 31 read-only DFER Digital Filter Enable Register 0xC0 32 read-write n 0x0 0x0 DFE Digital Filter Enable 0 32 read-write 0 Digital Filter is disabled on the corresponding pin and output of the digital filter is reset to zero.Each bit in the field enables the digital filter of the same number as the bit. #0 1 Digital Filter is enabled on the corresponding pin, provided pin is configured as a digital input. #1 DFWR Digital Filter Width Register 0xC8 32 read-write n 0x0 0x0 FILT Filter Length 0 5 read-write RESERVED no description available 5 27 read-only GPCHR Global Pin Control High Register 0x84 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only GPCLR Global Pin Control Low Register 0x80 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only ISFR Interrupt Status Flag Register 0xA0 32 read-write n 0x0 0x0 ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to the flag. If configured for a level sensitive interrupt and the pin remains asserted then the flag will set again immediately after it is cleared. #1 PCR0 Pin Control Register n 0x0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR1 Pin Control Register n 0x4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR10 Pin Control Register n 0xDC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR11 Pin Control Register n 0x108 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR12 Pin Control Register n 0x138 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR13 Pin Control Register n 0x16C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR14 Pin Control Register n 0x1A4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR15 Pin Control Register n 0x1E0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR16 Pin Control Register n 0x220 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR17 Pin Control Register n 0x264 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR18 Pin Control Register n 0x2AC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR19 Pin Control Register n 0x2F8 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR2 Pin Control Register n 0xC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR20 Pin Control Register n 0x348 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR21 Pin Control Register n 0x39C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR22 Pin Control Register n 0x3F4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR23 Pin Control Register n 0x450 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR24 Pin Control Register n 0x4B0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR25 Pin Control Register n 0x514 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR26 Pin Control Register n 0x57C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR27 Pin Control Register n 0x5E8 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR28 Pin Control Register n 0x658 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR29 Pin Control Register n 0x6CC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR3 Pin Control Register n 0x18 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR30 Pin Control Register n 0x744 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR31 Pin Control Register n 0x7C0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR4 Pin Control Register n 0x28 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR5 Pin Control Register n 0x3C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR6 Pin Control Register n 0x54 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR7 Pin Control Register n 0x70 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR8 Pin Control Register n 0x90 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR9 Pin Control Register n 0xB4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PORTF Pin Control and Interrupts PORT 0x0 0x0 0xCC registers n PORTF 92 DFCR Digital Filter Clock Register 0xC4 32 read-write n 0x0 0x0 CS Clock Source 0 1 read-write 0 Digital Filters are clocked by the bus clock. #0 1 Digital Filters are clocked by the 1 kHz LPO clock. #1 RESERVED no description available 1 31 read-only DFER Digital Filter Enable Register 0xC0 32 read-write n 0x0 0x0 DFE Digital Filter Enable 0 32 read-write 0 Digital Filter is disabled on the corresponding pin and output of the digital filter is reset to zero.Each bit in the field enables the digital filter of the same number as the bit. #0 1 Digital Filter is enabled on the corresponding pin, provided pin is configured as a digital input. #1 DFWR Digital Filter Width Register 0xC8 32 read-write n 0x0 0x0 FILT Filter Length 0 5 read-write RESERVED no description available 5 27 read-only GPCHR Global Pin Control High Register 0x84 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only GPCLR Global Pin Control Low Register 0x80 32 write-only n 0x0 0x0 GPWD Global Pin Write Data 0 16 write-only GPWE Global Pin Write Enable 16 16 write-only ISFR Interrupt Status Flag Register 0xA0 32 read-write n 0x0 0x0 ISF Interrupt Status Flag 0 32 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to the flag. If configured for a level sensitive interrupt and the pin remains asserted then the flag will set again immediately after it is cleared. #1 PCR0 Pin Control Register n 0x0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR1 Pin Control Register n 0x4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR10 Pin Control Register n 0xDC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR11 Pin Control Register n 0x108 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR12 Pin Control Register n 0x138 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR13 Pin Control Register n 0x16C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR14 Pin Control Register n 0x1A4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR15 Pin Control Register n 0x1E0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR16 Pin Control Register n 0x220 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR17 Pin Control Register n 0x264 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR18 Pin Control Register n 0x2AC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR19 Pin Control Register n 0x2F8 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR2 Pin Control Register n 0xC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR20 Pin Control Register n 0x348 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR21 Pin Control Register n 0x39C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR22 Pin Control Register n 0x3F4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR23 Pin Control Register n 0x450 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR24 Pin Control Register n 0x4B0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR25 Pin Control Register n 0x514 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR26 Pin Control Register n 0x57C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR27 Pin Control Register n 0x5E8 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR28 Pin Control Register n 0x658 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR29 Pin Control Register n 0x6CC 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR3 Pin Control Register n 0x18 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR30 Pin Control Register n 0x744 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR31 Pin Control Register n 0x7C0 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR4 Pin Control Register n 0x28 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR5 Pin Control Register n 0x3C 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR6 Pin Control Register n 0x54 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR7 Pin Control Register n 0x70 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR8 Pin Control Register n 0x90 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PCR9 Pin Control Register n 0xB4 32 read-write n 0x0 0x0 DSE Drive Strength Enable 6 1 read-write 0 Low drive strength is configured on the corresponding pin, if pin is configured as a digital output. #0 1 High drive strength is configured on the corresponding pin, if pin is configured as a digital output. #1 IRQC Interrupt Configuration 16 4 read-write 0000 Interrupt/DMA Request disabled. #0000 0001 DMA Request on rising edge. #0001 0010 DMA Request on falling edge. #0010 0011 DMA Request on either edge. #0011 0100 Reserved. #0100 1000 Interrupt when logic zero. #1000 1001 Interrupt on rising edge. #1001 1010 Interrupt on falling edge. #1010 1011 Interrupt on either edge. #1011 1100 Interrupt when logic one. #1100 ISF Interrupt Status Flag 24 1 read-write 0 Configured interrupt has not been detected. #0 1 Configured interrupt has been detected. If pin is configured to generate a DMA request then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer, otherwise the flag remains set until a logic one is written to that flag. If configured for a level sensitive interrupt that remains asserted then flag will set again immediately. #1 LK Lock Register 15 1 read-write 0 Pin Control Register bits [15:0] are not locked. #0 1 Pin Control Register bits [15:0] are locked and cannot be updated until the next System Reset. #1 MUX Pin Mux Control 8 3 read-write 000 Pin Disabled (Analog). #000 001 Alternative 1 (GPIO). #001 010 Alternative 2 (chip specific). #010 011 Alternative 3 (chip specific). #011 100 Alternative 4 (chip specific). #100 101 Alternative 5 (chip specific). #101 110 Alternative 6 (chip specific). #110 111 Alternative 7 (chip specific / JTAG / NMI). #111 ODE Open Drain Enable 5 1 read-write 0 Open Drain output is disabled on the corresponding pin. #0 1 Open Drain output is enabled on the corresponding pin, provided pin is configured as a digital output. #1 PE Pull Enable 1 1 read-write 0 Internal pull-up or pull-down resistor is not enabled on the corresponding pin. #0 1 Internal pull-up or pull-down resistor is enabled on the corresponding pin, provided pin is configured as a digital input. #1 PFE Passive Filter Enable 4 1 read-write 0 Passive Input Filter is disabled on the corresponding pin. #0 1 Passive Input Filter is enabled on the corresponding pin, provided pin is configured as a digital input. A low pass filter (10 MHz to 30 MHz bandwidth) is enabled on the digital input path. Disable the Passive Input Filter when supporting high speed interfaces (> 2 MHz) on the pin. #1 PS Pull Select 0 1 read-write 0 Internal pull-down resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #0 1 Internal pull-up resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable Register bit is set. #1 RESERVED no description available 3 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 11 4 read-only RESERVED no description available 20 4 read-only RESERVED no description available 25 7 read-only SRE Slew Rate Enable 2 1 read-write 0 Fast slew rate is configured on the corresponding pin, if pin is configured as a digital output. #0 1 Slow slew rate is configured on the corresponding pin, if pin is configured as a digital output. #1 PTA General Purpose Input/Output GPIO 0x0 0x0 0x18 registers n PORTA 87 INT_PORTA 103 GPIOA_PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 GPIOA_PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port data direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured for general-purpose output, for the GPIO function. #1 GPIOA_PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0 or, is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 GPIOA_PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 GPIOA_PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 GPIOA_PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port data direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured for general-purpose output, for the GPIO function. #1 PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0 or, is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTB General Purpose Input/Output GPIO 0x0 0x0 0x18 registers n PORTB 88 INT_PORTB 104 GPIOB_PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 GPIOB_PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port data direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured for general-purpose output, for the GPIO function. #1 GPIOB_PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0 or, is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 GPIOB_PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 GPIOB_PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 GPIOB_PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port data direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured for general-purpose output, for the GPIO function. #1 PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0 or, is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTC General Purpose Input/Output GPIO 0x0 0x0 0x18 registers n PORTC 89 INT_PORTC 105 GPIOC_PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 GPIOC_PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port data direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured for general-purpose output, for the GPIO function. #1 GPIOC_PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0 or, is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 GPIOC_PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 GPIOC_PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 GPIOC_PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port data direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured for general-purpose output, for the GPIO function. #1 PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0 or, is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTD General Purpose Input/Output GPIO 0x0 0x0 0x18 registers n PORTD 90 INT_PORTD 106 GPIOD_PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 GPIOD_PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port data direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured for general-purpose output, for the GPIO function. #1 GPIOD_PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0 or, is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 GPIOD_PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 GPIOD_PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 GPIOD_PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port data direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured for general-purpose output, for the GPIO function. #1 PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0 or, is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTE General Purpose Input/Output GPIO 0x0 0x0 0x18 registers n PORTE 91 INT_PORTE 107 GPIOE_PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 GPIOE_PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port data direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured for general-purpose output, for the GPIO function. #1 GPIOE_PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0 or, is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 GPIOE_PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 GPIOE_PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 GPIOE_PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port data direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured for general-purpose output, for the GPIO function. #1 PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0 or, is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PTF General Purpose Input/Output GPIO 0x0 0x0 0x18 registers n PORTF 92 INT_PORTF 108 GPIOF_PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 GPIOF_PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port data direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured for general-purpose output, for the GPIO function. #1 GPIOF_PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0 or, is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 GPIOF_PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 GPIOF_PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 GPIOF_PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 PCOR Port Clear Output Register 0x8 32 write-only n 0x0 0x0 PTCO Port Clear Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is cleared to logic 0. #1 PDDR Port Data Direction Register 0x14 32 read-write n 0x0 0x0 PDD Port data direction 0 32 read-write 0 Pin is configured as general-purpose input, for the GPIO function. #0 1 Pin is configured for general-purpose output, for the GPIO function. #1 PDIR Port Data Input Register 0x10 32 read-only n 0x0 0x0 PDI Port Data Input 0 32 read-only 0 Pin logic level is logic 0 or, is not configured for use by digital function. #0 1 Pin logic level is logic 1. #1 PDOR Port Data Output Register 0x0 32 read-write n 0x0 0x0 PDO Port Data Output 0 32 read-write 0 Logic level 0 is driven on pin, provided pin is configured for general-purpose output. #0 1 Logic level 1 is driven on pin, provided pin is configured for general-purpose output. #1 PSOR Port Set Output Register 0x4 32 write-only n 0x0 0x0 PTSO Port Set Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to logic 1. #1 PTOR Port Toggle Output Register 0xC 32 write-only n 0x0 0x0 PTTO Port Toggle Output 0 32 write-only 0 Corresponding bit in PDORn does not change. #0 1 Corresponding bit in PDORn is set to the inverse of its existing logic state. #1 RCM Reset Control Module RCM 0x0 0x0 0x8 registers n MR Mode Register 0x7 8 read-only n 0x0 0x0 EZP_MS EZP_MS_B pin state 1 1 read-only 0 Pin negated (logic 1) #0 1 Pin asserted (logic 0) #1 RESERVED no description available 0 1 read-only RESERVED no description available 2 6 read-only RPFC Reset Pin Filter Control Register 0x4 8 read-write n 0x0 0x0 RESERVED no description available 3 5 read-only RSTFLTSRW Reset pin filter select in run and wait modes 0 2 read-write 00 All filtering disabled #00 01 Bus clock filter enabled for normal operation #01 10 LPO clock filter enabled for normal operation #10 11 Reserved (all filtering disabled) #11 RSTFLTSS Reset pin filter select in stop mode 2 1 read-write 0 All filtering disabled #0 1 LPO clock filter enabled #1 RPFW Reset Pin Filter Width Register 0x5 8 read-write n 0x0 0x0 RESERVED no description available 5 3 read-only RSTFLTSEL Reset pin filter bus clock select 0 5 read-write 00000 Bus clock filter count is 1 #00000 00001 Bus clock filter count is 2 #00001 00010 Bus clock filter count is 3 #00010 00011 Bus clock filter count is 4 #00011 00100 Bus clock filter count is 5 #00100 00101 Bus clock filter count is 6 #00101 00110 Bus clock filter count is 7 #00110 00111 Bus clock filter count is 8 #00111 01000 Bus clock filter count is 9 #01000 01001 Bus clock filter count is 10 #01001 01010 Bus clock filter count is 11 #01010 01011 Bus clock filter count is 12 #01011 01100 Bus clock filter count is 13 #01100 01101 Bus clock filter count is 14 #01101 01110 Bus clock filter count is 15 #01110 01111 Bus clock filter count is 16 #01111 10000 Bus clock filter count is 17 #10000 10001 Bus clock filter count is 18 #10001 10010 Bus clock filter count is 19 #10010 10011 Bus clock filter count is 20 #10011 10100 Bus clock filter count is 21 #10100 10101 Bus clock filter count is 22 #10101 10110 Bus clock filter count is 23 #10110 10111 Bus clock filter count is 24 #10111 11000 Bus clock filter count is 25 #11000 11001 Bus clock filter count is 26 #11001 11010 Bus clock filter count is 27 #11010 11011 Bus clock filter count is 28 #11011 11100 Bus clock filter count is 29 #11100 11101 Bus clock filter count is 30 #11101 11110 Bus clock filter count is 31 #11110 11111 Bus clock filter count is 32 #11111 SRS0 System Reset Status Register 0 0x0 8 read-only n 0x0 0x0 LOC Loss-of-clock reset 2 1 read-only 0 Reset not caused by a loss of external clock. #0 1 Reset caused by a loss of external clock. #1 LVD Low-voltage detect reset 1 1 read-only 0 Reset not caused by LVD trip or POR #0 1 Reset caused by LVD trip or POR #1 PIN External reset pin 6 1 read-only 0 Reset not caused by external reset pin #0 1 Reset caused by external reset pin #1 POR Power-on reset 7 1 read-only 0 Reset not caused by POR #0 1 Reset caused by POR #1 RESERVED no description available 3 2 read-only WAKEUP Low leakage wakeup reset 0 1 read-only 0 Reset not caused by LLWU module wakeup source #0 1 Reset caused by LLWU module wakeup source #1 WDOG Watchdog 5 1 read-only 0 Reset not caused by watchdog timeout #0 1 Reset caused by watchdog timeout #1 SRS1 System Reset Status Register 1 0x1 8 read-only n 0x0 0x0 EZPT EzPort Reset 4 1 read-only 0 Reset not caused by EzPort receiving the RESET command while the device is in EzPort mode #0 1 Reset caused by EzPort receiving the RESET command while the device is in EzPort mode #1 JTAG JTAG generated reset 0 1 read-only 0 Reset not caused by JTAG #0 1 Reset caused by JTAG #1 LOCKUP Core Lockup 1 1 read-only 0 Reset not caused by core LOCKUP event #0 1 Reset caused by core LOCKUP event #1 MDM_AP MDM-AP system reset request 3 1 read-only 0 Reset not caused by host debugger system setting of the System Reset Request bit #0 1 Reset caused by host debugger system setting of the System Reset Request bit #1 RESERVED no description available 6 1 read-only RESERVED no description available 7 1 read-only SACKERR Stop Mode Acknowledge Error Reset 5 1 read-only 0 Reset not caused by peripheral failure to acknowledge attempt to enter stop mode #0 1 Reset caused by peripheral failure to acknowledge attempt to enter stop mode #1 SW Software 2 1 read-only 0 Reset not caused by software setting of SYSRESETREQ bit #0 1 Reset caused by software setting of SYSRESETREQ bit #1 RFSYS System register file RFSYS 0x0 0x0 0x20 registers n REG0 Register file register 0x0 32 read-write n 0x0 0x0 HH no description available 24 8 read-write HL no description available 16 8 read-write LH no description available 8 8 read-write LL no description available 0 8 read-write REG1 Register file register 0x4 32 read-write n 0x0 0x0 HH no description available 24 8 read-write HL no description available 16 8 read-write LH no description available 8 8 read-write LL no description available 0 8 read-write REG2 Register file register 0xC 32 read-write n 0x0 0x0 HH no description available 24 8 read-write HL no description available 16 8 read-write LH no description available 8 8 read-write LL no description available 0 8 read-write REG3 Register file register 0x18 32 read-write n 0x0 0x0 HH no description available 24 8 read-write HL no description available 16 8 read-write LH no description available 8 8 read-write LL no description available 0 8 read-write REG4 Register file register 0x28 32 read-write n 0x0 0x0 HH no description available 24 8 read-write HL no description available 16 8 read-write LH no description available 8 8 read-write LL no description available 0 8 read-write REG5 Register file register 0x3C 32 read-write n 0x0 0x0 HH no description available 24 8 read-write HL no description available 16 8 read-write LH no description available 8 8 read-write LL no description available 0 8 read-write REG6 Register file register 0x54 32 read-write n 0x0 0x0 HH no description available 24 8 read-write HL no description available 16 8 read-write LH no description available 8 8 read-write LL no description available 0 8 read-write REG7 Register file register 0x70 32 read-write n 0x0 0x0 HH no description available 24 8 read-write HL no description available 16 8 read-write LH no description available 8 8 read-write LL no description available 0 8 read-write RFVBAT VBAT register file RFVBAT 0x0 0x0 0x20 registers n REG0 VBAT register file register 0x0 32 read-write n 0x0 0x0 HH no description available 24 8 read-write HL no description available 16 8 read-write LH no description available 8 8 read-write LL no description available 0 8 read-write REG1 VBAT register file register 0x4 32 read-write n 0x0 0x0 HH no description available 24 8 read-write HL no description available 16 8 read-write LH no description available 8 8 read-write LL no description available 0 8 read-write REG2 VBAT register file register 0xC 32 read-write n 0x0 0x0 HH no description available 24 8 read-write HL no description available 16 8 read-write LH no description available 8 8 read-write LL no description available 0 8 read-write REG3 VBAT register file register 0x18 32 read-write n 0x0 0x0 HH no description available 24 8 read-write HL no description available 16 8 read-write LH no description available 8 8 read-write LL no description available 0 8 read-write REG4 VBAT register file register 0x28 32 read-write n 0x0 0x0 HH no description available 24 8 read-write HL no description available 16 8 read-write LH no description available 8 8 read-write LL no description available 0 8 read-write REG5 VBAT register file register 0x3C 32 read-write n 0x0 0x0 HH no description available 24 8 read-write HL no description available 16 8 read-write LH no description available 8 8 read-write LL no description available 0 8 read-write REG6 VBAT register file register 0x54 32 read-write n 0x0 0x0 HH no description available 24 8 read-write HL no description available 16 8 read-write LH no description available 8 8 read-write LL no description available 0 8 read-write REG7 VBAT register file register 0x70 32 read-write n 0x0 0x0 HH no description available 24 8 read-write HL no description available 16 8 read-write LH no description available 8 8 read-write LL no description available 0 8 read-write RNG Random Number Generator Accelerator RNG 0x0 0x0 0x10 registers n RNG 23 INT_RNG 39 CR RNGA Control Register 0x0 32 read-write n 0x0 0x0 CLRI Clear Interrupt 3 1 write-only 0 Do not clear the interrupt. #0 1 Clear the interrupt. #1 GO no description available 0 1 read-write 0 RNGA Output Register is not loaded with random data. #0 1 RNGA Output Register is loaded with random data. #1 HA High Assurance 1 1 read-write 0 Notification of security violations is enabled. #0 1 Notification of security violations is masked. #1 INTM Interrupt Mask 2 1 read-write 0 Interrupt is enabled. #0 1 Interrupt is masked. #1 RESERVED no description available 5 27 read-only SLP Sleep 4 1 read-write 0 RNGA is not in Sleep mode. #0 1 RNGA is in Sleep mode. #1 ER RNGA Entropy Register 0x8 32 write-only n 0x0 0x0 EXT_ENT External Entropy 0 32 write-only OR RNGA Output Register 0xC 32 read-only n 0x0 0x0 RANDOUT Random Output 0 32 read-only SR RNGA Status Register 0x4 32 read-only n 0x0 0x0 ERRI Error Interrupt 3 1 read-only 0 The RNGA Output Register has not been read while empty. #0 1 The RNGA Output Register has been read while empty. #1 LRS Last Read Status 1 1 read-only 0 Last read was performed while the RNGA Output Register was not empty. #0 1 Last read was performed while the RNGA Output Register was empty (underflow condition). #1 OREG_LVL Output Register Level 8 8 read-only OREG_SIZE Output Register Size 16 8 read-only ORU Output Register Underflow 2 1 read-only 0 The RNGA Output Register has not been read while empty since last read of the RNGA Status Register. #0 1 The RNGA Output Register has been read while empty since last read of the RNGA Status Register. #1 RESERVED no description available 5 3 read-only RESERVED no description available 24 8 read-only SECV Security Violation 0 1 read-only 0 No security violations have occured or the High Assurance bit (HA) in the RNGA Control Register is not set. #0 1 A security violation has occurred. #1 SLP Sleep 4 1 read-only 0 The RNGA is not in Sleep mode. #0 1 The RNGA is in Sleep mode. #1 RTC Secure Real Time Clock RTC 0x0 0x0 0x808 registers n RTC 66 RTC_Seconds 67 INT_RTC 82 INT_RTC_Seconds 83 CR RTC Control Register 0x10 32 read-write n 0x0 0x0 CLKO Clock Output 9 1 read-write 0 The 32kHz clock is output to other peripherals #0 1 The 32kHz clock is not output to other peripherals #1 OSCE Oscillator Enable 8 1 read-write 0 32.768 kHz oscillator is disabled. #0 1 32.768 kHz oscillator is enabled. After setting this bit, wait the oscillator startup time before enabling the time counter to allow the 32.768 kHz clock time to stabilize. #1 RESERVED no description available 4 4 read-only RESERVED no description available 14 1 read-only RESERVED no description available 15 17 read-only SC16P Oscillator 16pF load configure 10 1 read-write 0 Disable the load. #0 1 Enable the additional load. #1 SC2P Oscillator 2pF load configure 13 1 read-write 0 Disable the load. #0 1 Enable the additional load. #1 SC4P Oscillator 4pF load configure 12 1 read-write 0 Disable the load. #0 1 Enable the additional load. #1 SC8P Oscillator 8pF load configure 11 1 read-write 0 Disable the load. #0 1 Enable the additional load. #1 SUP Supervisor Access 2 1 read-write 0 Non-supervisor mode write accesses are not supported and generate a bus error. #0 1 Non-supervisor mode write accesses are supported. #1 SWR Software Reset 0 1 read-write 0 No effect #0 1 Resets all RTC registers except for the SWR bit and the RTC_WAR and RTC_RAR registers. The SWR bit is cleared after VBAT POR and by software explicitly clearing it. #1 UM Update Mode 3 1 read-write 0 Registers cannot be written when locked. #0 1 Registers can be written when locked under limited conditions. #1 WPE Wakeup Pin Enable 1 1 read-write 0 Wakeup pin is disabled. #0 1 Wakeup pin is enabled and wakeup pin asserts if the RTC interrupt asserts and the chip is powered down. #1 IER RTC Interrupt Enable Register 0x1C 32 read-write n 0x0 0x0 MOIE Monotonic Overflow Interrupt Enable 3 1 read-write 0 Monotonic overflow flag does not generate an interrupt. #0 1 Monotonic overflow flag does generate an interrupt. #1 RESERVED no description available 5 3 read-write RESERVED no description available 8 24 read-only TAIE Time Alarm Interrupt Enable 2 1 read-write 0 Time alarm flag does not generate an interrupt. #0 1 Time alarm flag does generate an interrupt. #1 TIIE Time Invalid Interrupt Enable 0 1 read-write 0 Time invalid flag does not generate an interrupt. #0 1 Time invalid flag does generate an interrupt. #1 TOIE Time Overflow Interrupt Enable 1 1 read-write 0 Time overflow flag does not generate an interrupt. #0 1 Time overflow flag does generate an interrupt. #1 TSIE Time Seconds Interrupt Enable 4 1 read-write 0 Seconds interrupt is disabled. #0 1 Seconds interrupt is enabled. #1 LR RTC Lock Register 0x18 32 read-write n 0x0 0x0 CRL Control Register Lock 4 1 read-write 0 Control register is locked and writes are ignored. #0 1 Control register is not locked and writes complete as normal. #1 LRL Lock Register Lock 6 1 read-write 0 Lock register is locked and writes are ignored. #0 1 Lock register is not locked and writes complete as normal. #1 MCHL Monotonic Counter High Lock 11 1 read-write 0 Monotonic counter high register is locked and writes are ignored. #0 1 Monotonic counter high register is not locked and writes complete as normal. #1 MCLL Monotonic Counter Low Lock 10 1 read-write 0 Monotonic counter low register is locked and writes are ignored. #0 1 Monotonic counter low register is not locked and writes complete as normal. #1 MEL Monotonic Enable Lock 9 1 read-write 0 Monotonic enable register is locked and writes are ignored. #0 1 Monotonic enable register is not locked and writes complete as normal. #1 RESERVED no description available 0 3 read-only RESERVED no description available 7 1 read-only RESERVED no description available 12 4 read-only RESERVED no description available 16 16 read-only SRL Status Register Lock 5 1 read-write 0 Status register is locked and writes are ignored. #0 1 Status register is not locked and writes complete as normal. #1 TCL Time Compensation Lock 3 1 read-write 0 Time compensation register is locked and writes are ignored. #0 1 Time compensation register is not locked and writes complete as normal. #1 TTSL Tamper Time Seconds Lock 8 1 read-write 0 Tamper time seconds register is locked and writes are ignored. #0 1 Tamper time seconds register is not locked and writes complete as normal. #1 MCHR RTC Monotonic Counter High Register 0x2C 32 read-write n 0x0 0x0 MCH Monotonic Counter High 0 32 read-write MCLR RTC Monotonic Counter Low Register 0x28 32 read-write n 0x0 0x0 MCL Monotonic Counter Low 0 32 read-write MER RTC Monotonic Enable Register 0x24 32 read-write n 0x0 0x0 MCE Monotonic Counter Enable 4 1 read-write 0 Writes to the monotonic counter load the counter with the value written. #0 1 Writes to the monotonic counter increment the counter. #1 RESERVED no description available 0 4 read-only RESERVED no description available 5 27 read-only RAR RTC Read Access Register 0x804 32 read-write n 0x0 0x0 CRR Control Register Read 4 1 read-write 0 Reads to the control register are ignored. #0 1 Reads to the control register complete as normal. #1 IERR Interrupt Enable Register Read 7 1 read-write 0 Reads to the interrupt enable register are ignored. #0 1 Reads to the interrupt enable register complete as normal. #1 LRR Lock Register Read 6 1 read-write 0 Reads to the lock register are ignored. #0 1 Reads to the lock register complete as normal. #1 MCHR Monotonic Counter High Read 11 1 read-write 0 Reads to the monotonic counter high register are ignored. #0 1 Reads to the monotonic counter high register complete as normal. #1 MCLR Monotonic Counter Low Read 10 1 read-write 0 Reads to the monotonic counter low register are ignored. #0 1 Reads to the monotonic counter low register complete as normal. #1 MERR Monotonic Enable Register Read 9 1 read-write 0 Reads to the monotonic enable register are ignored. #0 1 Reads to the monotonic enable register complete as normal. #1 RESERVED no description available 12 4 read-only RESERVED no description available 16 16 read-only SRR Status Register Read 5 1 read-write 0 Reads to the status register are ignored. #0 1 Reads to the status register complete as normal. #1 TARR Time Alarm Register Read 2 1 read-write 0 Reads to the time alarm register are ignored. #0 1 Reads to the time alarm register complete as normal. #1 TCRR Time Compensation Register Read 3 1 read-write 0 Reads to the time compensation register are ignored. #0 1 Reads to the time compensation register complete as normal. #1 TPRR Time Prescaler Register Read 1 1 read-write 0 Reads to the time prescaler register are ignored. #0 1 Reads to the time prescaler register complete as normal. #1 TSRR Time Seconds Register Read 0 1 read-write 0 Reads to the time seconds register are ignored. #0 1 Reads to the time seconds register complete as normal. #1 TTSR Tamper Time Seconds Read 8 1 read-write 0 Reads to the tamper time seconds register are ignored. #0 1 Reads to the tamper time seconds register complete as normal. #1 SR RTC Status Register 0x14 32 read-write n 0x0 0x0 MOF Monotonic Overflow Flag 3 1 read-only 0 Monotonic counter overflow has not occurred. #0 1 Monotonic counter overflow has occurred and monotonic counter is read as zero. #1 RESERVED no description available 5 27 read-only TAF Time Alarm Flag 2 1 read-only 0 Time alarm has not occurred. #0 1 Time alarm has occurred. #1 TCE Time Counter Enable 4 1 read-write 0 Time counter is disabled. #0 1 Time counter is enabled. #1 TIF Time Invalid Flag 0 1 read-only 0 Time is valid. #0 1 Time is invalid and time counter is read as zero. #1 TOF Time Overflow Flag 1 1 read-only 0 Time overflow has not occurred. #0 1 Time overflow has occurred and time counter is read as zero. #1 TAR RTC Time Alarm Register 0x8 32 read-write n 0x0 0x0 TAR Time Alarm Register 0 32 read-write TCR RTC Time Compensation Register 0xC 32 read-write n 0x0 0x0 CIC Compensation Interval Counter 24 8 read-only CIR Compensation Interval Register 8 8 read-write TCR Time Compensation Register 0 8 read-write 0 Time prescaler register overflows every 32768 clock cycles. #0 1 Time prescaler register overflows every 32767 clock cycles. #1 10000000 Time prescaler register overflows every 32896 clock cycles. #10000000 1111111 Time prescaler register overflows every 32641 clock cycles. #1111111 11111111 Time prescaler register overflows every 32769 clock cycles. #11111111 TCV Time Compensation Value 16 8 read-only TPR RTC Time Prescaler Register 0x4 32 read-write n 0x0 0x0 RESERVED no description available 16 16 read-only TPR Time Prescaler Register 0 16 read-write TSR RTC Time Seconds Register 0x0 32 read-write n 0x0 0x0 TSR Time Seconds Register 0 32 read-write TTSR RTC Tamper Time Seconds Register 0x20 32 read-only n 0x0 0x0 TTS Tamper Time Seconds 0 32 read-only WAR RTC Write Access Register 0x800 32 read-write n 0x0 0x0 CRW Control Register Write 4 1 read-write 0 Writes to the control register are ignored. #0 1 Writes to the control register complete as normal. #1 IERW Interrupt Enable Register Write 7 1 read-write 0 Writes to the interupt enable register are ignored. #0 1 Writes to the interrupt enable register complete as normal. #1 LRW Lock Register Write 6 1 read-write 0 Writes to the lock register are ignored. #0 1 Writes to the lock register complete as normal. #1 MCHW Monotonic Counter High Write 11 1 read-write 0 Writes to the monotonic counter high register are ignored. #0 1 Writes to the monotonic counter high register complete as normal. #1 MCLW Monotonic Counter Low Write 10 1 read-write 0 Writes to the monotonic counter low register are ignored. #0 1 Writes to the monotonic counter low register complete as normal. #1 MERW Monotonic Enable Register Write 9 1 read-write 0 Writes to the monotonic enable register are ignored. #0 1 Writes to the monotonic enable register complete as normal. #1 RESERVED no description available 12 4 read-only RESERVED no description available 16 16 read-only SRW Status Register Write 5 1 read-write 0 Writes to the status register are ignored. #0 1 Writes to the status register complete as normal. #1 TARW Time Alarm Register Write 2 1 read-write 0 Writes to the time alarm register are ignored. #0 1 Writes to the time alarm register complete as normal. #1 TCRW Time Compensation Register Write 3 1 read-write 0 Writes to the time compensation register are ignored. #0 1 Writes to the time compensation register complete as normal. #1 TPRW Time Prescaler Register Write 1 1 read-write 0 Writes to the time prescaler register are ignored. #0 1 Writes to the time prescaler register complete as normal. #1 TSRW Time Seconds Register Write 0 1 read-write 0 Writes to the time seconds register are ignored. #0 1 Writes to the time seconds register complete as normal. #1 TTSW Tamper Time Seconds Write 8 1 read-write 0 Writes to the tamper time seconds register are ignored. #0 1 Writes to the tamper time seconds register complete as normal. #1 SDHC Secured Digital Host Controller SDHC 0x0 0x0 0x100 registers n SDHC 80 INT_SDHC 96 AC12ERR Auto CMD12 Error Status Register 0x3C 32 read-only n 0x0 0x0 AC12CE Auto CMD12 CRC Error 3 1 read-only 0 No CRC error #0 1 CRC Error met in auto CMD12 Response #1 AC12EBE Auto CMD12 End Bit Error 2 1 read-only 0 No error #0 1 End bit error generated #1 AC12IE Auto CMD12 Index Error 4 1 read-only 0 No error #0 1 Error, the CMD index in response is not CMD12 #1 AC12NE Auto CMD12 Not Executed 0 1 read-only 0 Executed #0 1 Not executed #1 AC12TOE Auto CMD12 Timeout Error 1 1 read-only 0 No error #0 1 Time out #1 CNIBAC12E Command Not Issued By Auto CMD12 Error 7 1 read-only 0 No error #0 1 Not issued #1 RESERVED no description available 5 2 read-only RESERVED no description available 8 24 read-only ADMAES ADMA Error Status Register 0x54 32 read-only n 0x0 0x0 ADMADCE ADMA Descritor Error 3 1 read-only 0 No error #0 1 Error #1 ADMAES ADMA Error State (when ADMA Error is occurred.) 0 2 read-only ADMALME ADMA Length Mismatch Error 2 1 read-only 0 No error #0 1 Error #1 RESERVED no description available 4 28 read-only ADSADDR ADMA System Address Register 0x58 32 read-write n 0x0 0x0 ADSADDR ADMA System Address 2 30 read-write RESERVED no description available 0 2 read-only BLKATTR Block Attributes Register 0x4 32 read-write n 0x0 0x0 BLKCNT Blocks Count For Current Transfer 16 16 read-write 0 Stop count #0 1 1 block #1 10 2 blocks #10 1111111111111111 65535 blocks #1111111111111111 BLKSIZE Transfer Block Size 0 13 read-write 0 No data transfer #0 1 1 Byte #1 10 2 Bytes #10 100 4 Bytes #100 1000000000 512 Bytes #1000000000 100000000000 2048 Bytes #100000000000 1000000000000 4096 Bytes #1000000000000 11 3 Bytes #11 111111111 511 Bytes #111111111 RESERVED no description available 13 3 read-only CMDARG Command Argument Register 0x8 32 read-write n 0x0 0x0 CMDARG Command Argument 0 32 read-write CMDRSP0 Command Response 0 0x10 32 read-only n 0x0 0x0 CMDRSP0 Command Response 0 0 32 read-only CMDRSP1 Command Response 1 0x14 32 read-only n 0x0 0x0 CMDRSP1 Command Response 1 0 32 read-only CMDRSP2 Command Response 2 0x18 32 read-only n 0x0 0x0 CMDRSP2 Command Response 2 0 32 read-only CMDRSP3 Command Response 3 0x1C 32 read-only n 0x0 0x0 CMDRSP3 Command Response 3 0 32 read-only DATPORT Buffer Data Port Register 0x20 32 read-write n 0x0 0x0 DATCONT Data Content 0 32 read-write DSADDR DMA System Address Register 0x0 32 read-write n 0x0 0x0 DSADDR DMA System Address 2 30 read-write RESERVED no description available 0 2 read-only FEVT Force Event Register 0x50 32 write-only n 0x0 0x0 AC12CE Force Event Auto Command 12 CRC Error 2 1 write-only AC12E Force Event Auto Command 12 Error 24 1 write-only AC12EBE Force Event Auto Command 12 End Bit Error 3 1 write-only AC12IE Force Event Auto Command 12 Index Error 4 1 write-only AC12NE Force Event Auto Command 12 Not Executed 0 1 write-only AC12TOE Force Event Auto Command 12 Time Out Error 1 1 write-only CCE Force Event Command CRC Error 17 1 write-only CEBE Force Event Command End Bit Error 18 1 write-only CIE Force Event Command Index Error 19 1 write-only CINT Force Event Card Interrupt 31 1 write-only CNIBAC12E Force Event Command Not Executed By Auto Command 12 Error 7 1 write-only CTOE Force Event Command Time Out Error 16 1 write-only DCE Force Event Data CRC Error 21 1 write-only DEBE Force Event Data End Bit Error 22 1 write-only DMAE Force Event DMA Error 28 1 write-only DTOE Force Event Data Time Out Error 20 1 write-only RESERVED no description available 5 2 write-only RESERVED no description available 8 8 write-only RESERVED no description available 23 1 write-only RESERVED no description available 25 3 write-only RESERVED no description available 29 2 write-only HOSTVER Host Controller Version 0xFC 32 read-only n 0x0 0x0 RESERVED no description available 16 16 read-only SVN Specification Version Number 0 8 read-only 1 SD host specification version 2.0, supports test event register and ADMA. #1 VVN Vendor Version Number 8 8 read-only 0 Freescale SDHC version 1.0 #0 10000 Freescale SDHC version 2.0 #10000 10001 Freescale SDHC version 2.1 #10001 10010 Freescale SDHC version 2.2 #10010 HTCAPBLT Host Controller Capabilities 0x40 32 read-only n 0x0 0x0 ADMAS ADMA Support 20 1 read-only 0 Advanced DMA not supported #0 1 Advanced DMA supported #1 DMAS DMA Support 22 1 read-only 0 DMA not supported #0 1 DMA supported #1 HSS High Speed Support 21 1 read-only 0 High speed not supported #0 1 High speed supported #1 MBL Max Block Length 16 3 read-only 000 512 bytes #000 001 1024 bytes #001 010 2048 bytes #010 011 4096 bytes #011 RESERVED no description available 0 16 read-only RESERVED no description available 19 1 read-only RESERVED no description available 27 5 read-only SRS Suspend/Resume Support 23 1 read-only 0 Not supported #0 1 Supported #1 VS18 Voltage Support 1.8 V 26 1 read-only 0 1.8 V not supported #0 1 1.8 V supported #1 VS30 Voltage Support 3.0 V 25 1 read-only 0 3.0 V not supported #0 1 3.0 V supported #1 VS33 Voltage Support 3.3 V 24 1 read-only 0 3.3 V not supported #0 1 3.3 V supported #1 IRQSIGEN Interrupt Signal Enable Register 0x38 32 read-write n 0x0 0x0 AC12EIEN Auto CMD12 Error Interrupt Enable 24 1 read-write 0 Masked #0 1 Enabled #1 BGEIEN Block Gap Event Interrupt Enable 2 1 read-write 0 Masked #0 1 Enabled #1 BRRIEN Buffer Read Ready Interrupt Enable 5 1 read-write 0 Masked #0 1 Enabled #1 BWRIEN Buffer Write Ready Interrupt Enable 4 1 read-write 0 Masked #0 1 Enabled #1 CCEIEN Command CRC Error Interrupt Enable 17 1 read-write 0 Masked #0 1 Enabled #1 CCIEN Command Complete Interrupt Enable 0 1 read-write 0 Masked #0 1 Enabled #1 CEBEIEN Command End Bit Error Interrupt Enable 18 1 read-write 0 Masked #0 1 Enabled #1 CIEIEN Command Index Error Interrupt Enable 19 1 read-write 0 Masked #0 1 Enabled #1 CINSIEN Card Insertion Interrupt Enable 6 1 read-write 0 Masked #0 1 Enabled #1 CINTIEN Card Interrupt Enable 8 1 read-write 0 Masked #0 1 Enabled #1 CRMIEN Card Removal Interrupt Enable 7 1 read-write 0 Masked #0 1 Enabled #1 CTOEIEN Command Timeout Error Interrupt Enable 16 1 read-write 0 Masked #0 1 Enabled #1 DCEIEN Data CRC Error Interrupt Enable 21 1 read-write 0 Masked #0 1 Enabled #1 DEBEIEN Data End Bit Error Interrupt Enable 22 1 read-write 0 Masked #0 1 Enabled #1 DINTIEN DMA Interrupt Enable 3 1 read-write 0 Masked #0 1 Enabled #1 DMAEIEN DMA Error Interrupt Enable 28 1 read-write 0 Masked #0 1 Enabled #1 DTOEIEN Data Timeout Error Interrupt Enable 20 1 read-write 0 Masked #0 1 Enabled #1 RESERVED no description available 9 7 read-only RESERVED no description available 23 1 read-only RESERVED no description available 25 3 read-only RESERVED no description available 29 3 read-only TCIEN Transfer Complete Interrupt Enable 1 1 read-write 0 Masked #0 1 Enabled #1 IRQSTAT Interrupt Status Register 0x30 32 read-write n 0x0 0x0 AC12E Auto CMD12 Error 24 1 read-write 0 No Error #0 1 Error #1 BGE Block Gap Event 2 1 read-write 0 No block gap event #0 1 Transaction stopped at block gap #1 BRR Buffer Read Ready 5 1 read-write 0 Not ready to read buffer #0 1 Ready to read buffer #1 BWR Buffer Write Ready 4 1 read-write 0 Not ready to write buffer #0 1 Ready to write buffer #1 CC Command Complete 0 1 read-write 0 Command not complete #0 1 Command complete #1 CCE Command CRC Error 17 1 read-write 0 No Error #0 1 CRC Error Generated #1 CEBE Command End Bit Error 18 1 read-write 0 No Error #0 1 End Bit Error Generated #1 CIE Command Index Error 19 1 read-write 0 No Error #0 1 Error #1 CINS Card Insertion 6 1 read-write 0 Card state unstable or removed #0 1 Card inserted #1 CINT Card Interrupt 8 1 read-write 0 No Card Interrupt #0 1 Generate Card Interrupt #1 CRM Card Removal 7 1 read-write 0 Card state unstable or inserted #0 1 Card removed #1 CTOE Command Timeout Error 16 1 read-write 0 No Error #0 1 Time out #1 DCE Data CRC Error 21 1 read-write 0 No Error #0 1 Error #1 DEBE Data End Bit Error 22 1 read-write 0 No Error #0 1 Error #1 DINT DMA Interrupt 3 1 read-write 0 No DMA Interrupt #0 1 DMA Interrupt is generated #1 DMAE DMA Error 28 1 read-write 0 No Error #0 1 Error #1 DTOE Data Timeout Error 20 1 read-write 0 No Error #0 1 Time out #1 RESERVED no description available 9 7 read-only RESERVED no description available 23 1 read-only RESERVED no description available 25 3 read-only RESERVED no description available 29 3 read-only TC Transfer Complete 1 1 read-write 0 Transfer not complete #0 1 Transfer complete #1 IRQSTATEN Interrupt Status Enable Register 0x34 32 read-write n 0x0 0x0 AC12ESEN Auto CMD12 Error Status Enable 24 1 read-write 0 Masked #0 1 Enabled #1 BGESEN Block Gap Event Status Enable 2 1 read-write 0 Masked #0 1 Enabled #1 BRRSEN Buffer Read Ready Status Enable 5 1 read-write 0 Masked #0 1 Enabled #1 BWRSEN Buffer Write Ready Status Enable 4 1 read-write 0 Masked #0 1 Enabled #1 CCESEN Command CRC Error Status Enable 17 1 read-write 0 Masked #0 1 Enabled #1 CCSEN Command Complete Status Enable 0 1 read-write 0 Masked #0 1 Enabled #1 CEBESEN Command End Bit Error Status Enable 18 1 read-write 0 Masked #0 1 Enabled #1 CIESEN Command Index Error Status Enable 19 1 read-write 0 Masked #0 1 Enabled #1 CINSEN Card Insertion Status Enable 6 1 read-write 0 Masked #0 1 Enabled #1 CINTSEN Card Interrupt Status Enable 8 1 read-write 0 Masked #0 1 Enabled #1 CRMSEN Card Removal Status Enable 7 1 read-write 0 Masked #0 1 Enabled #1 CTOESEN Command Timeout Error Status Enable 16 1 read-write 0 Masked #0 1 Enabled #1 DCESEN Data CRC Error Status Enable 21 1 read-write 0 Masked #0 1 Enabled #1 DEBESEN Data End Bit Error Status Enable 22 1 read-write 0 Masked #0 1 Enabled #1 DINTSEN DMA Interrupt Status Enable 3 1 read-write 0 Masked #0 1 Enabled #1 DMAESEN DMA Error Status Enable 28 1 read-write 0 Masked #0 1 Enabled #1 DTOESEN Data Timeout Error Status Enable 20 1 read-write 0 Masked #0 1 Enabled #1 RESERVED no description available 9 7 read-only RESERVED no description available 23 1 read-only RESERVED no description available 25 3 read-only RESERVED no description available 29 3 read-only TCSEN Transfer Complete Status Enable 1 1 read-write 0 Masked #0 1 Enabled #1 MMCBOOT MMC Boot Register 0xC4 32 read-write n 0x0 0x0 AUTOSABGEN no description available 7 1 read-write BOOTACK Boot ack mode select 4 1 read-write 0 No ack #0 1 Ack #1 BOOTBLKCNT no description available 16 16 read-write BOOTEN Boot mode enable 6 1 read-write 0 Fast boot disable #0 1 Fast boot enable #1 BOOTMODE Boot mode select 5 1 read-write 0 Normal boot #0 1 Alternative boot #1 DTOCVACK Boot ACK time out counter value. 0 4 read-write 0000 SDCLK x 2^8 #0000 0001 SDCLK x 2^9 #0001 0010 SDCLK x 2^10 #0010 0011 SDCLK x 2^11 #0011 0100 SDCLK x 2^12 #0100 0101 SDCLK x 2^13 #0101 0110 SDCLK x 2^14 #0110 0111 SDCLK x 2^15 #0111 1110 SDCLK x 2^22 #1110 1111 Reserved #1111 RESERVED no description available 8 8 read-only PROCTL Protocol Control Register 0x28 32 read-write n 0x0 0x0 CDSS Card Detect Signal Selection 7 1 read-write 0 Card detection level is selected (for normal purpose) #0 1 Card detection test level is selected (for test purpose) #1 CDTL Card Detect Test Level 6 1 read-write 0 Card detect test level is 0, no card inserted #0 1 Card detect test level is 1, card inserted #1 CREQ Continue Request 17 1 read-write 0 No effect #0 1 Restart #1 D3CD DAT3 as Card Detection Pin 3 1 read-write 0 DAT3 does not monitor card Insertion #0 1 DAT3 as card detection pin #1 DMAS DMA Select 8 2 read-write 00 No DMA or simple DMA is selected #00 01 ADMA1 is selected #01 10 ADMA2 is selected #10 11 Reserved #11 DTW Data Transfer Width 1 2 read-write 00 1-bit mode #00 01 4-bit mode #01 10 8-bit mode #10 11 Reserved #11 EMODE Endian Mode 4 2 read-write 00 Big endian mode #00 01 Half word big endian mode #01 10 Little endian mode #10 11 Reserved #11 IABG Interrupt At Block Gap 19 1 read-write 0 Disabled #0 1 Enabled #1 LCTL LED Control 0 1 read-write 0 LED off #0 1 LED on #1 RESERVED no description available 10 6 read-only RESERVED no description available 20 4 read-only RESERVED no description available 27 5 read-only RWCTL Read Wait Control 18 1 read-write 0 Disable read wait control, and stop SD clock at block gap when SABGREQ bit is set. #0 1 Enable read wait control, and assert read wait without stopping SD clock at block gap when SABGREQ bit is set. #1 SABGREQ Stop At Block Gap Request 16 1 read-write 0 Transfer #0 1 Stop #1 WECINS Wakeup Event Enable On SD Card Insertion 25 1 read-write 0 Disabled #0 1 Enabled #1 WECINT Wakeup Event Enable On Card Interrupt 24 1 read-write 0 Disabled #0 1 Enabled #1 WECRM Wakeup Event Enable On SD Card Removal 26 1 read-write 0 Disabled #0 1 Enabled #1 PRSSTAT Present State Register 0x24 32 read-only n 0x0 0x0 BREN Buffer Read Enable 11 1 read-only 0 Read disable, valid data less than the watermark level exist in the buffer. #0 1 Read enable, valid data greater than the watermark level exist in the buffer. #1 BWEN Buffer Write Enable 10 1 read-only 0 Write disable, the buffer can hold valid data less than the write watermark level. #0 1 Write enable, the buffer can hold valid data greater than the write watermark level. #1 CDIHB Command Inhibit (DAT) 1 1 read-only 0 Can issue command which uses the DAT line #0 1 Cannot issue command which uses the DAT line #1 CIHB Command Inhibit (CMD) 0 1 read-only 0 Can issue command using only CMD line #0 1 Cannot issue command #1 CINS Card Inserted 16 1 read-only 0 Power on reset or no card #0 1 Card inserted #1 CLSL CMD Line Signal Level 23 1 read-only DLA Data Line Active 2 1 read-only 0 DAT line inactive #0 1 DAT line active #1 DLSL DAT Line Signal Level 24 8 read-only HCKOFF System Clock Gated Off Internally 5 1 read-only 0 System clock is active #0 1 System clock is gated off #1 IPGOFF Bus Clock Gated Off Internally 4 1 read-only 0 Bus clock is active #0 1 Bus clock is gated off #1 PEROFF SDHC clock Gated Off Internally 6 1 read-only 0 SDHC clock is active #0 1 SDHC clock is gated off #1 RESERVED no description available 12 4 read-only RESERVED no description available 17 6 read-only RTA Read Transfer Active 9 1 read-only 0 No valid data #0 1 Transferring data #1 SDOFF SD Clock Gated Off Internally 7 1 read-only 0 SD clock is active #0 1 SD clock is gated off #1 SDSTB SD Clock Stable 3 1 read-only 0 Clock is changing frequency and not stable #0 1 Clock is stable #1 WTA Write Transfer Active 8 1 read-only 0 No valid data #0 1 Transferring data #1 SYSCTL System Control Register 0x2C 32 read-write n 0x0 0x0 DTOCV Data Timeout Counter Value 16 4 read-write 0000 SDCLK x 213 #0000 0001 SDCLK x 214 #0001 1110 SDCLK x 227 #1110 1111 Reserved #1111 DVS Divisor 4 4 read-write 0 Divisor by 1 #0 1 Divisor by 2 #1 1110 Divisor by 15 #1110 1111 Divisor by 16 #1111 HCKEN System Clock Enable 1 1 read-write 0 System clock will be internally gated off #0 1 System clock will not be automatically gated off #1 INITA Initialization Active 27 1 read-write IPGEN IPG Clock Enable 0 1 read-write 0 Bus clock will be internally gated off #0 1 Bus clock will not be automatically gated off #1 PEREN Peripheral Clock Enable 2 1 read-write 0 SDHC clock will be internally gated off #0 1 SDHC clock will not be automatically gated off #1 RESERVED no description available 20 4 read-only RESERVED no description available 28 4 read-only RSTA Software Reset For ALL 24 1 write-only 0 No reset #0 1 Reset #1 RSTC Software Reset For CMD Line 25 1 write-only 0 No reset #0 1 Reset #1 RSTD Software Reset For DAT Line 26 1 write-only 0 No reset #0 1 Reset #1 SDCLKEN SD Clock Enable 3 1 read-write SDCLKFS SDCLK Frequency Select 8 8 read-write 1 Base clock divided by 2 #1 10 Base clock divided by 4 #10 100 Base clock divided by 8 #100 1000 Base clock divided by 16 #1000 10000 Base clock divided by 32 #10000 100000 Base clock divided by 64 #100000 1000000 Base clock divided by 128 #1000000 10000000 Base clock divided by 256 #10000000 VENDOR Vendor Specific Register 0xC0 32 read-write n 0x0 0x0 EXBLKNU Exact block number block read enable for SDIO CMD53 1 1 read-write 0 none exact block read. #0 1 Exact block read for SDIO CMD53. #1 EXTDMAEN External DMA Request Enable 0 1 read-write 0 In any scenario, SDHC does not send out external DMA request. #0 1 When internal DMA is not active, the external DMA request will be sent out. #1 INTSTVAL Internal State Value 16 8 read-only RESERVED no description available 2 14 read-only RESERVED no description available 24 4 read-only RESERVED no description available 28 4 read-only WML Watermark Level Register 0x44 32 read-write n 0x0 0x0 RDWML Read Watermark Level 0 8 read-write RESERVED no description available 8 5 read-only RESERVED no description available 13 3 read-only RESERVED no description available 29 3 read-only WRBRSTLEN no description available 24 5 read-only WRWML Write Watermark Level 16 8 read-write XFERTYP Transfer Type Register 0xC 32 read-write n 0x0 0x0 AC12EN Auto CMD12 Enable 2 1 read-write 0 Disable #0 1 Enable #1 BCEN Block Count Enable 1 1 read-write 0 Disable #0 1 Enable #1 CCCEN Command CRC Check Enable 19 1 read-write 0 Disable #0 1 Enable #1 CICEN Command Index Check Enable 20 1 read-write 0 Disable #0 1 Enable #1 CMDINX Command Index 24 6 read-write CMDTYP Command Type 22 2 read-write 00 Normal other commands #00 01 Suspend CMD52 for writing bus suspend in CCCR #01 10 Resume CMD52 for writing function select in CCCR #10 11 Abort CMD12, CMD52 for writing I/O abort in CCCR #11 DMAEN DMA Enable 0 1 read-write 0 Disable #0 1 Enable #1 DPSEL Data Present Select 21 1 read-write 0 No data present #0 1 Data present #1 DTDSEL Data Transfer Direction Select 4 1 read-write 0 Write (host to card) #0 1 Read (card to host) #1 MSBSEL Multi/Single Block Select 5 1 read-write 0 Single block #0 1 Multiple blocks #1 RESERVED no description available 3 1 read-only RESERVED no description available 6 10 read-only RESERVED no description available 18 1 read-only RESERVED no description available 30 2 read-only RSPTYP Response Type Select 16 2 read-write 00 No response #00 01 Response length 136 #01 10 Response length 48 #10 11 Response length 48, check busy after response #11 SIM System Integration Module SIM 0x0 0x0 0x1070 registers n CLKDIV1 System Clock Divider Register 1 0x1044 32 read-write n 0x0 0x0 OUTDIV1 Clock 1 output divider value 28 4 read-write 0000 Divide-by-1. #0000 0001 Divide-by-2. #0001 0010 Divide-by-3. #0010 0011 Divide-by-4. #0011 0100 Divide-by-5. #0100 0101 Divide-by-6. #0101 0110 Divide-by-7. #0110 0111 Divide-by-8. #0111 1000 Divide-by-9. #1000 1001 Divide-by-10. #1001 1010 Divide-by-11. #1010 1011 Divide-by-12. #1011 1100 Divide-by-13. #1100 1101 Divide-by-14. #1101 1110 Divide-by-15. #1110 1111 Divide-by-16. #1111 OUTDIV2 Clock 2 output divider value 24 4 read-write 0000 Divide-by-1. #0000 0001 Divide-by-2. #0001 0010 Divide-by-3. #0010 0011 Divide-by-4. #0011 0100 Divide-by-5. #0100 0101 Divide-by-6. #0101 0110 Divide-by-7. #0110 0111 Divide-by-8. #0111 1000 Divide-by-9. #1000 1001 Divide-by-10. #1001 1010 Divide-by-11. #1010 1011 Divide-by-12. #1011 1100 Divide-by-13. #1100 1101 Divide-by-14. #1101 1110 Divide-by-15. #1110 1111 Divide-by-16. #1111 OUTDIV3 Clock 3 output divider value 20 4 read-write 0000 Divide-by-1. #0000 0001 Divide-by-2. #0001 0010 Divide-by-3. #0010 0011 Divide-by-4. #0011 0100 Divide-by-5. #0100 0101 Divide-by-6. #0101 0110 Divide-by-7. #0110 0111 Divide-by-8. #0111 1000 Divide-by-9. #1000 1001 Divide-by-10. #1001 1010 Divide-by-11. #1010 1011 Divide-by-12. #1011 1100 Divide-by-13. #1100 1101 Divide-by-14. #1101 1110 Divide-by-15. #1110 1111 Divide-by-16. #1111 OUTDIV4 Clock 4 output divider value 16 4 read-write 0000 Divide-by-1. #0000 0001 Divide-by-2. #0001 0010 Divide-by-3. #0010 0011 Divide-by-4. #0011 0100 Divide-by-5. #0100 0101 Divide-by-6. #0101 0110 Divide-by-7. #0110 0111 Divide-by-8. #0111 1000 Divide-by-9. #1000 1001 Divide-by-10. #1001 1010 Divide-by-11. #1010 1011 Divide-by-12. #1011 1100 Divide-by-13. #1100 1101 Divide-by-14. #1101 1110 Divide-by-15. #1110 1111 Divide-by-16. #1111 RESERVED no description available 0 16 read-only CLKDIV2 System Clock Divider Register 2 0x1048 32 read-write n 0x0 0x0 RESERVED no description available 4 4 read-only RESERVED no description available 12 20 read-only USBFSDIV USB FS clock divider divisor 1 3 read-write USBFSFRAC USB FS clock divider fraction 0 1 read-write USBHSDIV USB HS clock divider divisor 9 3 read-write USBHSFRAC USB HS clock divider fraction 8 1 read-write CLKDIV4 System Clock Divider Register 4 0x1068 32 read-write n 0x0 0x0 NFCDIV NFC clock divider divisor 27 5 read-write NFCFRAC NFC clock divider fraction 24 3 read-write RESERVED no description available 4 20 read-only TRACEDIV Trace clock divider divisor 1 3 read-write TRACEFRAC Trace clock divider fraction 0 1 read-write FCFG1 Flash Configuration Register 1 0x104C 32 read-write n 0x0 0x0 DEPART FlexNVM partition 8 4 read-only EESIZE EEPROM size 16 4 read-only 0000 16 KB #0000 0001 8 KB #0001 0010 4 KB #0010 0011 2 KB #0011 0100 1 KB #0100 0101 512 Bytes #0101 0110 256 Bytes #0110 0111 128 Bytes #0111 1000 64 Bytes #1000 1001 32 Bytes #1001 1111 0 Bytes #1111 FTFDIS Disable FTFE 0 1 read-write NVMSIZE FlexNVM size 28 4 read-only 0000 0 KB #0000 0001 Reserved #0001 0010 Reserved #0010 0011 Reserved #0011 0100 Reserved #0100 0101 Reserved #0101 0110 Reserved #0110 0111 Reserved #0111 1000 Reserved #1000 1001 Reserved #1001 1010 Reserved #1010 1011 512 KB, 16 KB protection region #1011 1100 Reserved #1100 1101 Reserved #1101 1110 Reserved #1110 1111 512 KB, 16 KB protection region #1111 PFSIZE Program flash size 24 4 read-only 0000 Reserved #0000 0001 Reserved #0001 0010 Reserved #0010 0011 Reserved #0011 0100 Reserved #0100 0101 Reserved #0101 0110 Reserved #0110 0111 Reserved #0111 1000 Reserved #1000 1001 Reserved #1001 1010 Reserved #1010 1011 512 KB, 16 KB protection size #1011 1100 Reserved #1100 1101 1024 KB, 32 KB protection size #1101 1110 Reserved #1110 1111 1024 KB, 32 KB protection size #1111 RESERVED no description available 1 7 read-only RESERVED no description available 12 4 read-only RESERVED no description available 20 4 read-only FCFG2 Flash Configuration Register 2 0x1050 32 read-only n 0x0 0x0 MAXADDR01 Max address block 0 or 1 24 6 read-only MAXADDR23 Max address block 2 or 3 16 6 read-only RESERVED no description available 0 16 read-only RESERVED no description available 22 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 30 1 read-only RESERVED no description available 31 1 read-only MCR Misc Control Register 0x106C 32 read-write n 0x0 0x0 PDBLOOP PDB Loop Mode 29 1 read-write 0 Provides two seperated minor loop, loop for ADC0/1 and loop for ADC2/3D #0 1 Provides a loop to involve ADC0, ADC1, ADC2 and ADC3. #1 RESERVED no description available 0 4 read-only RESERVED no description available 4 1 write-only RESERVED no description available 5 3 read-write RESERVED no description available 8 2 read-only RESERVED no description available 10 6 read-only RESERVED no description available 16 1 read-only RESERVED no description available 17 12 read-only TRACECLKDIS Trace clock disable. 31 1 read-write 0 Enables trace clock. #0 1 Disable trace clock. #1 ULPICLKOBE 60 MHz ULPI clock (ULPI_CLK) output enable 30 1 read-write 0 Internal generated 60MHz ULPI clock is not output to the ULPI_CLK pin. #0 1 Interanl generated 60MHz ULPI clock provide clock for external ULPI phy. #1 SCGC1 System Clock Gating Control Register 1 0x1028 32 read-write n 0x0 0x0 OSC1 OSC1 clock gate control 5 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 RESERVED no description available 0 5 read-only RESERVED no description available 6 4 read-only RESERVED no description available 12 20 read-only UART4 UART4 clock gate control 10 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 UART5 UART5 clock gate control 11 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 SCGC2 System Clock Gating Control Register 2 0x102C 32 read-write n 0x0 0x0 DAC0 12BDAC0 clock gate control 12 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 DAC1 12BDAC1 clock gate control 13 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 ENET ENET clock gate control 0 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 RESERVED no description available 1 11 read-only RESERVED no description available 14 18 read-only SCGC3 System Clock Gating Control Register 3 0x1030 32 read-write n 0x0 0x0 ADC1 ADC1 clock gate control 27 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 ADC3 ADC3 clock gate control 28 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 DSPI2 DSPI2 clock gate control 12 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 ESDHC ESDHC clock gate control 17 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 FLEXCAN1 FlexCAN1 clock gate control 4 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 FTM2 FTM2 clock gate control 24 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 FTM3 FTM3 clock gate control 25 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 NFC NFC clock gate control 8 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 RESERVED no description available 1 3 read-only RESERVED no description available 5 3 read-only RESERVED no description available 9 3 read-only RESERVED no description available 13 1 read-only RESERVED no description available 14 1 read-only RESERVED no description available 16 1 read-only RESERVED no description available 18 4 read-only RESERVED no description available 22 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 26 1 read-only RESERVED no description available 29 3 read-only RNGA RNGA clock gate control 0 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 SAI1 SAI1 clock gate control 15 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 SCGC4 System Clock Gating Control Register 4 0x1034 32 read-write n 0x0 0x0 CMP Comparator clock gate control 19 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 CMT CMT clock gate control 2 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 EWM EWM clock gate control 1 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 IIC0 IIC0 clock gate control 6 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 IIC1 IIC1 clock gate control 7 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 LLWU LLWU Clock Gate Control 28 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 RESERVED no description available 0 1 read-only RESERVED no description available 3 1 read-only RESERVED no description available 4 1 read-only RESERVED no description available 5 1 read-only RESERVED no description available 8 2 read-only RESERVED no description available 14 4 read-only RESERVED no description available 21 7 read-only RESERVED no description available 29 1 read-only RESERVED no description available 30 1 read-only RESERVED no description available 31 1 read-only UART0 UART0 clock gate control 10 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 UART1 UART1 clock gate control 11 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 UART2 UART2 clock gate control 12 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 UART3 UART3 clock gate control 13 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 USBFS USB FS clock gate control 18 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 VREF VREF clock gate control 20 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 SCGC5 System Clock Gating Control Register 5 0x1038 32 read-write n 0x0 0x0 LPTIMER LPTMR clock gate control 0 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 PORTA PORTA clock gate control 9 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 PORTB PORTB clock gate control 10 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 PORTC PORTC clock gate control 11 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 PORTD PORTD clock gate control 12 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 PORTE PORTE clock gate control 13 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 PORTF PORTF clock gate control 14 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 REGFILE Register File Clock Gate Control 1 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 RESERVED no description available 2 1 read-only RESERVED no description available 3 1 read-only RESERVED no description available 4 1 read-only RESERVED no description available 6 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 8 1 read-only RESERVED no description available 15 3 read-only RESERVED no description available 18 1 read-only RESERVED no description available 19 13 read-only TSI TSI clock gate control 5 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 SCGC6 System Clock Gating Control Register 6 0x103C 32 read-write n 0x0 0x0 ADC0 ADC0 clock gate control 27 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 ADC2 ADC2 clock gate control 28 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 CRC CRC clock gate control 18 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 DMAMUX0 DMAMUX0 clock gate control 1 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 DMAMUX1 DMAMUX1 clock gate control 2 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 DSPI0 DSPI0 clock gate control 12 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 DSPI1 DSPI1 clock gate control 13 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 FLEXCAN0 FlexCAN0 clock gate control 4 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 FTM0 FTM0 clock gate control 24 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 FTM1 FTM1 clock gate control 25 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 PDB PDB clock gate control 22 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 PIT PIT clock gate control 23 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 RESERVED no description available 0 1 read-only RESERVED no description available 3 1 read-only RESERVED no description available 5 7 read-only RESERVED no description available 14 1 read-only RESERVED no description available 16 2 read-only RESERVED no description available 19 1 read-only RESERVED no description available 26 1 read-only RESERVED no description available 30 1 read-only RESERVED no description available 31 1 read-only RTC RTC clock gate control 29 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 SAI0 SAI0 clock gate control 15 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 USBDCD USB DCD clock gate control 21 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 USBHS USBHS clock gate control 20 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 SCGC7 System Clock Gating Control Register 7 0x1040 32 read-write n 0x0 0x0 DMA DMA controller clock gate control 1 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 FLEXBUS FlexBus controller clock gate control 0 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 MPU MPU clock gate control 2 1 read-write 0 Clock is disabled. #0 1 Clock is enabled. #1 RESERVED no description available 3 1 read-only RESERVED no description available 4 28 read-only SDID System Device Identification Register 0x1024 32 read-only n 0x0 0x0 FAMID Kinetis family identification 4 3 read-only 000 K10 #000 001 K20 #001 010 K61 #010 011 Reserved #011 100 K60 #100 101 K70 #101 110 Reserved #110 111 Reserved #111 PINID Pincount identification 0 4 read-only 0000 Reserved #0000 0001 Reserved #0001 0010 Reserved #0010 0011 Reserved #0011 0100 Reserved #0100 0101 Reserved #0101 0110 Reserved #0110 0111 Reserved #0111 1000 Reserved #1000 1001 Reserved #1001 1010 144-pin #1010 1011 Reserved #1011 1100 196-pin #1100 1101 Reserved #1101 1110 256-pin #1110 1111 Reserved #1111 RESERVED no description available 7 1 read-only RESERVED no description available 8 1 read-only RESERVED no description available 9 1 read-only RESERVED no description available 10 2 read-only RESERVED no description available 16 16 read-only REVID Device revision number 12 4 read-only SOPT1 System Options Register 1 0x0 32 read-write n 0x0 0x0 OSC32KSEL 32 kHz oscillator clock select 19 1 read-write 0 System oscillator (OSC32KCLK) #0 1 RTC oscillator #1 RAMSIZE RAM size 12 4 read-only 0000 Undefined #0000 0001 Undefined #0001 0010 Undefined #0010 0011 Undefined #0011 0100 Undefined #0100 0101 Undefined #0101 0110 Undefined #0110 0111 Undefined #0111 1000 Undefined #1000 1001 128 KB #1001 1010 Undefined #1010 1011 Undefined #1011 1100 Undefined #1100 1101 Undefined #1101 1110 Undefined #1110 1111 Undefined #1111 RESERVED no description available 0 6 read-only RESERVED no description available 6 2 read-only RESERVED no description available 8 2 read-only RESERVED no description available 10 2 read-only RESERVED no description available 16 3 read-only RESERVED no description available 20 9 read-only USBREGEN USB voltage regulator enable 31 1 read-write 0 USB voltage regulator is disabled. #0 1 USB voltage regulator is enabled #1 USBSSTBY USB voltage regulator in standby mode during Stop, VLPS, LLS or VLLS 30 1 read-write 0 USB voltage regulator not in standby during Stop, VLPS, LLS and VLLS modes. #0 1 USB voltage regulator in standby during Stop, VLPS, LLS and VLLS modes. #1 USBVSTBY USB voltage regulator in standby mode during VLPR or VLPW 29 1 read-write 0 USB voltage regulator not in standby during VLPR and VLPW modes. #0 1 USB voltage regulator in standby during VLPR and VLPW modes. #1 SOPT1CFG SOPT1 Configuration Register 0x4 32 read-write n 0x0 0x0 RESERVED no description available 0 24 read-only RESERVED no description available 27 5 read-only URWE USB voltage regulator enable write enable 24 1 read-write 0 SOPT1[USBREGEN] cannot be written. #0 1 SOPT1[USBREGEN] can be written. #1 USSWE USB voltage regulator stop standby write enable 26 1 read-write 0 SOPT1[USBSSTBY] cannot be written. #0 1 SOPT1[USBSSTBY] can be written. #1 UVSWE USB voltage regulator VLP standby write enable 25 1 read-write 0 SOPT1[USBVSTBY] cannot be written. #0 1 SOPT1[USBVSTBY] can be written. #1 SOPT2 System Options Register 2 0x1004 32 read-write n 0x0 0x0 CLKOUTSEL Clock out select 5 3 read-write 000 FlexBus clock (reset value) #000 001 Reserved #001 010 Flash ungated clock #010 011 LPO clock (1 kHz) #011 100 MCGIRCLK #100 101 RTC 32 kHz clock #101 110 OSC0ERCLK #110 111 OSC1ERCLK #111 CMTUARTPAD CMT/UART pad drive strength 11 1 read-write 0 Single-pad drive strength for CMT IRO or UART0_TXD. #0 1 Dual-pad drive strength for CMT IRO or UART0_TXD. #1 ESDHCSRC ESDHC perclk source select 28 2 read-write 00 Core/system clock #00 01 MCGPLLCLK/MCGFLLCLK selected by PLLFLLSEL[1:0] #01 10 OSC0ERCLK #10 11 External bypass clock (PTD11) #11 FBSL Flexbus security level 8 2 read-write 00 All off-chip accesses (op code and data) via the FlexBus are disallowed. #00 10 Off-chip op code accesses are disallowed. Data accesses are allowed. #10 11 Off-chip op code accesses and data accesses are allowed. #11 NFCSRC NFC Flash clock source select 30 2 read-write 00 Bus clock #00 01 MCGPLL0CLK #01 10 MCGPLL1CLK #10 11 OSC0ERCLK #11 NFC_CLKSEL NFC Flash clock select 15 1 read-write 0 Clock divider NFC clock #0 1 EXTAL1 clock. #1 PLLFLLSEL PLL/FLL clock select 16 2 read-write 00 MCGFLLCLK #00 01 MCGPLL0CLK #01 10 MCGPLL1CLK #10 11 System Platform clock #11 RESERVED no description available 0 2 read-only RESERVED no description available 10 1 read-only RESERVED no description available 13 1 read-only RESERVED no description available 14 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 20 2 read-only RESERVED no description available 24 2 read-only RESERVED no description available 26 2 read-only RTCCLKOUTSEL RTC clock out select 4 1 read-write 0 RTC 1 Hz clock drives RTC CLKOUT. #0 1 RTC 32 kHz oscillator drives RTC CLKOUT. #1 TRACECLKSEL Debug trace clock select 12 1 read-write 0 MCGCLKOUT #0 1 Core/system clock #1 USBFSRC USB FS clock source select 22 2 read-write 00 MCGPLLCLK/MCGFLLCLK selected by PLLFLLSEL[1:0] #00 01 MCGPLL0CLK #01 10 MCGPLL1CLK #10 11 OSC0ERCLK #11 USBF_CLKSEL USB FS clock select 18 1 read-write 0 External bypass clock (PTE26) #0 1 Clock divider USB FS clock #1 USBHSRC USB HS clock source select 2 2 read-write 00 Bus clock #00 01 MCGPLL0CLK #01 10 MCGPLL1CLK #10 11 OSC0ERCLK #11 SOPT4 System Options Register 4 0x100C 32 read-write n 0x0 0x0 FTM0CLKSEL FlexTimer 0 external clock pin select 24 1 read-write 0 FTM0 external clock driven by FTM CLKIN0 pin #0 1 FTM0 external clock driven by FTM CLKIN1 pin. #1 FTM0FLT0 FlexTimer 0 Fault 0 Select 0 1 read-write 0 FTM0_FLT0 drives FTM 0 fault 0. #0 1 CMP0 OUT drives FTM 0 fault 0. #1 FTM0FLT1 FlexTimer 0 Fault 1 Select 1 1 read-write 0 FTM0_FLT1 drives FTM 0 fault 1. #0 1 CMP1 OUT drives FTM 0 fault 1. #1 FTM0FLT2 FlexTimer 0 Fault 2 Select 2 1 read-write 0 FTM0_FLT2 drives FTM 0 fault 2. #0 1 CMP2 OUT drives FTM 0 fault 2. #1 FTM0FLT3 FlexTimer 0 Fault 3 Select. 3 1 read-write 0 FTM0_FLT3 drives FTM 0 fault 3. #0 1 CMP0 OUT drives FTM 0 fault 3. #1 FTM0TRG0SRC FlexTimer 0 hardware trigger 0 source select 28 1 read-write 0 CMP0 OUT drives FTM0 hardware trigger 0. #0 1 FTM1 channel match trigger drives FTM0 hardware trigger 0. #1 FTM0TRG1SRC FlexTimer 0 hardware trigger 1 source select 29 1 read-write 0 PDB output trigger 1 drives FTM0 hardware trigger 1. #0 1 FTM2 channel match trigger drives FTM0 hardware trigger 1. #1 FTM1CH0SRC FlexTimer 1 channel 0 input capture source select 18 2 read-write 00 FTM1_CH0 pin #00 01 CMP0 output #01 10 CMP1 output #10 11 USB SOF trigger #11 FTM1CLKSEL FlexTimer 1 external clock pin select 25 1 read-write 0 FTM1 external clock driven by FTM CLKIN0 pin. #0 1 FTM1 external clock driven by FTM CLKIN1 pin. #1 FTM1FLT0 FlexTimer 1 Fault 0 Select 4 1 read-write 0 FTM1_FLT0 drives FTM 1 fault 0. #0 1 CMP0 OUT drives FTM 1 fault 0. #1 FTM2CH0SRC FlexTimer 2 channel 0 input capture source select 20 2 read-write 00 FTM2_CH0 pin #00 01 CMP0 output #01 10 CMP1 output #10 11 Reserved #11 FTM2CLKSEL FlexTimer 2 external clock pin select 26 1 read-write 0 FTM2 external clock driven by FTM CLKIN0 pin. #0 1 FTM2 external clock driven by FTM CLKIN1 pin. #1 FTM2FLT0 FlexTimer 2 Fault 0 Select 8 1 read-write 0 FTM2_FLT0 drives FTM 2 fault 0. #0 1 CMP0 OUT drives FTM 2 fault 0. #1 FTM3CLKSEL FlexTimer 3 external clock pin select 27 1 read-write 0 FTM3 external clock driven by FTM CLKIN0 pin. #0 1 FTM3 external clock driven by FTM CLKIN1 pin . #1 FTM3FLT0 FlexTimer 3 Fault 0 Select. 12 1 read-write 0 FTM3_FLT0 drives FTM 2 fault 0. #0 1 CMP0 OUT drives FTM 2 fault 0. #1 FTM3TRG0SRC FlexTimer 3 hardware trigger 0 source select 30 1 read-write 0 CMP3 OUT drives FTM3 hardware trigger 0. #0 1 FTM1 channel match trigger drives FTM3 hardware trigger 0. #1 FTM3TRG1SRC FlexTimer 3 hardware trigger 1 source select 31 1 read-write 0 PDB output trigger 3 drives FTM3 hardware trigger 1. #0 1 FTM2 channel match trigger drives FTM3 hardware trigger 1. #1 RESERVED no description available 5 3 read-only RESERVED no description available 9 3 read-only RESERVED no description available 13 5 read-only RESERVED no description available 22 2 read-only SOPT5 System Options Register 5 0x1010 32 read-write n 0x0 0x0 RESERVED no description available 8 24 read-only UART0RXSRC UART0 receive data source select 2 2 read-write 00 UART0_RX pin #00 01 CMP0 #01 10 CMP1 #10 11 Reserved #11 UART0TXSRC UART0 transmit data source select 0 2 read-write 00 UART0_TX pin #00 01 UART0_TX pin modulated with FTM1 channel 0 output #01 10 UART0_TX pin modulated with FTM2 channel 0 output #10 11 Reserved #11 UART1RXSRC UART1 receive data source select 6 2 read-write 00 UART1_RX pin #00 01 CMP0 #01 10 CMP1 #10 11 Reserved #11 UART1TXSRC UART1 transmit data source select 4 2 read-write 00 UART1_TX pin #00 01 UART1_TX pin modulated with FTM1 channel 0 Output #01 10 UART1_TX pin modulated with FTM2 channel 0 Output #10 11 Reserved #11 SOPT6 System Options Register 6 0x1014 32 read-write n 0x0 0x0 MCC MCC 0 16 read-write PCR PCR 16 4 read-write RESERVED no description available 20 12 read-only SOPT7 System Options Register 7 0x1018 32 read-write n 0x0 0x0 ADC0ALTTRGEN ADC0 alternate trigger enable 7 1 read-write 0 PDB trigger selected for ADC0. #0 1 Alternate trigger selected for ADC0. #1 ADC0PRETRGSEL ADC0 pre-trigger select 4 1 read-write 0 Pre-trigger A selected for ADC0. #0 1 Pre-trigger B selected for ADC0. #1 ADC0TRGSEL ADC0 trigger select 0 4 read-write 0000 External trigger #0000 0001 High speed comparator 0 asynchronous interrupt #0001 0010 High speed comparator 1 asynchronous interrupt #0010 0011 High speed comparator 2 asynchronous interrupt #0011 0100 PIT trigger 0 #0100 0101 PIT trigger 1 #0101 0110 PIT trigger 2 #0110 0111 PIT trigger 3 #0111 1000 FTM0 trigger #1000 1001 FTM1 trigger #1001 1010 FTM2 trigger #1010 1011 FTM3 trigger #1011 1100 RTC alarm #1100 1101 RTC seconds #1101 1110 Low-power timer trigger #1110 1111 High speed comparator 3 asynchronous interrupt #1111 ADC1ALTTRGEN ADC1 alternate trigger enable 15 1 read-write 0 PDB trigger selected for ADC1. #0 1 Alternate trigger selected for ADC1. #1 ADC1PRETRGSEL ADC1 pre-trigger select 12 1 read-write 0 Pre-trigger A selected for ADC1. #0 1 Pre-trigger B selected for ADC1. #1 ADC1TRGSEL ADC1 trigger select 8 4 read-write 0000 External trigger #0000 0001 High speed comparator 0 asynchronous interrupt #0001 0010 High speed comparator 1 asynchronous interrupt #0010 0011 High speed comparator 2 asynchronous interrupt #0011 0100 PIT trigger 0 #0100 0101 PIT trigger 1 #0101 0110 PIT trigger 2 #0110 0111 PIT trigger 3 #0111 1000 FTM0 trigger #1000 1001 FTM1 trigger #1001 1010 FTM2 trigger #1010 1011 FTM3 trigger #1011 1100 RTC alarm #1100 1101 RTC seconds #1101 1110 Low-power timer trigger #1110 1111 High speed comparator 3 asynchronous interrupt #1111 ADC2ALTTRGEN ADC2 alternate trigger enable 23 1 read-write 0 PDB trigger selected for ADC2. #0 1 Alternate trigger selected for ADC2. #1 ADC2PRETRGSEL ADC2 pre-trigger select 20 1 read-write 0 Pre-trigger A selected for ADC2. #0 1 Pre-trigger B selected for ADC2. #1 ADC2TRGSEL ADC2 trigger select 16 4 read-write 0000 External trigger #0000 0001 High speed comparator 0 asynchronous interrupt #0001 0010 High speed comparator 1 asynchronous interrupt #0010 0011 High speed comparator 2 asynchronous interrupt #0011 0100 PIT trigger 0 #0100 0101 PIT trigger 1 #0101 0110 PIT trigger 2 #0110 0111 PIT trigger 3 #0111 1000 FTM0 trigger #1000 1001 FTM1 trigger #1001 1010 FTM2 trigger #1010 1011 FTM3 trigger #1011 1100 RTC alarm #1100 1101 RTC seconds #1101 1110 Low-power timer trigger #1110 1111 High speed comparator 3 asynchronous interrupt #1111 ADC3ALTTRGEN ADC3 alternate trigger enable 31 1 read-write 0 PDB trigger selected for ADC3. #0 1 Alternate trigger selected for ADC3. #1 ADC3PRETRGSEL ADC3 pre-trigger select 28 1 read-write 0 Pre-trigger A selected for ADC3. #0 1 Pre-trigger B selected for ADC3. #1 ADC3TRGSEL ADC3 trigger select 24 4 read-write 0000 External trigger #0000 0001 High speed comparator 0 asynchronous interrupt #0001 0010 High speed comparator 1 asynchronous interrupt #0010 0011 High speed comparator 2 asynchronous interrupt #0011 0100 PIT trigger 0 #0100 0101 PIT trigger 1 #0101 0110 PIT trigger 2 #0110 0111 PIT trigger 3 #0111 1000 FTM0 trigger #1000 1001 FTM1 trigger #1001 1010 FTM2 trigger #1010 1011 FTM3 trigger #1011 1100 RTC alarm #1100 1101 RTC seconds #1101 1110 Low-power timer trigger #1110 1111 High speed comparator 3 asynchronous interrupt #1111 RESERVED no description available 5 2 read-only RESERVED no description available 13 2 read-only RESERVED no description available 21 2 read-only RESERVED no description available 29 2 read-only UIDH Unique Identification Register High 0x1054 32 read-only n 0x0 0x0 UID Unique Identification 0 32 read-only UIDL Unique Identification Register Low 0x1060 32 read-only n 0x0 0x0 UID Unique Identification 0 32 read-only UIDMH Unique Identification Register Mid-High 0x1058 32 read-only n 0x0 0x0 UID Unique Identification 0 32 read-only UIDML Unique Identification Register Mid Low 0x105C 32 read-only n 0x0 0x0 UID Unique Identification 0 32 read-only SMC System Mode Controller SMC 0x0 0x0 0x4 registers n PMCTRL Power Mode Control Register 0x1 8 read-write n 0x0 0x0 LPWUI Low Power Wake Up on Interrupt 7 1 read-write 0 The system remains in a VLP mode on an interrupt #0 1 The system exits to normal RUN mode on an interrupt #1 RESERVED no description available 4 1 read-only RUNM Run Mode Control 5 2 read-write 00 Normal run mode (RUN) #00 01 Reserved #01 10 Very low power run mode (VLPR) #10 11 Reserved #11 STOPA Stop Aborted 3 1 read-only 0 The previous stop mode entry was successsful. #0 1 The previous stop mode entry was aborted. #1 STOPM Stop Mode Control 0 3 read-write 000 Normal stop (STOP) #000 001 Reserved #001 010 Very low power stop (VLPS) #010 011 Low leakage stop (LLS) #011 100 Very low leakage stop (VLLSx) #100 101 Reserved #101 110 Reseved #110 111 Reserved #111 PMPROT Power Mode Protection Register 0x0 8 read-write n 0x0 0x0 ALLS Allow low leakage stop mode 3 1 read-write 0 LLS is not allowed #0 1 LLS is allowed #1 AVLLS Allow very low leakage stop mode 1 1 read-write 0 Any VLLSx mode is not allowed #0 1 Any VLLSx mode is allowed #1 AVLP Allow very low power modes 5 1 read-write 0 VLPR, VLPW and VLPS are not allowed #0 1 VLPR, VLPW and VLPS are allowed #1 RESERVED no description available 0 1 read-only RESERVED no description available 2 1 read-only RESERVED no description available 4 1 read-only RESERVED no description available 6 2 read-only PMSTAT Power Mode Status Register 0x3 8 read-only n 0x0 0x0 PMSTAT no description available 0 7 read-only RESERVED no description available 7 1 read-only VLLSCTRL VLLS Control Register 0x2 8 read-write n 0x0 0x0 RESERVED no description available 3 1 read-only RESERVED no description available 4 1 read-only RESERVED no description available 5 1 read-only RESERVED no description available 6 2 read-only VLLSM VLLS Mode Control 0 3 read-write 000 Reserved #000 001 VLLS1 #001 010 VLLS2 #010 011 VLLS3 #011 100 Reserved #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 SPI0 Deserial Serial Peripheral Interface SPI 0x0 0x0 0x8C registers n SPI0 26 INT_SPI0 42 CTAR0 DSPI Clock and Transfer Attributes Register (In Master Mode) SPI0 0x18 32 read-write n 0x0 0x0 ASC After SCK Delay Scaler 8 4 read-write BR Baud Rate Scaler 0 4 read-write CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 CSSCK PCS to SCK Delay Scaler 12 4 read-write DBR Double Baud Rate 31 1 read-write 0 The baud rate is computed normally with a 50/50 duty cycle. #0 1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. #1 DT Delay After Transfer Scaler 4 4 read-write FMSZ Frame Size 27 4 read-write LSBFE LSB First 24 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 PASC After SCK Delay Prescaler 20 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PBR Baud Rate Prescaler 16 2 read-write 00 Baud Rate Prescaler value is 2. #00 01 Baud Rate Prescaler value is 3. #01 10 Baud Rate Prescaler value is 5. #10 11 Baud Rate Prescaler value is 7. #11 PCSSCK PCS to SCK Delay Prescaler 22 2 read-write 00 PCS to SCK Prescaler value is 1. #00 01 PCS to SCK Prescaler value is 3. #01 10 PCS to SCK Prescaler value is 5. #10 11 PCS to SCK Prescaler value is 7. #11 PDT Delay after Transfer Prescaler 18 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 CTAR1 DSPI Clock and Transfer Attributes Register (In Master Mode) SPI0 0x28 32 read-write n 0x0 0x0 ASC After SCK Delay Scaler 8 4 read-write BR Baud Rate Scaler 0 4 read-write CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 CSSCK PCS to SCK Delay Scaler 12 4 read-write DBR Double Baud Rate 31 1 read-write 0 The baud rate is computed normally with a 50/50 duty cycle. #0 1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. #1 DT Delay After Transfer Scaler 4 4 read-write FMSZ Frame Size 27 4 read-write LSBFE LSB First 24 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 PASC After SCK Delay Prescaler 20 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PBR Baud Rate Prescaler 16 2 read-write 00 Baud Rate Prescaler value is 2. #00 01 Baud Rate Prescaler value is 3. #01 10 Baud Rate Prescaler value is 5. #10 11 Baud Rate Prescaler value is 7. #11 PCSSCK PCS to SCK Delay Prescaler 22 2 read-write 00 PCS to SCK Prescaler value is 1. #00 01 PCS to SCK Prescaler value is 3. #01 10 PCS to SCK Prescaler value is 5. #10 11 PCS to SCK Prescaler value is 7. #11 PDT Delay after Transfer Prescaler 18 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 CTAR_SLAVE DSPI Clock and Transfer Attributes Register (In Slave Mode) SPI0 0xC 32 read-write n 0x0 0x0 CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 FMSZ Frame Size 27 5 read-write RESERVED no description available 0 22 read-only RESERVED no description available 22 1 read-only RESERVED no description available 23 2 read-only MCR DSPI Module Configuration Register 0x0 32 read-write n 0x0 0x0 CLR_RXF no description available 10 1 write-only 0 Do not clear the Rx FIFO counter. #0 1 Clear the Rx FIFO counter. #1 CLR_TXF Clear TX FIFO 11 1 write-only 0 Do not clear the Tx FIFO counter. #0 1 Clear the Tx FIFO counter. #1 CONT_SCKE Continuous SCK Enable 30 1 read-write 0 Continuous SCK disabled. #0 1 Continuous SCK enabled. #1 DCONF DSPI Configuration 28 2 read-write 00 SPI #00 01 Reserved #01 10 Reserved #10 11 Reserved #11 DIS_RXF Disable Receive FIFO 12 1 read-write 0 Rx FIFO is enabled. #0 1 Rx FIFO is disabled. #1 DIS_TXF Disable Transmit FIFO 13 1 read-write 0 Tx FIFO is enabled. #0 1 Tx FIFO is disabled. #1 DOZE Doze Enable 15 1 read-write 0 Doze mode has no effect on DSPI. #0 1 Doze mode disables DSPI. #1 FRZ Freeze 27 1 read-write 0 Do not halt serial transfers in debug mode. #0 1 Halt serial transfers in debug mode. #1 HALT Halt 0 1 read-write 0 Start transfers. #0 1 Stop transfers. #1 MDIS Module Disable 14 1 read-write 0 Enable DSPI clocks. #0 1 Allow external logic to disable DSPI clocks. #1 MSTR Master/Slave Mode Select 31 1 read-write 0 DSPI is in slave mode. #0 1 DSPI is in master mode. #1 MTFE Modified Timing Format Enable 26 1 read-write 0 Modified SPI transfer format disabled. #0 1 Modified SPI transfer format enabled. #1 PCSIS Peripheral Chip Select x Inactive State 16 6 read-write 0 The inactive state of PCSx is low. #0 1 The inactive state of PCSx is high. #1 PCSSE Peripheral Chip Select Strobe Enable 25 1 read-write 0 PCS[5]/PCSS is used as the Peripheral Chip Select[5] signal. #0 1 PCS[5]/PCSS is used as an active-low PCS Strobe signal. #1 RESERVED no description available 1 1 read-only RESERVED no description available 2 1 read-only RESERVED no description available 3 5 read-only RESERVED no description available 22 2 read-only ROOE Receive FIFO Overflow Overwrite Enable 24 1 read-write 0 Incoming data is ignored. #0 1 Incoming data is shifted into the shift register. #1 SMPL_PT Sample Point 8 2 read-write 00 0 system clocks between SCK edge and SIN sample #00 01 1 system clock between SCK edge and SIN sample #01 10 2 system clocks between SCK edge and SIN sample #10 11 Reserved #11 POPR DSPI POP RX FIFO Register 0x38 32 read-only n 0x0 0x0 RXDATA Received Data 0 32 read-only PUSHR DSPI PUSH TX FIFO Register In Master Mode SPI0 0x34 32 read-write n 0x0 0x0 CONT Continuous Peripheral Chip Select Enable 31 1 read-write 0 Return PCSn signals to their inactive state between transfers. #0 1 Keep PCSn signals asserted between transfers. #1 CTAS Clock and Transfer Attributes Select. 28 3 read-write 000 CTAR0 #000 001 CTAR1 #001 010 Reserved #010 011 Reserved #011 100 Reserved #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 CTCNT Clear Transfer Counter. 26 1 read-write 0 Do not clear the TCR[SPI_TCNT] field. #0 1 Clear the TCR[SPI_TCNT] field. #1 EOQ End Of Queue 27 1 read-write 0 The SPI data is not the last data to transfer. #0 1 The SPI data is the last data to transfer. #1 PCS no description available 16 6 read-write 0 Negate the PCS[x] signal. #0 1 Assert the PCS[x] signal. #1 RESERVED no description available 22 2 read-only RESERVED no description available 24 2 read-only TXDATA Transmit Data 0 16 read-write PUSHR_SLAVE DSPI PUSH TX FIFO Register In Slave Mode SPI0 0x34 32 read-write n 0x0 0x0 RESERVED no description available 16 16 read-only TXDATA Transmit Data 0 16 read-write RSER DSPI DMA/Interrupt Request Select and Enable Register 0x30 32 read-write n 0x0 0x0 EOQF_RE DSPI Finished Request Enable 28 1 read-write 0 EOQF interrupt requests are disabled. #0 1 EOQF interrupt requests are enabled. #1 RESERVED no description available 0 14 read-only RESERVED no description available 14 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 18 1 read-only RESERVED no description available 20 1 read-only RESERVED no description available 21 1 read-only RESERVED no description available 22 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 26 1 read-only RESERVED no description available 29 1 read-only RESERVED no description available 30 1 read-only RFDF_DIRS Receive FIFO Drain DMA or Interrupt Request Select. 16 1 read-write 0 Interrupt request. #0 1 DMA request. #1 RFDF_RE Receive FIFO Drain Request Enable 17 1 read-write 0 RFDF interrupt or DMA requests are disabled #0 1 RFDF interrupt or DMA requests are enabled #1 RFOF_RE Receive FIFO Overflow Request Enable 19 1 read-write 0 RFOF interrupt requests are disabled. #0 1 RFOF interrupt requests are enabled. #1 TCF_RE Transmission Complete Request Enable 31 1 read-write 0 TCF interrupt requests are disabled. #0 1 TCF interrupt requests are enabled. #1 TFFF_DIRS Transmit FIFO Fill DMA or Interrupt Request Select 24 1 read-write 0 TFFF flag generates interrupt requests. #0 1 TFFF flag generates DMA requests. #1 TFFF_RE Transmit FIFO Fill Request Enable 25 1 read-write 0 TFFF interrupts or DMA requests are disabled. #0 1 TFFF interrupts or DMA requests are enabled. #1 TFUF_RE Transmit FIFO Underflow Request Enable 27 1 read-write 0 TFUF interrupt requests are disabled. #0 1 TFUF interrupt requests are enabled. #1 RXFR0 DSPI Receive FIFO Registers 0xF8 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only RXFR1 DSPI Receive FIFO Registers 0x178 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only RXFR2 DSPI Receive FIFO Registers 0x1FC 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only RXFR3 DSPI Receive FIFO Registers 0x284 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only SR DSPI Status Register 0x2C 32 read-write n 0x0 0x0 EOQF End of Queue Flag 28 1 read-write 0 EOQ is not set in the executing command. #0 1 EOQ is set in the executing SPI command. #1 POPNXTPTR Pop Next Pointer 0 4 read-only RESERVED no description available 16 1 read-only RESERVED no description available 18 1 read-only RESERVED no description available 20 1 read-only RESERVED no description available 21 1 read-only RESERVED no description available 22 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 24 1 read-only RESERVED no description available 26 1 read-only RESERVED no description available 29 1 read-only RFDF Receive FIFO Drain Flag 17 1 read-write 0 Rx FIFO is empty. #0 1 Rx FIFO is not empty. #1 RFOF Receive FIFO Overflow Flag 19 1 read-write 0 No Rx FIFO overflow. #0 1 Rx FIFO overflow has occurred. #1 RXCTR RX FIFO Counter 4 4 read-only TCF Transfer Complete Flag 31 1 read-write 0 Transfer not complete. #0 1 Transfer complete. #1 TFFF Transmit FIFO Fill Flag 25 1 read-write 0 Tx FIFO is full. #0 1 Tx FIFO is not full. #1 TFUF Transmit FIFO Underflow Flag 27 1 read-write 0 No Tx FIFO underflow. #0 1 Tx FIFO underflow has occurred. #1 TXCTR TX FIFO Counter 12 4 read-only TXNXTPTR Transmit Next Pointer 8 4 read-only TXRXS TX and RX Status 30 1 read-write 0 Transmit and receive operations are disabled (DSPI is in stopped state). #0 1 Transmit and receive operations are enabled (DSPI is in running state). #1 TCR DSPI Transfer Count Register 0x8 32 read-write n 0x0 0x0 RESERVED no description available 0 16 read-only SPI_TCNT SPI Transfer Counter 16 16 read-write TXFR0 DSPI Transmit FIFO Registers 0x78 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TXFR1 DSPI Transmit FIFO Registers 0xB8 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TXFR2 DSPI Transmit FIFO Registers 0xFC 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TXFR3 DSPI Transmit FIFO Registers 0x144 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only SPI1 Deserial Serial Peripheral Interface SPI 0x0 0x0 0x8C registers n SPI1 27 INT_SPI1 43 CTAR0 DSPI Clock and Transfer Attributes Register (In Master Mode) SPI1 0x18 32 read-write n 0x0 0x0 ASC After SCK Delay Scaler 8 4 read-write BR Baud Rate Scaler 0 4 read-write CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 CSSCK PCS to SCK Delay Scaler 12 4 read-write DBR Double Baud Rate 31 1 read-write 0 The baud rate is computed normally with a 50/50 duty cycle. #0 1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. #1 DT Delay After Transfer Scaler 4 4 read-write FMSZ Frame Size 27 4 read-write LSBFE LSB First 24 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 PASC After SCK Delay Prescaler 20 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PBR Baud Rate Prescaler 16 2 read-write 00 Baud Rate Prescaler value is 2. #00 01 Baud Rate Prescaler value is 3. #01 10 Baud Rate Prescaler value is 5. #10 11 Baud Rate Prescaler value is 7. #11 PCSSCK PCS to SCK Delay Prescaler 22 2 read-write 00 PCS to SCK Prescaler value is 1. #00 01 PCS to SCK Prescaler value is 3. #01 10 PCS to SCK Prescaler value is 5. #10 11 PCS to SCK Prescaler value is 7. #11 PDT Delay after Transfer Prescaler 18 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 CTAR1 DSPI Clock and Transfer Attributes Register (In Master Mode) SPI1 0x28 32 read-write n 0x0 0x0 ASC After SCK Delay Scaler 8 4 read-write BR Baud Rate Scaler 0 4 read-write CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 CSSCK PCS to SCK Delay Scaler 12 4 read-write DBR Double Baud Rate 31 1 read-write 0 The baud rate is computed normally with a 50/50 duty cycle. #0 1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. #1 DT Delay After Transfer Scaler 4 4 read-write FMSZ Frame Size 27 4 read-write LSBFE LSB First 24 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 PASC After SCK Delay Prescaler 20 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PBR Baud Rate Prescaler 16 2 read-write 00 Baud Rate Prescaler value is 2. #00 01 Baud Rate Prescaler value is 3. #01 10 Baud Rate Prescaler value is 5. #10 11 Baud Rate Prescaler value is 7. #11 PCSSCK PCS to SCK Delay Prescaler 22 2 read-write 00 PCS to SCK Prescaler value is 1. #00 01 PCS to SCK Prescaler value is 3. #01 10 PCS to SCK Prescaler value is 5. #10 11 PCS to SCK Prescaler value is 7. #11 PDT Delay after Transfer Prescaler 18 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 CTAR_SLAVE DSPI Clock and Transfer Attributes Register (In Slave Mode) SPI1 0xC 32 read-write n 0x0 0x0 CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 FMSZ Frame Size 27 5 read-write RESERVED no description available 0 22 read-only RESERVED no description available 22 1 read-only RESERVED no description available 23 2 read-only MCR DSPI Module Configuration Register 0x0 32 read-write n 0x0 0x0 CLR_RXF no description available 10 1 write-only 0 Do not clear the Rx FIFO counter. #0 1 Clear the Rx FIFO counter. #1 CLR_TXF Clear TX FIFO 11 1 write-only 0 Do not clear the Tx FIFO counter. #0 1 Clear the Tx FIFO counter. #1 CONT_SCKE Continuous SCK Enable 30 1 read-write 0 Continuous SCK disabled. #0 1 Continuous SCK enabled. #1 DCONF DSPI Configuration 28 2 read-write 00 SPI #00 01 Reserved #01 10 Reserved #10 11 Reserved #11 DIS_RXF Disable Receive FIFO 12 1 read-write 0 Rx FIFO is enabled. #0 1 Rx FIFO is disabled. #1 DIS_TXF Disable Transmit FIFO 13 1 read-write 0 Tx FIFO is enabled. #0 1 Tx FIFO is disabled. #1 DOZE Doze Enable 15 1 read-write 0 Doze mode has no effect on DSPI. #0 1 Doze mode disables DSPI. #1 FRZ Freeze 27 1 read-write 0 Do not halt serial transfers in debug mode. #0 1 Halt serial transfers in debug mode. #1 HALT Halt 0 1 read-write 0 Start transfers. #0 1 Stop transfers. #1 MDIS Module Disable 14 1 read-write 0 Enable DSPI clocks. #0 1 Allow external logic to disable DSPI clocks. #1 MSTR Master/Slave Mode Select 31 1 read-write 0 DSPI is in slave mode. #0 1 DSPI is in master mode. #1 MTFE Modified Timing Format Enable 26 1 read-write 0 Modified SPI transfer format disabled. #0 1 Modified SPI transfer format enabled. #1 PCSIS Peripheral Chip Select x Inactive State 16 6 read-write 0 The inactive state of PCSx is low. #0 1 The inactive state of PCSx is high. #1 PCSSE Peripheral Chip Select Strobe Enable 25 1 read-write 0 PCS[5]/PCSS is used as the Peripheral Chip Select[5] signal. #0 1 PCS[5]/PCSS is used as an active-low PCS Strobe signal. #1 RESERVED no description available 1 1 read-only RESERVED no description available 2 1 read-only RESERVED no description available 3 5 read-only RESERVED no description available 22 2 read-only ROOE Receive FIFO Overflow Overwrite Enable 24 1 read-write 0 Incoming data is ignored. #0 1 Incoming data is shifted into the shift register. #1 SMPL_PT Sample Point 8 2 read-write 00 0 system clocks between SCK edge and SIN sample #00 01 1 system clock between SCK edge and SIN sample #01 10 2 system clocks between SCK edge and SIN sample #10 11 Reserved #11 POPR DSPI POP RX FIFO Register 0x38 32 read-only n 0x0 0x0 RXDATA Received Data 0 32 read-only PUSHR DSPI PUSH TX FIFO Register In Master Mode SPI1 0x34 32 read-write n 0x0 0x0 CONT Continuous Peripheral Chip Select Enable 31 1 read-write 0 Return PCSn signals to their inactive state between transfers. #0 1 Keep PCSn signals asserted between transfers. #1 CTAS Clock and Transfer Attributes Select. 28 3 read-write 000 CTAR0 #000 001 CTAR1 #001 010 Reserved #010 011 Reserved #011 100 Reserved #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 CTCNT Clear Transfer Counter. 26 1 read-write 0 Do not clear the TCR[SPI_TCNT] field. #0 1 Clear the TCR[SPI_TCNT] field. #1 EOQ End Of Queue 27 1 read-write 0 The SPI data is not the last data to transfer. #0 1 The SPI data is the last data to transfer. #1 PCS no description available 16 6 read-write 0 Negate the PCS[x] signal. #0 1 Assert the PCS[x] signal. #1 RESERVED no description available 22 2 read-only RESERVED no description available 24 2 read-only TXDATA Transmit Data 0 16 read-write PUSHR_SLAVE DSPI PUSH TX FIFO Register In Slave Mode SPI1 0x34 32 read-write n 0x0 0x0 RESERVED no description available 16 16 read-only TXDATA Transmit Data 0 16 read-write RSER DSPI DMA/Interrupt Request Select and Enable Register 0x30 32 read-write n 0x0 0x0 EOQF_RE DSPI Finished Request Enable 28 1 read-write 0 EOQF interrupt requests are disabled. #0 1 EOQF interrupt requests are enabled. #1 RESERVED no description available 0 14 read-only RESERVED no description available 14 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 18 1 read-only RESERVED no description available 20 1 read-only RESERVED no description available 21 1 read-only RESERVED no description available 22 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 26 1 read-only RESERVED no description available 29 1 read-only RESERVED no description available 30 1 read-only RFDF_DIRS Receive FIFO Drain DMA or Interrupt Request Select. 16 1 read-write 0 Interrupt request. #0 1 DMA request. #1 RFDF_RE Receive FIFO Drain Request Enable 17 1 read-write 0 RFDF interrupt or DMA requests are disabled #0 1 RFDF interrupt or DMA requests are enabled #1 RFOF_RE Receive FIFO Overflow Request Enable 19 1 read-write 0 RFOF interrupt requests are disabled. #0 1 RFOF interrupt requests are enabled. #1 TCF_RE Transmission Complete Request Enable 31 1 read-write 0 TCF interrupt requests are disabled. #0 1 TCF interrupt requests are enabled. #1 TFFF_DIRS Transmit FIFO Fill DMA or Interrupt Request Select 24 1 read-write 0 TFFF flag generates interrupt requests. #0 1 TFFF flag generates DMA requests. #1 TFFF_RE Transmit FIFO Fill Request Enable 25 1 read-write 0 TFFF interrupts or DMA requests are disabled. #0 1 TFFF interrupts or DMA requests are enabled. #1 TFUF_RE Transmit FIFO Underflow Request Enable 27 1 read-write 0 TFUF interrupt requests are disabled. #0 1 TFUF interrupt requests are enabled. #1 RXFR0 DSPI Receive FIFO Registers 0xF8 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only RXFR1 DSPI Receive FIFO Registers 0x178 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only RXFR2 DSPI Receive FIFO Registers 0x1FC 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only RXFR3 DSPI Receive FIFO Registers 0x284 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only SR DSPI Status Register 0x2C 32 read-write n 0x0 0x0 EOQF End of Queue Flag 28 1 read-write 0 EOQ is not set in the executing command. #0 1 EOQ is set in the executing SPI command. #1 POPNXTPTR Pop Next Pointer 0 4 read-only RESERVED no description available 16 1 read-only RESERVED no description available 18 1 read-only RESERVED no description available 20 1 read-only RESERVED no description available 21 1 read-only RESERVED no description available 22 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 24 1 read-only RESERVED no description available 26 1 read-only RESERVED no description available 29 1 read-only RFDF Receive FIFO Drain Flag 17 1 read-write 0 Rx FIFO is empty. #0 1 Rx FIFO is not empty. #1 RFOF Receive FIFO Overflow Flag 19 1 read-write 0 No Rx FIFO overflow. #0 1 Rx FIFO overflow has occurred. #1 RXCTR RX FIFO Counter 4 4 read-only TCF Transfer Complete Flag 31 1 read-write 0 Transfer not complete. #0 1 Transfer complete. #1 TFFF Transmit FIFO Fill Flag 25 1 read-write 0 Tx FIFO is full. #0 1 Tx FIFO is not full. #1 TFUF Transmit FIFO Underflow Flag 27 1 read-write 0 No Tx FIFO underflow. #0 1 Tx FIFO underflow has occurred. #1 TXCTR TX FIFO Counter 12 4 read-only TXNXTPTR Transmit Next Pointer 8 4 read-only TXRXS TX and RX Status 30 1 read-write 0 Transmit and receive operations are disabled (DSPI is in stopped state). #0 1 Transmit and receive operations are enabled (DSPI is in running state). #1 TCR DSPI Transfer Count Register 0x8 32 read-write n 0x0 0x0 RESERVED no description available 0 16 read-only SPI_TCNT SPI Transfer Counter 16 16 read-write TXFR0 DSPI Transmit FIFO Registers 0x78 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TXFR1 DSPI Transmit FIFO Registers 0xB8 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TXFR2 DSPI Transmit FIFO Registers 0xFC 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TXFR3 DSPI Transmit FIFO Registers 0x144 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only SPI2 Deserial Serial Peripheral Interface SPI 0x0 0x0 0x8C registers n SPI2 28 INT_SPI2 44 CTAR0 DSPI Clock and Transfer Attributes Register (In Master Mode) SPI2 0x18 32 read-write n 0x0 0x0 ASC After SCK Delay Scaler 8 4 read-write BR Baud Rate Scaler 0 4 read-write CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 CSSCK PCS to SCK Delay Scaler 12 4 read-write DBR Double Baud Rate 31 1 read-write 0 The baud rate is computed normally with a 50/50 duty cycle. #0 1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. #1 DT Delay After Transfer Scaler 4 4 read-write FMSZ Frame Size 27 4 read-write LSBFE LSB First 24 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 PASC After SCK Delay Prescaler 20 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PBR Baud Rate Prescaler 16 2 read-write 00 Baud Rate Prescaler value is 2. #00 01 Baud Rate Prescaler value is 3. #01 10 Baud Rate Prescaler value is 5. #10 11 Baud Rate Prescaler value is 7. #11 PCSSCK PCS to SCK Delay Prescaler 22 2 read-write 00 PCS to SCK Prescaler value is 1. #00 01 PCS to SCK Prescaler value is 3. #01 10 PCS to SCK Prescaler value is 5. #10 11 PCS to SCK Prescaler value is 7. #11 PDT Delay after Transfer Prescaler 18 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 CTAR1 DSPI Clock and Transfer Attributes Register (In Master Mode) SPI2 0x28 32 read-write n 0x0 0x0 ASC After SCK Delay Scaler 8 4 read-write BR Baud Rate Scaler 0 4 read-write CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 CSSCK PCS to SCK Delay Scaler 12 4 read-write DBR Double Baud Rate 31 1 read-write 0 The baud rate is computed normally with a 50/50 duty cycle. #0 1 The baud rate is doubled with the duty cycle depending on the Baud Rate Prescaler. #1 DT Delay After Transfer Scaler 4 4 read-write FMSZ Frame Size 27 4 read-write LSBFE LSB First 24 1 read-write 0 Data is transferred MSB first. #0 1 Data is transferred LSB first. #1 PASC After SCK Delay Prescaler 20 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 PBR Baud Rate Prescaler 16 2 read-write 00 Baud Rate Prescaler value is 2. #00 01 Baud Rate Prescaler value is 3. #01 10 Baud Rate Prescaler value is 5. #10 11 Baud Rate Prescaler value is 7. #11 PCSSCK PCS to SCK Delay Prescaler 22 2 read-write 00 PCS to SCK Prescaler value is 1. #00 01 PCS to SCK Prescaler value is 3. #01 10 PCS to SCK Prescaler value is 5. #10 11 PCS to SCK Prescaler value is 7. #11 PDT Delay after Transfer Prescaler 18 2 read-write 00 Delay after Transfer Prescaler value is 1. #00 01 Delay after Transfer Prescaler value is 3. #01 10 Delay after Transfer Prescaler value is 5. #10 11 Delay after Transfer Prescaler value is 7. #11 CTAR_SLAVE DSPI Clock and Transfer Attributes Register (In Slave Mode) SPI2 0xC 32 read-write n 0x0 0x0 CPHA Clock Phase 25 1 read-write 0 Data is captured on the leading edge of SCK and changed on the following edge. #0 1 Data is changed on the leading edge of SCK and captured on the following edge. #1 CPOL Clock Polarity 26 1 read-write 0 The inactive state value of SCK is low. #0 1 The inactive state value of SCK is high. #1 FMSZ Frame Size 27 5 read-write RESERVED no description available 0 22 read-only RESERVED no description available 22 1 read-only RESERVED no description available 23 2 read-only MCR DSPI Module Configuration Register 0x0 32 read-write n 0x0 0x0 CLR_RXF no description available 10 1 write-only 0 Do not clear the Rx FIFO counter. #0 1 Clear the Rx FIFO counter. #1 CLR_TXF Clear TX FIFO 11 1 write-only 0 Do not clear the Tx FIFO counter. #0 1 Clear the Tx FIFO counter. #1 CONT_SCKE Continuous SCK Enable 30 1 read-write 0 Continuous SCK disabled. #0 1 Continuous SCK enabled. #1 DCONF DSPI Configuration 28 2 read-write 00 SPI #00 01 Reserved #01 10 Reserved #10 11 Reserved #11 DIS_RXF Disable Receive FIFO 12 1 read-write 0 Rx FIFO is enabled. #0 1 Rx FIFO is disabled. #1 DIS_TXF Disable Transmit FIFO 13 1 read-write 0 Tx FIFO is enabled. #0 1 Tx FIFO is disabled. #1 DOZE Doze Enable 15 1 read-write 0 Doze mode has no effect on DSPI. #0 1 Doze mode disables DSPI. #1 FRZ Freeze 27 1 read-write 0 Do not halt serial transfers in debug mode. #0 1 Halt serial transfers in debug mode. #1 HALT Halt 0 1 read-write 0 Start transfers. #0 1 Stop transfers. #1 MDIS Module Disable 14 1 read-write 0 Enable DSPI clocks. #0 1 Allow external logic to disable DSPI clocks. #1 MSTR Master/Slave Mode Select 31 1 read-write 0 DSPI is in slave mode. #0 1 DSPI is in master mode. #1 MTFE Modified Timing Format Enable 26 1 read-write 0 Modified SPI transfer format disabled. #0 1 Modified SPI transfer format enabled. #1 PCSIS Peripheral Chip Select x Inactive State 16 6 read-write 0 The inactive state of PCSx is low. #0 1 The inactive state of PCSx is high. #1 PCSSE Peripheral Chip Select Strobe Enable 25 1 read-write 0 PCS[5]/PCSS is used as the Peripheral Chip Select[5] signal. #0 1 PCS[5]/PCSS is used as an active-low PCS Strobe signal. #1 RESERVED no description available 1 1 read-only RESERVED no description available 2 1 read-only RESERVED no description available 3 5 read-only RESERVED no description available 22 2 read-only ROOE Receive FIFO Overflow Overwrite Enable 24 1 read-write 0 Incoming data is ignored. #0 1 Incoming data is shifted into the shift register. #1 SMPL_PT Sample Point 8 2 read-write 00 0 system clocks between SCK edge and SIN sample #00 01 1 system clock between SCK edge and SIN sample #01 10 2 system clocks between SCK edge and SIN sample #10 11 Reserved #11 POPR DSPI POP RX FIFO Register 0x38 32 read-only n 0x0 0x0 RXDATA Received Data 0 32 read-only PUSHR DSPI PUSH TX FIFO Register In Master Mode SPI2 0x34 32 read-write n 0x0 0x0 CONT Continuous Peripheral Chip Select Enable 31 1 read-write 0 Return PCSn signals to their inactive state between transfers. #0 1 Keep PCSn signals asserted between transfers. #1 CTAS Clock and Transfer Attributes Select. 28 3 read-write 000 CTAR0 #000 001 CTAR1 #001 010 Reserved #010 011 Reserved #011 100 Reserved #100 101 Reserved #101 110 Reserved #110 111 Reserved #111 CTCNT Clear Transfer Counter. 26 1 read-write 0 Do not clear the TCR[SPI_TCNT] field. #0 1 Clear the TCR[SPI_TCNT] field. #1 EOQ End Of Queue 27 1 read-write 0 The SPI data is not the last data to transfer. #0 1 The SPI data is the last data to transfer. #1 PCS no description available 16 6 read-write 0 Negate the PCS[x] signal. #0 1 Assert the PCS[x] signal. #1 RESERVED no description available 22 2 read-only RESERVED no description available 24 2 read-only TXDATA Transmit Data 0 16 read-write PUSHR_SLAVE DSPI PUSH TX FIFO Register In Slave Mode SPI2 0x34 32 read-write n 0x0 0x0 RESERVED no description available 16 16 read-only TXDATA Transmit Data 0 16 read-write RSER DSPI DMA/Interrupt Request Select and Enable Register 0x30 32 read-write n 0x0 0x0 EOQF_RE DSPI Finished Request Enable 28 1 read-write 0 EOQF interrupt requests are disabled. #0 1 EOQF interrupt requests are enabled. #1 RESERVED no description available 0 14 read-only RESERVED no description available 14 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 18 1 read-only RESERVED no description available 20 1 read-only RESERVED no description available 21 1 read-only RESERVED no description available 22 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 26 1 read-only RESERVED no description available 29 1 read-only RESERVED no description available 30 1 read-only RFDF_DIRS Receive FIFO Drain DMA or Interrupt Request Select. 16 1 read-write 0 Interrupt request. #0 1 DMA request. #1 RFDF_RE Receive FIFO Drain Request Enable 17 1 read-write 0 RFDF interrupt or DMA requests are disabled #0 1 RFDF interrupt or DMA requests are enabled #1 RFOF_RE Receive FIFO Overflow Request Enable 19 1 read-write 0 RFOF interrupt requests are disabled. #0 1 RFOF interrupt requests are enabled. #1 TCF_RE Transmission Complete Request Enable 31 1 read-write 0 TCF interrupt requests are disabled. #0 1 TCF interrupt requests are enabled. #1 TFFF_DIRS Transmit FIFO Fill DMA or Interrupt Request Select 24 1 read-write 0 TFFF flag generates interrupt requests. #0 1 TFFF flag generates DMA requests. #1 TFFF_RE Transmit FIFO Fill Request Enable 25 1 read-write 0 TFFF interrupts or DMA requests are disabled. #0 1 TFFF interrupts or DMA requests are enabled. #1 TFUF_RE Transmit FIFO Underflow Request Enable 27 1 read-write 0 TFUF interrupt requests are disabled. #0 1 TFUF interrupt requests are enabled. #1 RXFR0 DSPI Receive FIFO Registers 0xF8 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only RXFR1 DSPI Receive FIFO Registers 0x178 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only RXFR2 DSPI Receive FIFO Registers 0x1FC 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only RXFR3 DSPI Receive FIFO Registers 0x284 32 read-only n 0x0 0x0 RXDATA Receive Data 0 32 read-only SR DSPI Status Register 0x2C 32 read-write n 0x0 0x0 EOQF End of Queue Flag 28 1 read-write 0 EOQ is not set in the executing command. #0 1 EOQ is set in the executing SPI command. #1 POPNXTPTR Pop Next Pointer 0 4 read-only RESERVED no description available 16 1 read-only RESERVED no description available 18 1 read-only RESERVED no description available 20 1 read-only RESERVED no description available 21 1 read-only RESERVED no description available 22 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 24 1 read-only RESERVED no description available 26 1 read-only RESERVED no description available 29 1 read-only RFDF Receive FIFO Drain Flag 17 1 read-write 0 Rx FIFO is empty. #0 1 Rx FIFO is not empty. #1 RFOF Receive FIFO Overflow Flag 19 1 read-write 0 No Rx FIFO overflow. #0 1 Rx FIFO overflow has occurred. #1 RXCTR RX FIFO Counter 4 4 read-only TCF Transfer Complete Flag 31 1 read-write 0 Transfer not complete. #0 1 Transfer complete. #1 TFFF Transmit FIFO Fill Flag 25 1 read-write 0 Tx FIFO is full. #0 1 Tx FIFO is not full. #1 TFUF Transmit FIFO Underflow Flag 27 1 read-write 0 No Tx FIFO underflow. #0 1 Tx FIFO underflow has occurred. #1 TXCTR TX FIFO Counter 12 4 read-only TXNXTPTR Transmit Next Pointer 8 4 read-only TXRXS TX and RX Status 30 1 read-write 0 Transmit and receive operations are disabled (DSPI is in stopped state). #0 1 Transmit and receive operations are enabled (DSPI is in running state). #1 TCR DSPI Transfer Count Register 0x8 32 read-write n 0x0 0x0 RESERVED no description available 0 16 read-only SPI_TCNT SPI Transfer Counter 16 16 read-write TXFR0 DSPI Transmit FIFO Registers 0x78 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TXFR1 DSPI Transmit FIFO Registers 0xB8 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TXFR2 DSPI Transmit FIFO Registers 0xFC 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only TXFR3 DSPI Transmit FIFO Registers 0x144 32 read-only n 0x0 0x0 TXCMD_TXDATA Transmit Command or Transmit Data 16 16 read-only TXDATA Transmit Data 0 16 read-only SystemControl System Control Registers SystemControl 0x0 0x8 0xD38 registers n 0x8 0xD84 registers n ACTLR Auxiliary Control Register, 0x8 32 read-write n 0x0 0x0 DISDEFWBUF Disables write buffer use during default memory map accesses. 1 1 read-write DISFOLD Disables folding of IT instructions. 2 1 read-write DISMCYCINT Disables interruption of multi-cycle instructions. 0 1 read-write RESERVED Reserved 31 1 read-only RESERVED Reserved 4 1 read-only RESERVED Reserved 5 1 read-only RESERVED Reserved 6 1 read-only RESERVED Reserved 7 1 read-only RESERVED Reserved 8 1 read-only RESERVED Reserved 9 1 read-only RESERVED Reserved 10 1 read-only RESERVED Reserved 11 1 read-only RESERVED Reserved 12 1 read-only RESERVED Reserved 13 1 read-only RESERVED Reserved 14 1 read-only RESERVED Reserved 15 1 read-only RESERVED Reserved 16 1 read-only RESERVED Reserved 17 1 read-only RESERVED Reserved 18 1 read-only RESERVED Reserved 19 1 read-only RESERVED Reserved 20 1 read-only RESERVED Reserved 21 1 read-only RESERVED Reserved 22 1 read-only RESERVED Reserved 23 1 read-only RESERVED Reserved 24 1 read-only RESERVED Reserved 25 1 read-only RESERVED Reserved 26 1 read-only RESERVED Reserved 27 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only AFSR Auxiliary Fault Status Register 0xD3C 32 read-write n 0x0 0x0 AUXFAULT Latched version of the AUXFAULT inputs 0 32 read-write AIRCR Application Interrupt and Reset Control Register 0xD0C 32 read-write n 0x0 0x0 ENDIANNESS no description available 15 1 read-only 0 Little-endian #0 1 Big-endian #1 PRIGROUP Interrupt priority grouping field. This field determines the split of group priority from subpriority. 8 3 read-write RESERVED Reserved 14 1 read-only RESERVED Reserved 4 1 read-only RESERVED Reserved 5 1 read-only RESERVED Reserved 6 1 read-only RESERVED Reserved 7 1 read-only RESERVED Reserved 11 1 read-only RESERVED Reserved 12 1 read-only RESERVED Reserved 13 1 read-only RESERVED Reserved 14 1 read-only SYSRESETREQ no description available 2 1 write-only 0 no system reset request #0 1 asserts a signal to the outer system that requests a reset #1 VECTCLRACTIVE no description available 1 1 write-only VECTKEY Register key 16 16 read-write VECTRESET no description available 0 1 write-only BFAR BusFault Address Register 0xD38 32 read-write n 0x0 0x0 ADDRESS Address of the BusFault location 0 32 read-write CCR Configuration and Control Register 0xD14 32 read-write n 0x0 0x0 BFHFNMIGN Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions. 8 1 read-write 0 data bus faults caused by load and store instructions cause a lock-up #0 1 handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions #1 DIV_0_TRP Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0 4 1 read-write 0 do not trap divide by 0 #0 1 trap divide by 0 #1 NONBASETHRDENA no description available 0 1 read-write 0 processor can enter Thread mode only when no exception is active #0 1 processor can enter Thread mode from any level under the control of an EXC_RETURN value #1 RESERVED Reserved 31 1 read-only RESERVED Reserved 5 1 read-only RESERVED Reserved 6 1 read-only RESERVED Reserved 7 1 read-only RESERVED Reserved 10 1 read-only RESERVED Reserved 11 1 read-only RESERVED Reserved 12 1 read-only RESERVED Reserved 13 1 read-only RESERVED Reserved 14 1 read-only RESERVED Reserved 15 1 read-only RESERVED Reserved 16 1 read-only RESERVED Reserved 17 1 read-only RESERVED Reserved 18 1 read-only RESERVED Reserved 19 1 read-only RESERVED Reserved 20 1 read-only RESERVED Reserved 21 1 read-only RESERVED Reserved 22 1 read-only RESERVED Reserved 23 1 read-only RESERVED Reserved 24 1 read-only RESERVED Reserved 25 1 read-only RESERVED Reserved 26 1 read-only RESERVED Reserved 27 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only STKALIGN Indicates stack alignment on exception entry 9 1 read-write 0 4-byte aligned #0 1 8-byte aligned #1 UNALIGN_TRP Enables unaligned access traps 3 1 read-write 0 do not trap unaligned halfword and word accesses #0 1 trap unaligned halfword and word accesses #1 USERSETMPEND Enables unprivileged software access to the STIR 1 1 read-write 0 disable #0 1 enable #1 CFSR Configurable Fault Status Registers 0xD28 32 read-write n 0x0 0x0 BFARVALID no description available 15 1 read-write 0 value in BFAR is not a valid fault address #0 1 BFAR holds a valid fault address #1 DACCVIOL no description available 1 1 read-write 0 no data access violation fault #0 1 the processor attempted a load or store at a location that does not permit the operation #1 DIVBYZERO no description available 25 1 read-write 0 no divide by zero fault, or divide by zero trapping not enabled #0 1 the processor has executed an SDIV or UDIV instruction with a divisor of 0 #1 IACCVIOL no description available 0 1 read-write 0 no instruction access violation fault #0 1 the processor attempted an instruction fetch from a location that does not permit execution #1 IBUSERR no description available 8 1 read-write 0 no instruction bus error #0 1 instruction bus error #1 IMPRECISERR no description available 10 1 read-write 0 no imprecise data bus error #0 1 a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error #1 INVPC no description available 18 1 read-write 0 no invalid PC load UsageFault #0 1 the processor has attempted an illegal load of EXC_RETURN to the PC #1 INVSTATE no description available 17 1 read-write 0 no invalid state UsageFault #0 1 the processor has attempted to execute an instruction that makes illegal use of the EPSR #1 LSPERR no description available 13 1 read-write 0 No bus fault occurred during floating-point lazy state preservation #0 1 A bus fault occurred during floating-point lazy state preservation #1 MLSPERR no description available 5 1 read-write 0 No MemManage fault occurred during floating-point lazy state preservation #0 1 A MemManage fault occurred during floating-point lazy state preservation #1 MMARVALID no description available 7 1 read-write 0 value in MMAR is not a valid fault address #0 1 MMAR holds a valid fault address #1 MSTKERR no description available 4 1 read-write 0 no stacking fault #0 1 stacking for an exception entry has caused one or more access violations #1 MUNSTKERR no description available 3 1 read-write 0 no unstacking fault #0 1 unstack for an exception return has caused one or more access violations #1 NOCP no description available 19 1 read-write 0 no UsageFault caused by attempting to access a coprocessor #0 1 the processor has attempted to access a coprocessor #1 PRECISERR no description available 9 1 read-write 0 no precise data bus error #0 1 a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault #1 RESERVED Reserved 31 1 read-only RESERVED Reserved 6 1 read-only RESERVED Reserved 14 1 read-only RESERVED Reserved 20 1 read-only RESERVED Reserved 21 1 read-only RESERVED Reserved 22 1 read-only RESERVED Reserved 23 1 read-only RESERVED Reserved 26 1 read-only RESERVED Reserved 27 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only STKERR no description available 12 1 read-write 0 no stacking fault #0 1 stacking for an exception entry has caused one or more BusFaults #1 UNALIGNED no description available 24 1 read-write 0 no unaligned access fault, or unaligned access trapping not enabled #0 1 the processor has made an unaligned memory access #1 UNDEFINSTR no description available 16 1 read-write 0 no undefined instruction UsageFault #0 1 the processor has attempted to execute an undefined instruction #1 UNSTKERR no description available 11 1 read-write 0 no unstacking fault #0 1 unstack for an exception return has caused one or more BusFaults #1 CPUID CPUID Base Register 0xD00 32 read-only n 0x0 0x0 IMPLEMENTER Implementer code 24 8 read-only PARTNO Indicates part number 4 12 read-only RESERVED (Constant) Reads as 1 19 1 read-only RESERVED (Constant) Reads as 1 17 1 read-only RESERVED (Constant) Reads as 1 18 1 read-only RESERVED (Constant) Reads as 1 19 1 read-only REVISION Indicates patch release: 0x0 = Patch 0 0 4 read-only VARIANT Indicates processor revision: 0x2 = Revision 2 20 4 read-only DFSR Debug Fault Status Register 0xD30 32 read-write n 0x0 0x0 BKPT no description available 1 1 read-write 0 No current breakpoint debug event #0 1 At least one current breakpoint debug event #1 DWTTRAP no description available 2 1 read-write 0 No current debug events generated by the DWT #0 1 At least one current debug event generated by the DWT #1 EXTERNAL no description available 4 1 read-write 0 No EDBGRQ debug event #0 1 EDBGRQ debug event #1 HALTED no description available 0 1 read-write 0 No active halt request debug event #0 1 Halt request debug event active #1 RESERVED Reserved 31 1 read-write RESERVED Reserved 6 1 read-write RESERVED Reserved 7 1 read-write RESERVED Reserved 8 1 read-write RESERVED Reserved 9 1 read-write RESERVED Reserved 10 1 read-write RESERVED Reserved 11 1 read-write RESERVED Reserved 12 1 read-write RESERVED Reserved 13 1 read-write RESERVED Reserved 14 1 read-write RESERVED Reserved 15 1 read-write RESERVED Reserved 16 1 read-write RESERVED Reserved 17 1 read-write RESERVED Reserved 18 1 read-write RESERVED Reserved 19 1 read-write RESERVED Reserved 20 1 read-write RESERVED Reserved 21 1 read-write RESERVED Reserved 22 1 read-write RESERVED Reserved 23 1 read-write RESERVED Reserved 24 1 read-write RESERVED Reserved 25 1 read-write RESERVED Reserved 26 1 read-write RESERVED Reserved 27 1 read-write RESERVED Reserved 28 1 read-write RESERVED Reserved 29 1 read-write RESERVED Reserved 30 1 read-write RESERVED Reserved 31 1 read-write VCATCH no description available 3 1 read-write 0 No Vector catch triggered #0 1 Vector catch triggered #1 HFSR HardFault Status register 0xD2C 32 read-write n 0x0 0x0 DEBUGEVT no description available 31 1 read-write FORCED no description available 30 1 read-write 0 no forced HardFault #0 1 forced HardFault #1 RESERVED Reserved 29 1 read-only RESERVED Reserved 2 1 read-only RESERVED Reserved 3 1 read-only RESERVED Reserved 4 1 read-only RESERVED Reserved 5 1 read-only RESERVED Reserved 6 1 read-only RESERVED Reserved 7 1 read-only RESERVED Reserved 8 1 read-only RESERVED Reserved 9 1 read-only RESERVED Reserved 10 1 read-only RESERVED Reserved 11 1 read-only RESERVED Reserved 12 1 read-only RESERVED Reserved 13 1 read-only RESERVED Reserved 14 1 read-only RESERVED Reserved 15 1 read-only RESERVED Reserved 16 1 read-only RESERVED Reserved 17 1 read-only RESERVED Reserved 18 1 read-only RESERVED Reserved 19 1 read-only RESERVED Reserved 20 1 read-only RESERVED Reserved 21 1 read-only RESERVED Reserved 22 1 read-only RESERVED Reserved 23 1 read-only RESERVED Reserved 24 1 read-only RESERVED Reserved 25 1 read-only RESERVED Reserved 26 1 read-only RESERVED Reserved 27 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only VECTTBL no description available 1 1 read-write 0 no BusFault on vector table read #0 1 BusFault on vector table read #1 ICSR Interrupt Control and State Register 0xD04 32 read-write n 0x0 0x0 ISRPENDING no description available 22 1 read-only ISRPREEMPT no description available 23 1 read-only 0 Will not service #0 1 Will service a pending exception #1 NMIPENDSET no description available 31 1 read-write 0 write: no effect read: NMI exception is not pending #0 1 write: changes NMI exception state to pending read: NMI exception is pending #1 PENDSTCLR no description available 25 1 write-only 0 no effect #0 1 removes the pending state from the SysTick exception #1 PENDSTSET no description available 26 1 read-write 0 write: no effect read: SysTick exception is not pending #0 1 write: changes SysTick exception state to pending read: SysTick exception is pending #1 PENDSVCLR no description available 27 1 write-only 0 no effect #0 1 removes the pending state from the PendSV exception #1 PENDSVSET no description available 28 1 read-write 0 write: no effect read: PendSV exception is not pending #0 1 write: changes PendSV exception state to pending read: PendSV exception is pending #1 RESERVED Reserved 30 1 read-only RESERVED Reserved 10 1 read-only RESERVED Reserved 18 1 read-only RESERVED Reserved 19 1 read-only RESERVED Reserved 20 1 read-only RESERVED Reserved 21 1 read-only RESERVED Reserved 24 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RETTOBASE no description available 11 1 read-only 0 there are preempted active exceptions to execute #0 1 there are no active exceptions, or the currently-executing exception is the only active exception #1 VECTACTIVE Active exception number 0 9 read-only VECTPENDING Exception number of the highest priority pending enabled exception 12 6 read-only MMFAR MemManage Address Register 0xD34 32 read-write n 0x0 0x0 ADDRESS Address of MemManage fault location 0 32 read-write SCB_ACTLR Auxiliary Control Register, 0x8 32 read-write n 0x0 0x0 DISDEFWBUF Disables write buffer use during default memory map accesses. 1 1 read-write DISFOLD Disables folding of IT instructions. 2 1 read-write DISMCYCINT Disables interruption of multi-cycle instructions. 0 1 read-write RESERVED Reserved 3 1 read-only RESERVED Reserved 4 1 read-only RESERVED Reserved 5 1 read-only RESERVED Reserved 6 1 read-only RESERVED Reserved 7 1 read-only RESERVED Reserved 8 1 read-only RESERVED Reserved 9 1 read-only RESERVED Reserved 10 1 read-only RESERVED Reserved 11 1 read-only RESERVED Reserved 12 1 read-only RESERVED Reserved 13 1 read-only RESERVED Reserved 14 1 read-only RESERVED Reserved 15 1 read-only RESERVED Reserved 16 1 read-only RESERVED Reserved 17 1 read-only RESERVED Reserved 18 1 read-only RESERVED Reserved 19 1 read-only RESERVED Reserved 20 1 read-only RESERVED Reserved 21 1 read-only RESERVED Reserved 22 1 read-only RESERVED Reserved 23 1 read-only RESERVED Reserved 24 1 read-only RESERVED Reserved 25 1 read-only RESERVED Reserved 26 1 read-only RESERVED Reserved 27 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only SCB_AFSR Auxiliary Fault Status Register 0xD3C 32 read-write n 0x0 0x0 AUXFAULT Latched version of the AUXFAULT inputs 0 32 read-write SCB_AIRCR Application Interrupt and Reset Control Register 0xD0C 32 read-write n 0x0 0x0 ENDIANNESS no description available 15 1 read-only 0 Little-endian #0 1 Big-endian #1 PRIGROUP Interrupt priority grouping field. This field determines the split of group priority from subpriority. 8 3 read-write RESERVED Reserved 3 1 read-only RESERVED Reserved 4 1 read-only RESERVED Reserved 5 1 read-only RESERVED Reserved 6 1 read-only RESERVED Reserved 7 1 read-only RESERVED Reserved 11 1 read-only RESERVED Reserved 12 1 read-only RESERVED Reserved 13 1 read-only RESERVED Reserved 14 1 read-only SYSRESETREQ no description available 2 1 write-only 0 no system reset request #0 1 asserts a signal to the outer system that requests a reset #1 VECTCLRACTIVE no description available 1 1 write-only VECTKEY Register key 16 16 read-write VECTRESET no description available 0 1 write-only SCB_BFAR BusFault Address Register 0xD38 32 read-write n 0x0 0x0 ADDRESS Address of the BusFault location 0 32 read-write SCB_CCR Configuration and Control Register 0xD14 32 read-write n 0x0 0x0 BFHFNMIGN Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions. 8 1 read-write 0 data bus faults caused by load and store instructions cause a lock-up #0 1 handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions #1 DIV_0_TRP Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0 4 1 read-write 0 do not trap divide by 0 #0 1 trap divide by 0 #1 NONBASETHRDENA no description available 0 1 read-write 0 processor can enter Thread mode only when no exception is active #0 1 processor can enter Thread mode from any level under the control of an EXC_RETURN value #1 RESERVED Reserved 2 1 read-only RESERVED Reserved 5 1 read-only RESERVED Reserved 6 1 read-only RESERVED Reserved 7 1 read-only RESERVED Reserved 10 1 read-only RESERVED Reserved 11 1 read-only RESERVED Reserved 12 1 read-only RESERVED Reserved 13 1 read-only RESERVED Reserved 14 1 read-only RESERVED Reserved 15 1 read-only RESERVED Reserved 16 1 read-only RESERVED Reserved 17 1 read-only RESERVED Reserved 18 1 read-only RESERVED Reserved 19 1 read-only RESERVED Reserved 20 1 read-only RESERVED Reserved 21 1 read-only RESERVED Reserved 22 1 read-only RESERVED Reserved 23 1 read-only RESERVED Reserved 24 1 read-only RESERVED Reserved 25 1 read-only RESERVED Reserved 26 1 read-only RESERVED Reserved 27 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only STKALIGN Indicates stack alignment on exception entry 9 1 read-write 0 4-byte aligned #0 1 8-byte aligned #1 UNALIGN_TRP Enables unaligned access traps 3 1 read-write 0 do not trap unaligned halfword and word accesses #0 1 trap unaligned halfword and word accesses #1 USERSETMPEND Enables unprivileged software access to the STIR 1 1 read-write 0 disable #0 1 enable #1 SCB_CFSR Configurable Fault Status Registers 0xD28 32 read-write n 0x0 0x0 BFARVALID no description available 15 1 read-write 0 value in BFAR is not a valid fault address #0 1 BFAR holds a valid fault address #1 DACCVIOL no description available 1 1 read-write 0 no data access violation fault #0 1 the processor attempted a load or store at a location that does not permit the operation #1 DIVBYZERO no description available 25 1 read-write 0 no divide by zero fault, or divide by zero trapping not enabled #0 1 the processor has executed an SDIV or UDIV instruction with a divisor of 0 #1 IACCVIOL no description available 0 1 read-write 0 no instruction access violation fault #0 1 the processor attempted an instruction fetch from a location that does not permit execution #1 IBUSERR no description available 8 1 read-write 0 no instruction bus error #0 1 instruction bus error #1 IMPRECISERR no description available 10 1 read-write 0 no imprecise data bus error #0 1 a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error #1 INVPC no description available 18 1 read-write 0 no invalid PC load UsageFault #0 1 the processor has attempted an illegal load of EXC_RETURN to the PC #1 INVSTATE no description available 17 1 read-write 0 no invalid state UsageFault #0 1 the processor has attempted to execute an instruction that makes illegal use of the EPSR #1 LSPERR no description available 13 1 read-write 0 No bus fault occurred during floating-point lazy state preservation #0 1 A bus fault occurred during floating-point lazy state preservation #1 MLSPERR no description available 5 1 read-write 0 No MemManage fault occurred during floating-point lazy state preservation #0 1 A MemManage fault occurred during floating-point lazy state preservation #1 MMARVALID no description available 7 1 read-write 0 value in MMAR is not a valid fault address #0 1 MMAR holds a valid fault address #1 MSTKERR no description available 4 1 read-write 0 no stacking fault #0 1 stacking for an exception entry has caused one or more access violations #1 MUNSTKERR no description available 3 1 read-write 0 no unstacking fault #0 1 unstack for an exception return has caused one or more access violations #1 NOCP no description available 19 1 read-write 0 no UsageFault caused by attempting to access a coprocessor #0 1 the processor has attempted to access a coprocessor #1 PRECISERR no description available 9 1 read-write 0 no precise data bus error #0 1 a data bus error has occurred, and the PC value stacked for the exception return points to the instruction that caused the fault #1 RESERVED Reserved 2 1 read-only RESERVED Reserved 6 1 read-only RESERVED Reserved 14 1 read-only RESERVED Reserved 20 1 read-only RESERVED Reserved 21 1 read-only RESERVED Reserved 22 1 read-only RESERVED Reserved 23 1 read-only RESERVED Reserved 26 1 read-only RESERVED Reserved 27 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only STKERR no description available 12 1 read-write 0 no stacking fault #0 1 stacking for an exception entry has caused one or more BusFaults #1 UNALIGNED no description available 24 1 read-write 0 no unaligned access fault, or unaligned access trapping not enabled #0 1 the processor has made an unaligned memory access #1 UNDEFINSTR no description available 16 1 read-write 0 no undefined instruction UsageFault #0 1 the processor has attempted to execute an undefined instruction #1 UNSTKERR no description available 11 1 read-write 0 no unstacking fault #0 1 unstack for an exception return has caused one or more BusFaults #1 SCB_CPACR Debug Fault Status Register 0xD88 32 read-write n 0x0 0x0 CP10 Access privileges for coprocessor 10. 20 2 read-write 00 Access denied. Any attempted access generates a NOCP UsageFault #00 01 Privileged access only. An unprivileged access generates a NOCP fault. #01 10 Reserved. The result of any access is UNPREDICTABLE. #10 11 Full access. #11 CP11 Access privileges for coprocessor 11. 22 2 read-write 00 Access denied. Any attempted access generates a NOCP UsageFault #00 01 Privileged access only. An unprivileged access generates a NOCP fault. #01 10 Reserved. The result of any access is UNPREDICTABLE. #10 11 Full access. #11 SCB_CPUID CPUID Base Register 0xD00 32 read-only n 0x0 0x0 IMPLEMENTER Implementer code 24 8 read-only PARTNO Indicates part number 4 12 read-only RESERVED (Constant) Reads as 1 16 1 read-only RESERVED (Constant) Reads as 1 17 1 read-only RESERVED (Constant) Reads as 1 18 1 read-only RESERVED (Constant) Reads as 1 19 1 read-only REVISION Indicates patch release: 0x0 = Patch 0 0 4 read-only VARIANT Indicates processor revision: 0x2 = Revision 2 20 4 read-only SCB_DFSR Debug Fault Status Register 0xD30 32 read-write n 0x0 0x0 BKPT no description available 1 1 read-write 0 No current breakpoint debug event #0 1 At least one current breakpoint debug event #1 DWTTRAP no description available 2 1 read-write 0 No current debug events generated by the DWT #0 1 At least one current debug event generated by the DWT #1 EXTERNAL no description available 4 1 read-write 0 No EDBGRQ debug event #0 1 EDBGRQ debug event #1 HALTED no description available 0 1 read-write 0 No active halt request debug event #0 1 Halt request debug event active #1 RESERVED Reserved 5 1 read-write RESERVED Reserved 6 1 read-write RESERVED Reserved 7 1 read-write RESERVED Reserved 8 1 read-write RESERVED Reserved 9 1 read-write RESERVED Reserved 10 1 read-write RESERVED Reserved 11 1 read-write RESERVED Reserved 12 1 read-write RESERVED Reserved 13 1 read-write RESERVED Reserved 14 1 read-write RESERVED Reserved 15 1 read-write RESERVED Reserved 16 1 read-write RESERVED Reserved 17 1 read-write RESERVED Reserved 18 1 read-write RESERVED Reserved 19 1 read-write RESERVED Reserved 20 1 read-write RESERVED Reserved 21 1 read-write RESERVED Reserved 22 1 read-write RESERVED Reserved 23 1 read-write RESERVED Reserved 24 1 read-write RESERVED Reserved 25 1 read-write RESERVED Reserved 26 1 read-write RESERVED Reserved 27 1 read-write RESERVED Reserved 28 1 read-write RESERVED Reserved 29 1 read-write RESERVED Reserved 30 1 read-write RESERVED Reserved 31 1 read-write VCATCH no description available 3 1 read-write 0 No Vector catch triggered #0 1 Vector catch triggered #1 SCB_HFSR HardFault Status register 0xD2C 32 read-write n 0x0 0x0 DEBUGEVT no description available 31 1 read-write FORCED no description available 30 1 read-write 0 no forced HardFault #0 1 forced HardFault #1 RESERVED Reserved 0 1 read-only RESERVED Reserved 2 1 read-only RESERVED Reserved 3 1 read-only RESERVED Reserved 4 1 read-only RESERVED Reserved 5 1 read-only RESERVED Reserved 6 1 read-only RESERVED Reserved 7 1 read-only RESERVED Reserved 8 1 read-only RESERVED Reserved 9 1 read-only RESERVED Reserved 10 1 read-only RESERVED Reserved 11 1 read-only RESERVED Reserved 12 1 read-only RESERVED Reserved 13 1 read-only RESERVED Reserved 14 1 read-only RESERVED Reserved 15 1 read-only RESERVED Reserved 16 1 read-only RESERVED Reserved 17 1 read-only RESERVED Reserved 18 1 read-only RESERVED Reserved 19 1 read-only RESERVED Reserved 20 1 read-only RESERVED Reserved 21 1 read-only RESERVED Reserved 22 1 read-only RESERVED Reserved 23 1 read-only RESERVED Reserved 24 1 read-only RESERVED Reserved 25 1 read-only RESERVED Reserved 26 1 read-only RESERVED Reserved 27 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only VECTTBL no description available 1 1 read-write 0 no BusFault on vector table read #0 1 BusFault on vector table read #1 SCB_ICSR Interrupt Control and State Register 0xD04 32 read-write n 0x0 0x0 ISRPENDING no description available 22 1 read-only ISRPREEMPT no description available 23 1 read-only 0 Will not service #0 1 Will service a pending exception #1 NMIPENDSET no description available 31 1 read-write 0 write: no effect; read: NMI exception is not pending #0 1 write: changes NMI exception state to pending; read: NMI exception is pending #1 PENDSTCLR no description available 25 1 write-only 0 no effect #0 1 removes the pending state from the SysTick exception #1 PENDSTSET no description available 26 1 read-write 0 write: no effect; read: SysTick exception is not pending #0 1 write: changes SysTick exception state to pending; read: SysTick exception is pending #1 PENDSVCLR no description available 27 1 write-only 0 no effect #0 1 removes the pending state from the PendSV exception #1 PENDSVSET no description available 28 1 read-write 0 write: no effect; read: PendSV exception is not pending #0 1 write: changes PendSV exception state to pending; read: PendSV exception is pending #1 RESERVED Reserved 9 1 read-only RESERVED Reserved 10 1 read-only RESERVED Reserved 18 1 read-only RESERVED Reserved 19 1 read-only RESERVED Reserved 20 1 read-only RESERVED Reserved 21 1 read-only RESERVED Reserved 24 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RETTOBASE no description available 11 1 read-only 0 there are preempted active exceptions to execute #0 1 there are no active exceptions, or the currently-executing exception is the only active exception #1 VECTACTIVE Active exception number 0 9 read-only VECTPENDING Exception number of the highest priority pending enabled exception 12 6 read-only SCB_MMFAR MemManage Address Register 0xD34 32 read-write n 0x0 0x0 ADDRESS Address of MemManage fault location 0 32 read-write SCB_SCR System Control Register 0xD10 32 read-write n 0x0 0x0 RESERVED Reserved 0 1 read-only RESERVED Reserved 3 1 read-only RESERVED Reserved 5 1 read-only RESERVED Reserved 6 1 read-only RESERVED Reserved 7 1 read-only RESERVED Reserved 8 1 read-only RESERVED Reserved 9 1 read-only RESERVED Reserved 10 1 read-only RESERVED Reserved 11 1 read-only RESERVED Reserved 12 1 read-only RESERVED Reserved 13 1 read-only RESERVED Reserved 14 1 read-only RESERVED Reserved 15 1 read-only RESERVED Reserved 16 1 read-only RESERVED Reserved 17 1 read-only RESERVED Reserved 18 1 read-only RESERVED Reserved 19 1 read-only RESERVED Reserved 20 1 read-only RESERVED Reserved 21 1 read-only RESERVED Reserved 22 1 read-only RESERVED Reserved 23 1 read-only RESERVED Reserved 24 1 read-only RESERVED Reserved 25 1 read-only RESERVED Reserved 26 1 read-only RESERVED Reserved 27 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only SEVONPEND no description available 4 1 read-write 0 only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded #0 1 enabled events and all interrupts, including disabled interrupts, can wakeup the processor #1 SLEEPDEEP no description available 2 1 read-write 0 sleep #0 1 deep sleep #1 SLEEPONEXIT no description available 1 1 read-write 0 o not sleep when returning to Thread mode #0 1 enter sleep, or deep sleep, on return from an ISR #1 SCB_SHCSR System Handler Control and State Register 0xD24 32 read-write n 0x0 0x0 BUSFAULTACT no description available 1 1 read-write 0 exception is not active #0 1 exception is active #1 BUSFAULTENA no description available 17 1 read-write 0 disable the exception #0 1 enable the exception #1 BUSFAULTPENDED no description available 14 1 read-write 0 exception is not pending #0 1 exception is pending #1 MEMFAULTACT no description available 0 1 read-write 0 exception is not active #0 1 exception is active #1 MEMFAULTENA no description available 16 1 read-write 0 disable the exception #0 1 enable the exception #1 MEMFAULTPENDED no description available 13 1 read-write 0 exception is not pending #0 1 exception is pending #1 MONITORACT no description available 8 1 read-write 0 exception is not active #0 1 exception is active #1 PENDSVACT no description available 10 1 read-write 0 exception is not active #0 1 exception is active #1 RESERVED Reserved 2 1 read-write RESERVED Reserved 4 1 read-write RESERVED Reserved 5 1 read-write RESERVED Reserved 6 1 read-write RESERVED Reserved 9 1 read-write RESERVED Reserved 19 1 read-write RESERVED Reserved 20 1 read-write RESERVED Reserved 21 1 read-write RESERVED Reserved 22 1 read-write RESERVED Reserved 23 1 read-write RESERVED Reserved 24 1 read-write RESERVED Reserved 25 1 read-write RESERVED Reserved 26 1 read-write RESERVED Reserved 27 1 read-write RESERVED Reserved 28 1 read-write RESERVED Reserved 29 1 read-write RESERVED Reserved 30 1 read-write RESERVED Reserved 31 1 read-write SVCALLACT no description available 7 1 read-write 0 exception is not active #0 1 exception is active #1 SVCALLPENDED no description available 15 1 read-write 0 exception is not pending #0 1 exception is pending #1 SYSTICKACT no description available 11 1 read-write 0 exception is not active #0 1 exception is active #1 USGFAULTACT no description available 3 1 read-write 0 exception is not active #0 1 exception is active #1 USGFAULTENA no description available 18 1 read-write 0 disable the exception #0 1 enable the exception #1 USGFAULTPENDED no description available 12 1 read-write 0 exception is not pending #0 1 exception is pending #1 SCB_SHPR1 System Handler Priority Register 1 0xD18 32 read-write n 0x0 0x0 PRI_4 Priority of system handler 4, MemManage 0 8 read-write PRI_5 Priority of system handler 5, BusFault 8 8 read-write PRI_6 Priority of system handler 6, UsageFault 16 8 read-write RESERVED Reserved 24 1 read-only RESERVED Reserved 25 1 read-only RESERVED Reserved 26 1 read-only RESERVED Reserved 27 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only SCB_SHPR2 System Handler Priority Register 2 0xD1C 32 read-write n 0x0 0x0 PRI_11 Priority of system handler 11, SVCall 24 8 read-write RESERVED Reserved 0 1 read-only RESERVED Reserved 1 1 read-only RESERVED Reserved 2 1 read-only RESERVED Reserved 3 1 read-only RESERVED Reserved 4 1 read-only RESERVED Reserved 5 1 read-only RESERVED Reserved 6 1 read-only RESERVED Reserved 7 1 read-only RESERVED Reserved 8 1 read-only RESERVED Reserved 9 1 read-only RESERVED Reserved 10 1 read-only RESERVED Reserved 11 1 read-only RESERVED Reserved 12 1 read-only RESERVED Reserved 13 1 read-only RESERVED Reserved 14 1 read-only RESERVED Reserved 15 1 read-only RESERVED Reserved 16 1 read-only RESERVED Reserved 17 1 read-only RESERVED Reserved 18 1 read-only RESERVED Reserved 19 1 read-only RESERVED Reserved 20 1 read-only RESERVED Reserved 21 1 read-only RESERVED Reserved 22 1 read-only RESERVED Reserved 23 1 read-only SCB_SHPR3 System Handler Priority Register 3 0xD20 32 read-write n 0x0 0x0 PRI_14 Priority of system handler 14, PendSV 16 8 read-write PRI_15 Priority of system handler 15, SysTick exception 24 8 read-write RESERVED Reserved 0 1 read-only RESERVED Reserved 1 1 read-only RESERVED Reserved 2 1 read-only RESERVED Reserved 3 1 read-only RESERVED Reserved 4 1 read-only RESERVED Reserved 5 1 read-only RESERVED Reserved 6 1 read-only RESERVED Reserved 7 1 read-only RESERVED Reserved 8 1 read-only RESERVED Reserved 9 1 read-only RESERVED Reserved 10 1 read-only RESERVED Reserved 11 1 read-only RESERVED Reserved 12 1 read-only RESERVED Reserved 13 1 read-only RESERVED Reserved 14 1 read-only RESERVED Reserved 15 1 read-only SCB_VTOR Vector Table Offset Register 0xD08 32 read-write n 0x0 0x0 RESERVED Reserved 0 1 read-write RESERVED Reserved 1 1 read-write RESERVED Reserved 2 1 read-write RESERVED Reserved 3 1 read-write RESERVED Reserved 4 1 read-write RESERVED Reserved 5 1 read-write RESERVED Reserved 6 1 read-write TBLOFF Vector table base offset 7 25 read-write SCR System Control Register 0xD10 32 read-write n 0x0 0x0 RESERVED Reserved 31 1 read-only RESERVED Reserved 3 1 read-only RESERVED Reserved 5 1 read-only RESERVED Reserved 6 1 read-only RESERVED Reserved 7 1 read-only RESERVED Reserved 8 1 read-only RESERVED Reserved 9 1 read-only RESERVED Reserved 10 1 read-only RESERVED Reserved 11 1 read-only RESERVED Reserved 12 1 read-only RESERVED Reserved 13 1 read-only RESERVED Reserved 14 1 read-only RESERVED Reserved 15 1 read-only RESERVED Reserved 16 1 read-only RESERVED Reserved 17 1 read-only RESERVED Reserved 18 1 read-only RESERVED Reserved 19 1 read-only RESERVED Reserved 20 1 read-only RESERVED Reserved 21 1 read-only RESERVED Reserved 22 1 read-only RESERVED Reserved 23 1 read-only RESERVED Reserved 24 1 read-only RESERVED Reserved 25 1 read-only RESERVED Reserved 26 1 read-only RESERVED Reserved 27 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only SEVONPEND no description available 4 1 read-write 0 only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded #0 1 enabled events and all interrupts, including disabled interrupts, can wakeup the processor #1 SLEEPDEEP no description available 2 1 read-write 0 sleep #0 1 deep sleep #1 SLEEPONEXIT no description available 1 1 read-write 0 o not sleep when returning to Thread mode #0 1 enter sleep, or deep sleep, on return from an ISR #1 SHCSR System Handler Control and State Register 0xD24 32 read-write n 0x0 0x0 BUSFAULTACT no description available 1 1 read-write 0 exception is not active #0 1 exception is active #1 BUSFAULTENA no description available 17 1 read-write 0 disable the exception #0 1 enable the exception #1 BUSFAULTPENDED no description available 14 1 read-write 0 exception is not pending #0 1 exception is pending #1 MEMFAULTACT no description available 0 1 read-write 0 exception is not active #0 1 exception is active #1 MEMFAULTENA no description available 16 1 read-write 0 disable the exception #0 1 enable the exception #1 MEMFAULTPENDED no description available 13 1 read-write 0 exception is not pending #0 1 exception is pending #1 MONITORACT no description available 8 1 read-write 0 exception is not active #0 1 exception is active #1 PENDSVACT no description available 10 1 read-write 0 exception is not active #0 1 exception is active #1 RESERVED Reserved 31 1 read-write RESERVED Reserved 4 1 read-write RESERVED Reserved 5 1 read-write RESERVED Reserved 6 1 read-write RESERVED Reserved 9 1 read-write RESERVED Reserved 19 1 read-write RESERVED Reserved 20 1 read-write RESERVED Reserved 21 1 read-write RESERVED Reserved 22 1 read-write RESERVED Reserved 23 1 read-write RESERVED Reserved 24 1 read-write RESERVED Reserved 25 1 read-write RESERVED Reserved 26 1 read-write RESERVED Reserved 27 1 read-write RESERVED Reserved 28 1 read-write RESERVED Reserved 29 1 read-write RESERVED Reserved 30 1 read-write RESERVED Reserved 31 1 read-write SVCALLACT no description available 7 1 read-write 0 exception is not active #0 1 exception is active #1 SVCALLPENDED no description available 15 1 read-write 0 exception is not pending #0 1 exception is pending #1 SYSTICKACT no description available 11 1 read-write 0 exception is not active #0 1 exception is active #1 USGFAULTACT no description available 3 1 read-write 0 exception is not active #0 1 exception is active #1 USGFAULTENA no description available 18 1 read-write 0 disable the exception #0 1 enable the exception #1 USGFAULTPENDED no description available 12 1 read-write 0 exception is not pending #0 1 exception is pending #1 SHPR1 System Handler Priority Register 1 0xD18 32 read-write n 0x0 0x0 PRI_4 Priority of system handler 4, MemManage 0 8 read-write PRI_5 Priority of system handler 5, BusFault 8 8 read-write PRI_6 Priority of system handler 6, UsageFault 16 8 read-write RESERVED Reserved 31 1 read-only RESERVED Reserved 25 1 read-only RESERVED Reserved 26 1 read-only RESERVED Reserved 27 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only RESERVED Reserved 30 1 read-only RESERVED Reserved 31 1 read-only SHPR2 System Handler Priority Register 2 0xD1C 32 read-write n 0x0 0x0 PRI_11 Priority of system handler 11, SVCall 24 8 read-write RESERVED Reserved 23 1 read-only RESERVED Reserved 1 1 read-only RESERVED Reserved 2 1 read-only RESERVED Reserved 3 1 read-only RESERVED Reserved 4 1 read-only RESERVED Reserved 5 1 read-only RESERVED Reserved 6 1 read-only RESERVED Reserved 7 1 read-only RESERVED Reserved 8 1 read-only RESERVED Reserved 9 1 read-only RESERVED Reserved 10 1 read-only RESERVED Reserved 11 1 read-only RESERVED Reserved 12 1 read-only RESERVED Reserved 13 1 read-only RESERVED Reserved 14 1 read-only RESERVED Reserved 15 1 read-only RESERVED Reserved 16 1 read-only RESERVED Reserved 17 1 read-only RESERVED Reserved 18 1 read-only RESERVED Reserved 19 1 read-only RESERVED Reserved 20 1 read-only RESERVED Reserved 21 1 read-only RESERVED Reserved 22 1 read-only RESERVED Reserved 23 1 read-only SHPR3 System Handler Priority Register 3 0xD20 32 read-write n 0x0 0x0 PRI_14 Priority of system handler 14, PendSV 16 8 read-write PRI_15 Priority of system handler 15, SysTick exception 24 8 read-write RESERVED Reserved 15 1 read-only RESERVED Reserved 1 1 read-only RESERVED Reserved 2 1 read-only RESERVED Reserved 3 1 read-only RESERVED Reserved 4 1 read-only RESERVED Reserved 5 1 read-only RESERVED Reserved 6 1 read-only RESERVED Reserved 7 1 read-only RESERVED Reserved 8 1 read-only RESERVED Reserved 9 1 read-only RESERVED Reserved 10 1 read-only RESERVED Reserved 11 1 read-only RESERVED Reserved 12 1 read-only RESERVED Reserved 13 1 read-only RESERVED Reserved 14 1 read-only RESERVED Reserved 15 1 read-only VTOR Vector Table Offset Register 0xD08 32 read-write n 0x0 0x0 RESERVED Reserved 6 1 read-write RESERVED Reserved 1 1 read-write RESERVED Reserved 2 1 read-write RESERVED Reserved 3 1 read-write RESERVED Reserved 4 1 read-write RESERVED Reserved 5 1 read-write RESERVED Reserved 6 1 read-write TBLOFF Vector table base offset 7 25 read-write SysTick System timer SysTick 0x0 0x0 0x10 registers n CALIB SysTick Calibration Value Register 0xC 32 read-only n 0x0 0x0 NOREF no description available 31 1 read-only 0 The reference clock is provided #0 1 The reference clock is not provided #1 RESERVED no description available 29 1 read-only RESERVED no description available 25 1 read-only RESERVED no description available 26 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 28 1 read-only RESERVED no description available 29 1 read-only SKEW no description available 30 1 read-only 0 10ms calibration value is exact #0 1 10ms calibration value is inexact, because of the clock frequency #1 TENMS Reload value to use for 10ms timing 0 24 read-only CSR SysTick Control and Status Register 0x0 32 read-write n 0x0 0x0 CLKSOURCE no description available 2 1 read-write 0 external clock #0 1 processor clock #1 COUNTFLAG no description available 16 1 read-write ENABLE no description available 0 1 read-write 0 counter disabled #0 1 counter enabled #1 RESERVED no description available 31 1 read-only RESERVED no description available 4 1 read-only RESERVED no description available 5 1 read-only RESERVED no description available 6 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 8 1 read-only RESERVED no description available 9 1 read-only RESERVED no description available 10 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 12 1 read-only RESERVED no description available 13 1 read-only RESERVED no description available 14 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 17 1 read-only RESERVED no description available 18 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 20 1 read-only RESERVED no description available 21 1 read-only RESERVED no description available 22 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 24 1 read-only RESERVED no description available 25 1 read-only RESERVED no description available 26 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 28 1 read-only RESERVED no description available 29 1 read-only RESERVED no description available 30 1 read-only RESERVED no description available 31 1 read-only TICKINT no description available 1 1 read-write 0 counting down to 0 does not assert the SysTick exception request #0 1 counting down to 0 asserts the SysTick exception request #1 CVR SysTick Current Value Register 0x8 32 read-write n 0x0 0x0 CURRENT Current value at the time the register is accessed 0 24 read-write RESERVED no description available 31 1 read-only RESERVED no description available 25 1 read-only RESERVED no description available 26 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 28 1 read-only RESERVED no description available 29 1 read-only RESERVED no description available 30 1 read-only RESERVED no description available 31 1 read-only RVR SysTick Reload Value Register 0x4 32 read-write n 0x0 0x0 RELOAD Value to load into the SysTick Current Value Register when the counter reaches 0 0 24 read-write RESERVED no description available 31 1 read-only RESERVED no description available 25 1 read-only RESERVED no description available 26 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 28 1 read-only RESERVED no description available 29 1 read-only RESERVED no description available 30 1 read-only RESERVED no description available 31 1 read-only SYST_CALIB SysTick Calibration Value Register 0xC 32 read-only n 0x0 0x0 NOREF no description available 31 1 read-only 0 The reference clock is provided #0 1 The reference clock is not provided #1 RESERVED no description available 24 1 read-only RESERVED no description available 25 1 read-only RESERVED no description available 26 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 28 1 read-only RESERVED no description available 29 1 read-only SKEW no description available 30 1 read-only 0 10ms calibration value is exact #0 1 10ms calibration value is inexact, because of the clock frequency #1 TENMS Reload value to use for 10ms timing 0 24 read-only SYST_CSR SysTick Control and Status Register 0x0 32 read-write n 0x0 0x0 CLKSOURCE no description available 2 1 read-write 0 external clock #0 1 processor clock #1 COUNTFLAG no description available 16 1 read-write ENABLE no description available 0 1 read-write 0 counter disabled #0 1 counter enabled #1 RESERVED no description available 3 1 read-only RESERVED no description available 4 1 read-only RESERVED no description available 5 1 read-only RESERVED no description available 6 1 read-only RESERVED no description available 7 1 read-only RESERVED no description available 8 1 read-only RESERVED no description available 9 1 read-only RESERVED no description available 10 1 read-only RESERVED no description available 11 1 read-only RESERVED no description available 12 1 read-only RESERVED no description available 13 1 read-only RESERVED no description available 14 1 read-only RESERVED no description available 15 1 read-only RESERVED no description available 17 1 read-only RESERVED no description available 18 1 read-only RESERVED no description available 19 1 read-only RESERVED no description available 20 1 read-only RESERVED no description available 21 1 read-only RESERVED no description available 22 1 read-only RESERVED no description available 23 1 read-only RESERVED no description available 24 1 read-only RESERVED no description available 25 1 read-only RESERVED no description available 26 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 28 1 read-only RESERVED no description available 29 1 read-only RESERVED no description available 30 1 read-only RESERVED no description available 31 1 read-only TICKINT no description available 1 1 read-write 0 counting down to 0 does not assert the SysTick exception request #0 1 counting down to 0 asserts the SysTick exception request #1 SYST_CVR SysTick Current Value Register 0x8 32 read-write n 0x0 0x0 CURRENT Current value at the time the register is accessed 0 24 read-write RESERVED no description available 24 1 read-only RESERVED no description available 25 1 read-only RESERVED no description available 26 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 28 1 read-only RESERVED no description available 29 1 read-only RESERVED no description available 30 1 read-only RESERVED no description available 31 1 read-only SYST_RVR SysTick Reload Value Register 0x4 32 read-write n 0x0 0x0 RELOAD Value to load into the SysTick Current Value Register when the counter reaches 0 0 24 read-write RESERVED no description available 24 1 read-only RESERVED no description available 25 1 read-only RESERVED no description available 26 1 read-only RESERVED no description available 27 1 read-only RESERVED no description available 28 1 read-only RESERVED no description available 29 1 read-only RESERVED no description available 30 1 read-only RESERVED no description available 31 1 read-only TSI0 Touch Sensing Input TSI0 0x0 0x0 0x124 registers n TSI0 83 INT_TSI0 99 CNTR1 Counter Register 0x200 32 read-only n 0x0 0x0 CTN TouchSensing Channel n 16-bit counter value 16 16 read-only CTN1 TouchSensing Channel n-1 16-bit counter value 0 16 read-only CNTR11 Counter Register 0x73C 32 read-only n 0x0 0x0 CTN TouchSensing Channel n 16-bit counter value 16 16 read-only CTN1 TouchSensing Channel n-1 16-bit counter value 0 16 read-only CNTR13 Counter Register 0x854 32 read-only n 0x0 0x0 CTN TouchSensing Channel n 16-bit counter value 16 16 read-only CTN1 TouchSensing Channel n-1 16-bit counter value 0 16 read-only CNTR15 Counter Register 0x970 32 read-only n 0x0 0x0 CTN TouchSensing Channel n 16-bit counter value 16 16 read-only CTN1 TouchSensing Channel n-1 16-bit counter value 0 16 read-only CNTR3 Counter Register 0x304 32 read-only n 0x0 0x0 CTN TouchSensing Channel n 16-bit counter value 16 16 read-only CTN1 TouchSensing Channel n-1 16-bit counter value 0 16 read-only CNTR5 Counter Register 0x40C 32 read-only n 0x0 0x0 CTN TouchSensing Channel n 16-bit counter value 16 16 read-only CTN1 TouchSensing Channel n-1 16-bit counter value 0 16 read-only CNTR7 Counter Register 0x518 32 read-only n 0x0 0x0 CTN TouchSensing Channel n 16-bit counter value 16 16 read-only CTN1 TouchSensing Channel n-1 16-bit counter value 0 16 read-only CNTR9 Counter Register 0x628 32 read-only n 0x0 0x0 CTN TouchSensing Channel n 16-bit counter value 16 16 read-only CTN1 TouchSensing Channel n-1 16-bit counter value 0 16 read-only GENCS General Control and Status Register 0x0 32 read-write n 0x0 0x0 EOSF End of Scan Flag. 15 1 read-write ERIE Error Interrupt Enable 5 1 read-write 0 Interrupt disabled for error. #0 1 Interrupt enabled for error. #1 ESOR End-of-Scan or Out-of-Range Interrupt select 4 1 read-write 0 Out-of-Range interrupt is allowed. #0 1 End-of-Scan interrupt is allowed. #1 EXTERF External Electrode error occurred 13 1 read-write 0 No fault happend on TSI electrodes #0 1 Short to VDD or VSS was detected on one or more electrodes. #1 LPCLKS Low Power Mode Clock Source Selection. 28 1 read-write 0 LPOCLK is selected to determine the scan period in low power mode #0 1 VLPOSCCLK is selected to determine the scan period in low power mode #1 LPSCNITV TSI Low Power Mode Scan Interval. 24 4 read-write 0000 1 ms scan interval #0000 0001 5 ms scan interval #0001 0010 10 ms scan interval #0010 0011 15 ms scan interval #0011 0100 20 ms scan interval #0100 0101 30 ms scan interval #0101 0110 40 ms scan interval #0110 0111 50 ms scan interval #0111 1000 75 ms scan interval #1000 1001 100 ms scan interval #1001 1010 125 ms scan interval #1010 1011 150 ms scan interval #1011 1100 200 ms scan interval #1100 1101 300 ms scan interval #1101 1110 400 ms scan interval #1110 1111 500 ms scan interval #1111 NSCN Number of Consecutive Scans per Electrode electrode. 19 5 read-write 00000 Once per electrode #00000 00001 Twice per electrode #00001 00010 3 times per electrode #00010 00011 4 times per electrode #00011 00100 5 times per electrode #00100 00101 6 times per electrode #00101 00110 7 times per electrode #00110 00111 8 times per electrode #00111 01000 9 times per electrode #01000 01001 10 times per electrode #01001 01010 11 times per electrode #01010 01011 12 times per electrode #01011 01100 13 times per electrode #01100 01101 14 times per electrode #01101 01110 15 times per electrode #01110 01111 16 times per electrode #01111 10000 17 times per electrode #10000 10001 18 times per electrode #10001 10010 19 times per electrode #10010 10011 20 times per electrode #10011 10100 21 times per electrode #10100 10101 22 times per electrode #10101 10110 23 times per electrode #10110 10111 24 times per electrode #10111 11000 25 times per electrode #11000 11001 26 times per electrode #11001 11010 27 times per electrode #11010 11011 28 times per electrode #11011 11100 29 times per electrode #11100 11101 30 times per electrode #11101 11110 31 times per electrode #11110 11111 32 times per electrode #11111 OUTRGF Out of Range Flag. 14 1 read-write OVRF Overrun error Flag. This flag is set when a scan trigger occurs while a scan is still in progress. Writing "1" to this bit will clear the flag to 0. 12 1 read-write 0 No over run. #0 1 Over Run occurred. #1 PS Electrode Oscillator prescaler. . 16 3 read-write 000 Electrode Oscillator Frequency divided by 1 #000 001 Electrode Oscillator Frequency divided by 2 #001 010 Electrode Oscillator Frequency divided by 4 #010 011 Electrode Oscillator Frequency divided by 8 #011 100 Electrode Oscillator Frequency divided by 16 #100 101 Electrode Oscillator Frequency divided by 32 #101 110 Electrode Oscillator Frequency divided by 64 #110 111 Electrode Oscillator Frequency divided by 128 #111 RESERVED Reserved 2 1 read-write RESERVED no description available 3 1 read-only RESERVED no description available 10 2 read-only RESERVED no description available 29 3 read-only SCNIP Scan In Progress status 9 1 read-only STM Scan Trigger Mode. This bit-field can only be changed if the TSI module is disabled (TSIEN bit = 0). 1 1 read-write 0 Software trigger scan. #0 1 Periodical Scan. #1 STPE no description available 0 1 read-write 0 Disable TSI when MCU goes into low power modes. #0 1 Allows TSI to continue running in all low power modes. #1 SWTS Software Trigger Start 8 1 write-only TSIEN Touch Sensing Input Module Enable 7 1 read-write 0 TSI module is disabled #0 1 TSI module is enabled #1 TSIIE Touch Sensing Input Interrupt Module Enable 6 1 read-write 0 Interrupt from TSI is disabled #0 1 Interrupt from TSI is enabled #1 PEN Pin Enable Register 0x8 32 read-write n 0x0 0x0 LPSP Low Power Scan Pin 16 4 read-write 0000 TSI_IN[0] is active in low power mode. #0000 0001 TSI_IN[1] is active in low power mode. #0001 0010 TSI_IN[2] is active in low power mode. #0010 0011 TSI_IN[3] is active in low power mode. #0011 0100 TSI_IN[4] is active in low power mode. #0100 0101 TSI_IN[5] is active in low power mode. #0101 0110 TSI_IN[6] is active in low power mode. #0110 0111 TSI_IN[7] is active in low power mode. #0111 1000 TSI_IN[8] is active in low power mode. #1000 1001 TSI_IN[9] is active in low power mode. #1001 1010 TSI_IN[10] is active in low power mode. #1010 1011 TSI_IN[11] is active in low power mode. #1011 1100 TSI_IN[12] is active in low power mode. #1100 1101 TSI_IN[13] is active in low power mode. #1101 1110 TSI_IN[14] is active in low power mode. #1110 1111 TSI_IN[15] is active in low power mode. #1111 PEN0 Touch Sensing Input Pin Enable Register 0 0 1 read-write 0 The corresponding pin is not used by TSI. #0 1 The corresponding pin is used by TSI. #1 PEN1 Touch Sensing Input Pin Enable Register 1 1 1 read-write 0 The corresponding pin is not used by TSI. #0 1 The corresponding pin is used by TSI. #1 PEN10 Touch Sensing Input Pin Enable Register 10 10 1 read-write 0 The corresponding pin is not used by TSI. #0 1 The corresponding pin is used by TSI. #1 PEN11 Touch Sensing Input Pin Enable Register 11 11 1 read-write 0 The corresponding pin is not used by TSI. #0 1 The corresponding pin is used by TSI. #1 PEN12 Touch Sensing Input Pin Enable Register 12 12 1 read-write 0 The corresponding pin is not used by TSI. #0 1 The corresponding pin is used by TSI. #1 PEN13 Touch Sensing Input Pin Enable Register 13 13 1 read-write 0 The corresponding pin is not used by TSI. #0 1 The corresponding pin is used by TSI. #1 PEN14 Touch Sensing Input Pin Enable Register 14 14 1 read-write 0 The corresponding pin is not used by TSI. #0 1 The corresponding pin is used by TSI. #1 PEN15 Touch Sensing Input Pin Enable Register 15 15 1 read-write 0 The corresponding pin is not used by TSI. #0 1 The corresponding pin is used by TSI. #1 PEN2 Touch Sensing Input Pin Enable Register 2 2 1 read-write 0 The corresponding pin is not used by TSI. #0 1 The corresponding pin is used by TSI. #1 PEN3 Touch Sensing Input Pin Enable Register 3 3 1 read-write 0 The corresponding pin is not used by TSI. #0 1 The corresponding pin is used by TSI. #1 PEN4 Touch Sensing Input Pin Enable Register 4 4 1 read-write 0 The corresponding pin is not used by TSI. #0 1 The corresponding pin is used by TSI. #1 PEN5 Touch Sensing Input Pin Enable Register 5 5 1 read-write 0 The corresponding pin is not used by TSI. #0 1 The corresponding pin is used by TSI. #1 PEN6 Touch Sensing Input Pin Enable Register 6 6 1 read-write 0 The corresponding pin is not used by TSI. #0 1 The corresponding pin is used by TSI. #1 PEN7 Touch Sensing Input Pin Enable Register 7 7 1 read-write 0 The corresponding pin is not used by TSI. #0 1 The corresponding pin is used by TSI. #1 PEN8 Touch Sensing Input Pin Enable Register 8 8 1 read-write 0 The corresponding pin is not used by TSI. #0 1 The corresponding pin is used by TSI. #1 PEN9 Touch Sensing Input Pin Enable Register 9 9 1 read-write 0 The corresponding pin is not used by TSI. #0 1 The corresponding pin is used by TSI. #1 RESERVED no description available 20 12 read-only SCANC SCAN Control Register 0x4 32 read-write n 0x0 0x0 AMCLKS Active Mode Clock Source 3 2 read-write 00 LPOSCCLK #00 01 MCGIRCLK. #01 10 OSC0ERCLK. #10 11 Not valid. #11 AMPSC Active Mode Prescaler 0 3 read-write 000 Input Clock Source divided by 1. #000 001 Input Clock Source divided by 2. #001 010 Input Clock Source divided by 4. #010 011 Input Clock Source divided by 8. #011 100 Input Clock Source divided by 16. #100 101 Input Clock Source divided by 32. #101 110 Input Clock Source divided by 64. #110 111 Input Clock Source divided by 128. #111 EXTCHRG External OSC Charge Current select 16 4 read-write 0000 2 uA charge current. #0000 0001 4 uA charge current. #0001 0010 6 uA charge current. #0010 0011 8 uA charge current. #0011 0100 10 uA charge current. #0100 0101 12 uA charge current. #0101 0110 14 uA charge current. #0110 0111 16 uA charge current. #0111 1000 18 uA charge current. #1000 1001 20 uA charge current. #1001 1010 22 uA charge current. #1010 1011 24 uA charge current. #1011 1100 26 uA charge current. #1100 1101 28 uA charge current. #1101 1110 30 uA charge current. #1110 1111 32 uA charge current. #1111 REFCHRG Ref OSC Charge Current select 24 4 read-write 0000 2 uA charge current. #0000 0001 4 uA charge current. #0001 0010 6 uA charge current. #0010 0011 8 uA charge current. #0011 0100 10 uA charge current. #0100 0101 12 uA charge current. #0101 0110 14 uA charge current. #0110 0111 16 uA charge current. #0111 1000 18 uA charge current. #1000 1001 20 uA charge current. #1001 1010 22 uA charge current. #1010 1011 24 uA charge current. #1011 1100 26 uA charge current. #1100 1101 28 uA charge current. #1101 1110 30 uA charge current. #1110 1111 32 uA charge current. #1111 RESERVED no description available 5 1 read-only RESERVED no description available 6 2 read-only RESERVED no description available 20 4 read-only RESERVED no description available 28 4 read-only SMOD Scan Module 8 8 read-write 00000000 Continue Scan. #00000000 THRESHOLD Low Power Channel Threshold Register 0x120 32 read-write n 0x0 0x0 HTHH Touch Sensing Channel High Threshold value 0 16 read-write LTHH Touch Sensing Channel Low Threshold value 16 16 read-write WUCNTR Wake-Up Channel Counter Register 0xC 32 read-only n 0x0 0x0 RESERVED no description available 16 16 read-only WUCNT TouchSensing wake-up Channel 16bit counter value 0 16 read-only UART0 Serial Communication Interface UART 0x0 0x0 0x32 registers n UART0_LON 44 UART0_RX_TX 45 UART0_ERR 46 INT_UART0_LON 60 INT_UART0_RX_TX 61 INT_UART0_ERR 62 B1T UART CEA709.1-B Beta1 Timer 0x24 8 read-write n 0x0 0x0 B1T Beta1 Timer 0 8 read-write BDH UART Baud Rate Registers: High 0x0 8 read-write n 0x0 0x0 LBKDIE LIN Break Detect Interrupt Enable 7 1 read-write 0 LBKDIF interrupt requests disabled. #0 1 LBKDIF interrupt requests enabled. #1 RESERVED no description available 5 1 read-only RXEDGIE RxD Input Active Edge Interrupt Enable 6 1 read-write 0 Hardware interrupts from RXEDGIF disabled using polling. #0 1 RXEDGIF interrupt request enabled. #1 SBR UART Baud Rate Bits 0 5 read-write BDL UART Baud Rate Registers: Low 0x1 8 read-write n 0x0 0x0 SBR UART Baud Rate Bits 0 8 read-write C1 UART Control Register 1 0x2 8 read-write n 0x0 0x0 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation. #0 1 Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC. #1 M 9-bit or 8-bit Mode Select 4 1 read-write 0 Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. #0 1 Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. #1 PE Parity Enable 1 1 read-write 0 Parity function disabled. #0 1 Parity function enabled. #1 PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 RSRC Receiver Source Select 5 1 read-write 0 Selects internal loop back mode. The receiver input is internally connected to transmitter output. #0 1 Single wire UART mode where the receiver input is connected to the transmit pin input signal. #1 UARTSWAI UART Stops in Wait Mode 6 1 read-write 0 UART clock continues to run in Wait mode. #0 1 UART clock freezes while CPU is in Wait mode. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Idle line wakeup. #0 1 Address mark wakeup. #1 C2 UART Control Register 2 0x3 8 read-write n 0x0 0x0 ILIE Idle Line Interrupt Enable 4 1 read-write 0 IDLE interrupt requests disabled. #0 1 IDLE interrupt requests enabled. #1 RE Receiver Enable 2 1 read-write 0 Receiver off. #0 1 Receiver on. #1 RIE Receiver Full Interrupt or DMA Transfer Enable 5 1 read-write 0 RDRF interrupt and DMA transfer requests disabled. #0 1 RDRF interrupt or DMA transfer requests enabled. #1 RWU Receiver Wakeup Control 1 1 read-write 0 Normal operation. #0 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. #1 SBK Send Break 0 1 read-write 0 Normal transmitter operation. #0 1 Queue break characters to be sent. #1 TCIE Transmission Complete Interrupt Enable 6 1 read-write 0 TC interrupt requests disabled. #0 1 TC interrupt requests enabled. #1 TE Transmitter Enable 3 1 read-write 0 Transmitter off. #0 1 Transmitter on. #1 TIE Transmitter Interrupt or DMA Transfer Enable. 7 1 read-write 0 TDRE interrupt and DMA transfer requests disabled. #0 1 TDRE interrupt or DMA transfer requests enabled. #1 C3 UART Control Register 3 0x6 8 read-write n 0x0 0x0 FEIE Framing Error Interrupt Enable 1 1 read-write 0 FE interrupt requests are disabled. #0 1 FE interrupt requests are enabled. #1 NEIE Noise Error Interrupt Enable 2 1 read-write 0 NF interrupt requests are disabled. #0 1 NF interrupt requests are enabled. #1 ORIE Overrun Error Interrupt Enable 3 1 read-write 0 OR interrupts are disabled. #0 1 OR interrupt requests are enabled. #1 PEIE Parity Error Interrupt Enable 0 1 read-write 0 PF interrupt requests are disabled. #0 1 PF interrupt requests are enabled. #1 R8 Received Bit 8 7 1 read-only T8 Transmit Bit 8 6 1 read-write TXDIR Transmitter Pin Data Direction in Single-Wire mode 5 1 read-write 0 TXD pin is an input in single wire mode. #0 1 TXD pin is an output in single wire mode. #1 TXINV Transmit Data Inversion. 4 1 read-write 0 Transmit data is not inverted. #0 1 Transmit data is inverted. #1 C4 UART Control Register 4 0xA 8 read-write n 0x0 0x0 BRFA Baud Rate Fine Adjust 0 5 read-write M10 10-bit Mode select 5 1 read-write 0 The parity bit is the ninth bit in the serial transmission. #0 1 The parity bit is the tenth bit in the serial transmission. #1 MAEN1 Match Address Mode Enable 1 7 1 read-write 0 All data received is transferred to the data buffer if MAEN2 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled. #1 MAEN2 Match Address Mode Enable 2 6 1 read-write 0 All data received is transferred to the data buffer if MAEN1 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled. #1 C5 UART Control Register 5 0xB 8 read-write n 0x0 0x0 RDMAS Receiver Full DMA Select 5 1 read-write 0 If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service. #0 1 If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer. #1 RESERVED no description available 0 5 read-only RESERVED no description available 6 1 read-only TDMAS Transmitter DMA Select 7 1 read-write 0 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service. #0 1 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer. #1 C6 UART CEA709.1-B Control Register 6 0x21 8 read-write n 0x0 0x0 CE Collision Enable 5 1 read-write 0 Collision detect feature is disabled. #0 1 Collision detect feature is enabled. #1 CP Collision Signal Polarity 4 1 read-write 0 Collision signal is active low. #0 1 Collision signal is active high. #1 EN709 EN709 7 1 read-write 0 CEA709.1-B is disabled. #0 1 CEA709.1-B is enabled #1 RESERVED no description available 0 4 read-only TX709 CEA709.1-B Transmit Enable 6 1 read-write 0 CEA709.1-B transmitter is disabled. #0 1 CEA709.1-B transmitter is enabled. #1 C7816 UART 7816 Control Register 0x18 8 read-write n 0x0 0x0 ANACK Generate NACK on Error 3 1 read-write 0 No NACK is automatically generated. #0 1 A NACK is automatically generated if a parity error is detected or if an invalid initial character is detected. #1 INIT Detect Initial Character 2 1 read-write 0 Normal operating mode. Receiver does not seek to identify initial character. #0 1 Receiver searches for initial character. #1 ISO_7816E ISO-7816 Functionality Enabled 0 1 read-write 0 ISO-7816 functionality is turned off/not enabled. #0 1 ISO-7816 functionality is turned on/enabled. #1 ONACK Generate NACK on Overflow 4 1 read-write 0 The received data does not generate a NACK when the receipt of the data results in an overflow event. #0 1 If the receiver buffer overflows, a NACK is automatically sent on a received character. #1 RESERVED no description available 5 3 read-only TTYPE Transfer Type 1 1 read-write 0 T = 0 per the ISO-7816 specification. #0 1 T = 1 per the ISO-7816 specification. #1 CFIFO UART FIFO Control Register 0x11 8 read-write n 0x0 0x0 RESERVED no description available 3 3 read-only RXFLUSH Receive FIFO/Buffer Flush 6 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 RXOFE Receive FIFO Overflow Interrupt Enable 2 1 read-write 0 RXOF flag does not generate an interrupt to the host. #0 1 RXOF flag generates an interrupt to the host. #1 RXUFE Receive FIFO Underflow Interrupt Enable 0 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXFLUSH Transmit FIFO/Buffer Flush 7 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 1 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 CPW UART CEA709.1-B Collision Pulse Width 0x2F 8 read-write n 0x0 0x0 CPW CEA709.1-B CPW register 0 8 read-write D UART Data Register 0x7 8 read-write n 0x0 0x0 RT no description available 0 8 read-write ED UART Extended Data Register 0xC 8 read-only n 0x0 0x0 NOISY no description available 7 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 PARITYE no description available 6 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 RESERVED no description available 0 6 read-only ET7816 UART 7816 Error Threshold Register 0x1E 8 read-write n 0x0 0x0 RXTHRESHOLD Receive NACK Threshold 0 4 read-write TXTHRESHOLD Transmit NACK Threshold 4 4 read-write 0 TXT asserts on the first NACK that is received. #0 1 TXT asserts on the second NACK that is received. #1 IE UART CEA709.1-B Interrupt Enable Register 0x29 8 read-write n 0x0 0x0 ISDIE Initial Sync Detection Interrupt Enable 5 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 PCTEIE Packet Cycle Timer Interrupt Enable 2 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 PRXIE Packet Received Interrupt Enable 4 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 PSIE Preamble Start Interrupt Enable 1 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 PTXIE Packet Transmitted Interrupt Enable 3 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 RESERVED no description available 7 1 read-only TXFIE Transmission Fail Interrupt Enable 0 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 WBEIE WBASE Expired Interrupt Enable 6 1 read-write 0 Interrupt is disabled. #0 1 Interrupt is enabled. #1 IE7816 UART 7816 Interrupt Enable Register 0x19 8 read-write n 0x0 0x0 BWTE Block Wait Timer Interrupt Enable 5 1 read-write 0 The assertion of IS7816[BWT] does not result in the generation of an interrupt. #0 1 The assertion of IS7816[BWT] results in the generation of an interrupt. #1 CWTE Character Wait Timer Interrupt Enable 6 1 read-write 0 The assertion of IS7816[CWT] does not result in the generation of an interrupt. #0 1 The assertion of IS7816[CWT] results in the generation of an interrupt. #1 GTVE Guard Timer Violated Interrupt Enable 2 1 read-write 0 The assertion of IS7816[GTV] does not result in the generation of an interrupt. #0 1 The assertion of IS7816[GTV] results in the generation of an interrupt. #1 INITDE Initial Character Detected Interrupt Enable 4 1 read-write 0 The assertion of IS7816[INITD] does not result in the generation of an interrupt. #0 1 The assertion of IS7816[INITD] results in the generation of an interrupt. #1 RESERVED no description available 3 1 read-only RXTE Receive Threshold Exceeded Interrupt Enable 0 1 read-write 0 The assertion of IS7816[RXT] does not result in the generation of an interrupt. #0 1 The assertion of IS7816[RXT] results in the generation of an interrupt. #1 TXTE Transmit Threshold Exceeded Interrupt Enable 1 1 read-write 0 The assertion of IS7816[TXT] does not result in the generation of an interrupt. #0 1 The assertion of IS7816[TXT] results in the generation of an interrupt. #1 WTE Wait Timer Interrupt Enable 7 1 read-write 0 The assertion of IS7816[WT] does not result in the generation of an interrupt. #0 1 The assertion of IS7816[WT] results in the generation of an interrupt. #1 IR UART Infrared Register 0xE 8 read-write n 0x0 0x0 IREN Infrared enable 2 1 read-write 0 IR disabled. #0 1 IR enabled. #1 RESERVED no description available 3 5 read-only TNP Transmitter narrow pulse 0 2 read-write 00 3/16. #00 01 1/16. #01 10 1/32. #10 11 1/4. #11 IS7816 UART 7816 Interrupt Status Register 0x1A 8 read-write n 0x0 0x0 BWT Block Wait Timer Interrupt 5 1 read-write 0 Block wait time (BWT) has not been violated. #0 1 Block wait time (BWT) has been violated. #1 CWT Character Wait Timer Interrupt 6 1 read-write 0 Character wait time (CWT) has not been violated. #0 1 Character wait time (CWT) has been violated. #1 GTV Guard Timer Violated Interrupt 2 1 read-write 0 A guard time (GT, CGT, or BGT) has not been violated. #0 1 A guard time (GT, CGT, or BGT) has been violated. #1 INITD Initial Character Detected Interrupt 4 1 read-write 0 A valid initial character has not been received. #0 1 A valid initial character has been received. #1 RESERVED no description available 3 1 read-only RXT Receive Threshold Exceeded Interrupt 0 1 read-write 0 The number of consecutive NACKS generated as a result of parity errors and buffer overruns is less than or equal to the value in ET7816[RXTHRESHOLD]. #0 1 The number of consecutive NACKS generated as a result of parity errors and buffer overruns is greater than the value in ET7816[RXTHRESHOLD]. #1 TXT Transmit Threshold Exceeded Interrupt 1 1 read-write 0 The number of retries and corresponding NACKS does not exceed the value in ET7816[TXTHRESHOLD]. #0 1 The number of retries and corresponding NACKS exceeds the value in ET7816[TXTHRESHOLD]. #1 WT Wait Timer Interrupt 7 1 read-write 0 Wait time (WT) has not been violated. #0 1 Wait time (WT) has been violated. #1 MA1 UART Match Address Registers 1 0x8 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MA2 UART Match Address Registers 2 0x9 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MODEM UART Modem Register 0xD 8 read-write n 0x0 0x0 RESERVED no description available 4 4 read-only RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER]. #1 TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO) #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 PCTH UART CEA709.1-B Packet Cycle Time Counter High 0x22 8 read-write n 0x0 0x0 PCTH Packet Cycle Time Counter High 0 8 read-write PCTL UART CEA709.1-B Packet Cycle Time Counter Low 0x23 8 read-write n 0x0 0x0 PCTL Packet Cycle Time Counter Low 0 8 read-write PFIFO UART FIFO Parameters 0x10 8 read-write n 0x0 0x0 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 000 Receive FIFO/Buffer depth = 1 dataword. #000 001 Receive FIFO/Buffer depth = 4 datawords. #001 010 Receive FIFO/Buffer depth = 8 datawords. #010 011 Receive FIFO/Buffer depth = 16 datawords. #011 100 Receive FIFO/Buffer depth = 32 datawords. #100 101 Receive FIFO/Buffer depth = 64 datawords. #101 110 Receive FIFO/Buffer depth = 128 datawords. #110 111 Reserved. #111 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 000 Transmit FIFO/Buffer depth = 1 dataword. #000 001 Transmit FIFO/Buffer depth = 4 datawords. #001 010 Transmit FIFO/Buffer depth = 8 datawords. #010 011 Transmit FIFO/Buffer depth = 16 datawords. #011 100 Transmit FIFO/Buffer depth = 32 datawords. #100 101 Transmit FIFO/Buffer depth = 64 datawords. #101 110 Transmit FIFO/Buffer depth = 128 datawords. #110 111 Reserved. #111 PRE UART CEA709.1-B Preamble 0x27 8 read-write n 0x0 0x0 PREAMBLE CEA709.1-B Preamble Register 0 8 read-write RCFIFO UART FIFO Receive Count 0x16 8 read-only n 0x0 0x0 RXCOUNT Receive Counter 0 8 read-only RIDT UART CEA709.1-B Receive Indeterminate Time 0x30 8 read-write n 0x0 0x0 RIDT CEA709.1-B Receive IDT register 0 8 read-write RPL UART CEA709.1-B Received Packet Length 0x2D 8 read-only n 0x0 0x0 RPL Received Packet Length 0 8 read-only RPREL UART CEA709.1-B Received Preamble Length 0x2E 8 read-only n 0x0 0x0 RPREL Received Preamble Length 0 8 read-only RWFIFO UART FIFO Receive Watermark 0x15 8 read-write n 0x0 0x0 RXWATER Receive Watermark 0 8 read-write S1 UART Status Register 1 0x4 8 read-only n 0x0 0x0 FE Framing Error Flag 1 1 read-only 0 No framing error detected. #0 1 Framing error. #1 IDLE Idle Line Flag 4 1 read-only 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared. #0 1 Receiver input has become idle or the flag has not been cleared since it last asserted. #1 NF Noise Flag 2 1 read-only 0 No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise. #0 1 At least one dataword was received with noise detected since the last time the flag was cleared. #1 OR Receiver Overrun Flag 3 1 read-only 0 No overrun has occurred since the last time the flag was cleared. #0 1 Overrun has occurred or the overrun flag has not been cleared since the last overrun occured. #1 PF Parity Error Flag 0 1 read-only 0 No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error. #0 1 At least one dataword was received with a parity error since the last time this flag was cleared. #1 RDRF Receive Data Register Full Flag 5 1 read-only 0 The number of datawords in the receive buffer is less than the number indicated by RXWATER. #0 1 The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared. #1 TC Transmit Complete Flag 6 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 7 1 read-only 0 The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER]. #0 1 The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared. #1 S2 UART Status Register 2 0x5 8 read-write n 0x0 0x0 BRK13 Break Transmit Character Length 2 1 read-write 0 Break character is 10, 11, or 12 bits long. #0 1 Break character is 13 or 14 bits long. #1 LBKDE LIN Break Detection Enable 1 1 read-write 0 Break character is detected at one of the following lengths: 10 bit times if C1[M] = 0 11 bit times if C1[M] = 1 and C4[M10] = 0 12 bit times if C1[M] = 1, C4[M10] = 1, and S1[PE] = 1 #0 1 Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1. #1 LBKDIF LIN Break Detect Interrupt Flag 7 1 read-write 0 No LIN break character detected. #0 1 LIN break character detected. #1 MSBF Most Significant Bit First 5 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE]. #1 RAF Receiver Active Flag 0 1 read-only 0 UART receiver idle/inactive waiting for a start bit. #0 1 UART receiver active, RxD input not idle. #1 RWUID Receive Wakeup Idle Detect 3 1 read-write 0 S1[IDLE] is not set upon detection of an idle character. #0 1 S1[IDLE] is set upon detection of an idle character. #1 RXEDGIF RxD Pin Active Edge Interrupt Flag 6 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 RXINV Receive Data Inversion 4 1 read-write 0 Receive data is not inverted. #0 1 Receive data is inverted. #1 S3 UART CEA709.1-B Status Register 0x2B 8 read-write n 0x0 0x0 ISD Initial Sync Detect 5 1 read-only 0 Initial sync is not detected. #0 1 Initial sync is detected. #1 PCTEF Packet Cycle Timer Expired Flag 2 1 read-write 0 Packet cycle time has not expired. #0 1 Packet cycle time has expired. #1 PEF Preamble Error Flag 7 1 read-write 0 Preamble is correct. #0 1 Preamble has an error. #1 PRXF Packet Received Flag 4 1 read-write 0 Packet is not received. #0 1 Packet is received. #1 PSF Preamble Start Flag 1 1 read-write 0 Preamble start is not detected. #0 1 Preamble start is detected. #1 PTXF Packet Transmitted Flag 3 1 read-write 0 Packet transmission is not complete. #0 1 Packet transmission is complete. #1 TXFF Transmission Fail Flag 0 1 read-write 0 Transmission continues normally. #0 1 Transmission has failed. #1 WBEF Wbase Expired Flag 6 1 read-write 0 WBASE time period has not expired. #0 1 WBASE time period has expired after beta1 time slots. #1 S4 UART CEA709.1-B Status Register 0x2C 8 read-write n 0x0 0x0 CDET CDET 2 2 read-write 00 No collision. #00 01 Collision occurred during preamble. #01 10 Collision occurred during data. #10 11 Collision occurred during line code violation. #11 FE Framing Error 0 1 read-write 0 Received packet is byte bound. #0 1 Received packet is not byte bound. #1 ILCV Improper Line Code Violation 1 1 read-write 0 Line code violation received is proper. #0 1 Line code violation received is improper, that is, less than three bit periods. #1 INITF Initial Synchronization Fail Flag 4 1 read-only 0 Initial synchronization has not failed. #0 1 Initial synchronization has failed. #1 RESERVED no description available 5 3 read-only SDTH UART CEA709.1-B Secondary Delay Timer High 0x25 8 read-write n 0x0 0x0 SDTH Secondary Delay Timer High 0 8 read-write SDTL UART CEA709.1-B Secondary Delay Timer Low 0x26 8 read-write n 0x0 0x0 SDTL Secondary Delay Timer Low 0 8 read-write SFIFO UART FIFO Status Register 0x12 8 read-write n 0x0 0x0 RESERVED no description available 3 3 read-only RXEMPT Receive Buffer/FIFO Empty 6 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 RXOF Receiver Buffer Overflow Flag 2 1 read-write 0 No receive buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer overflow has occurred since the last time the flag was cleared. #1 RXUF Receiver Buffer Underflow Flag 0 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 TXEMPT Transmit Buffer/FIFO Empty 7 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 TXOF Transmitter Buffer Overflow Flag 1 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 TCFIFO UART FIFO Transmit Count 0x14 8 read-only n 0x0 0x0 TXCOUNT Transmit Counter 0 8 read-only TIDT UART CEA709.1-B Transmit Indeterminate Time 0x31 8 read-write n 0x0 0x0 TIDT CEA709.1-B Transmit IDT Register 0 8 read-write TL7816 UART 7816 Transmit Length Register 0x1F 8 read-write n 0x0 0x0 TLEN Transmit Length 0 8 read-write TPL UART CEA709.1-B Transmit Packet Length 0x28 8 read-write n 0x0 0x0 TPL Transmit Packet Length Register 0 8 read-write TWFIFO UART FIFO Transmit Watermark 0x13 8 read-write n 0x0 0x0 TXWATER Transmit Watermark 0 8 read-write WB UART CEA709.1-B WBASE 0x2A 8 read-write n 0x0 0x0 WBASE CEA709.1-B WBASE register 0 8 read-write WF7816 UART 7816 Wait FD Register 0x1D 8 read-write n 0x0 0x0 GTFD FD Multiplier 0 8 read-write WN7816 UART 7816 Wait N Register 0x1C 8 read-write n 0x0 0x0 GTN Guard Band N 0 8 read-write WP7816T0 UART 7816 Wait Parameter Register UART0 0x1B 8 read-write n 0x0 0x0 WI Wait Timer Interrupt (C7816[TTYPE] = 0) 0 8 read-write WP7816T1 UART 7816 Wait Parameter Register UART0 0x1B 8 read-write n 0x0 0x0 BWI Block Wait Time Integer(C7816[TTYPE] = 1) 0 4 read-write CWI Character Wait Time Integer (C7816[TTYPE] = 1) 4 4 read-write UART1 Serial Communication Interface UART 0x0 0x0 0x20 registers n UART1_RX_TX 47 UART1_ERR 48 INT_UART1_RX_TX 63 INT_UART1_ERR 64 BDH UART Baud Rate Registers: High 0x0 8 read-write n 0x0 0x0 LBKDIE LIN Break Detect Interrupt Enable 7 1 read-write 0 LBKDIF interrupt requests disabled. #0 1 LBKDIF interrupt requests enabled. #1 RESERVED no description available 5 1 read-only RXEDGIE RxD Input Active Edge Interrupt Enable 6 1 read-write 0 Hardware interrupts from RXEDGIF disabled using polling. #0 1 RXEDGIF interrupt request enabled. #1 SBR UART Baud Rate Bits 0 5 read-write BDL UART Baud Rate Registers: Low 0x1 8 read-write n 0x0 0x0 SBR UART Baud Rate Bits 0 8 read-write C1 UART Control Register 1 0x2 8 read-write n 0x0 0x0 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation. #0 1 Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC. #1 M 9-bit or 8-bit Mode Select 4 1 read-write 0 Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. #0 1 Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. #1 PE Parity Enable 1 1 read-write 0 Parity function disabled. #0 1 Parity function enabled. #1 PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 RSRC Receiver Source Select 5 1 read-write 0 Selects internal loop back mode. The receiver input is internally connected to transmitter output. #0 1 Single wire UART mode where the receiver input is connected to the transmit pin input signal. #1 UARTSWAI UART Stops in Wait Mode 6 1 read-write 0 UART clock continues to run in Wait mode. #0 1 UART clock freezes while CPU is in Wait mode. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Idle line wakeup. #0 1 Address mark wakeup. #1 C2 UART Control Register 2 0x3 8 read-write n 0x0 0x0 ILIE Idle Line Interrupt Enable 4 1 read-write 0 IDLE interrupt requests disabled. #0 1 IDLE interrupt requests enabled. #1 RE Receiver Enable 2 1 read-write 0 Receiver off. #0 1 Receiver on. #1 RIE Receiver Full Interrupt or DMA Transfer Enable 5 1 read-write 0 RDRF interrupt and DMA transfer requests disabled. #0 1 RDRF interrupt or DMA transfer requests enabled. #1 RWU Receiver Wakeup Control 1 1 read-write 0 Normal operation. #0 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. #1 SBK Send Break 0 1 read-write 0 Normal transmitter operation. #0 1 Queue break characters to be sent. #1 TCIE Transmission Complete Interrupt Enable 6 1 read-write 0 TC interrupt requests disabled. #0 1 TC interrupt requests enabled. #1 TE Transmitter Enable 3 1 read-write 0 Transmitter off. #0 1 Transmitter on. #1 TIE Transmitter Interrupt or DMA Transfer Enable. 7 1 read-write 0 TDRE interrupt and DMA transfer requests disabled. #0 1 TDRE interrupt or DMA transfer requests enabled. #1 C3 UART Control Register 3 0x6 8 read-write n 0x0 0x0 FEIE Framing Error Interrupt Enable 1 1 read-write 0 FE interrupt requests are disabled. #0 1 FE interrupt requests are enabled. #1 NEIE Noise Error Interrupt Enable 2 1 read-write 0 NF interrupt requests are disabled. #0 1 NF interrupt requests are enabled. #1 ORIE Overrun Error Interrupt Enable 3 1 read-write 0 OR interrupts are disabled. #0 1 OR interrupt requests are enabled. #1 PEIE Parity Error Interrupt Enable 0 1 read-write 0 PF interrupt requests are disabled. #0 1 PF interrupt requests are enabled. #1 R8 Received Bit 8 7 1 read-only T8 Transmit Bit 8 6 1 read-write TXDIR Transmitter Pin Data Direction in Single-Wire mode 5 1 read-write 0 TXD pin is an input in single wire mode. #0 1 TXD pin is an output in single wire mode. #1 TXINV Transmit Data Inversion. 4 1 read-write 0 Transmit data is not inverted. #0 1 Transmit data is inverted. #1 C4 UART Control Register 4 0xA 8 read-write n 0x0 0x0 BRFA Baud Rate Fine Adjust 0 5 read-write M10 10-bit Mode select 5 1 read-write 0 The parity bit is the ninth bit in the serial transmission. #0 1 The parity bit is the tenth bit in the serial transmission. #1 MAEN1 Match Address Mode Enable 1 7 1 read-write 0 All data received is transferred to the data buffer if MAEN2 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled. #1 MAEN2 Match Address Mode Enable 2 6 1 read-write 0 All data received is transferred to the data buffer if MAEN1 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled. #1 C5 UART Control Register 5 0xB 8 read-write n 0x0 0x0 RDMAS Receiver Full DMA Select 5 1 read-write 0 If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service. #0 1 If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer. #1 RESERVED no description available 0 5 read-only RESERVED no description available 6 1 read-only TDMAS Transmitter DMA Select 7 1 read-write 0 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service. #0 1 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer. #1 C7816 UART 7816 Control Register 0x18 8 read-write n 0x0 0x0 ANACK Generate NACK on Error 3 1 read-write 0 No NACK is automatically generated. #0 1 A NACK is automatically generated if a parity error is detected or if an invalid initial character is detected. #1 INIT Detect Initial Character 2 1 read-write 0 Normal operating mode. Receiver does not seek to identify initial character. #0 1 Receiver searches for initial character. #1 ISO_7816E ISO-7816 Functionality Enabled 0 1 read-write 0 ISO-7816 functionality is turned off/not enabled. #0 1 ISO-7816 functionality is turned on/enabled. #1 ONACK Generate NACK on Overflow 4 1 read-write 0 The received data does not generate a NACK when the receipt of the data results in an overflow event. #0 1 If the receiver buffer overflows, a NACK is automatically sent on a received character. #1 RESERVED no description available 5 3 read-only TTYPE Transfer Type 1 1 read-write 0 T = 0 per the ISO-7816 specification. #0 1 T = 1 per the ISO-7816 specification. #1 CFIFO UART FIFO Control Register 0x11 8 read-write n 0x0 0x0 RESERVED no description available 3 3 read-only RXFLUSH Receive FIFO/Buffer Flush 6 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 RXOFE Receive FIFO Overflow Interrupt Enable 2 1 read-write 0 RXOF flag does not generate an interrupt to the host. #0 1 RXOF flag generates an interrupt to the host. #1 RXUFE Receive FIFO Underflow Interrupt Enable 0 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXFLUSH Transmit FIFO/Buffer Flush 7 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 1 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 D UART Data Register 0x7 8 read-write n 0x0 0x0 RT no description available 0 8 read-write ED UART Extended Data Register 0xC 8 read-only n 0x0 0x0 NOISY no description available 7 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 PARITYE no description available 6 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 RESERVED no description available 0 6 read-only ET7816 UART 7816 Error Threshold Register 0x1E 8 read-write n 0x0 0x0 RXTHRESHOLD Receive NACK Threshold 0 4 read-write TXTHRESHOLD Transmit NACK Threshold 4 4 read-write 0 TXT asserts on the first NACK that is received. #0 1 TXT asserts on the second NACK that is received. #1 IE7816 UART 7816 Interrupt Enable Register 0x19 8 read-write n 0x0 0x0 BWTE Block Wait Timer Interrupt Enable 5 1 read-write 0 The assertion of IS7816[BWT] does not result in the generation of an interrupt. #0 1 The assertion of IS7816[BWT] results in the generation of an interrupt. #1 CWTE Character Wait Timer Interrupt Enable 6 1 read-write 0 The assertion of IS7816[CWT] does not result in the generation of an interrupt. #0 1 The assertion of IS7816[CWT] results in the generation of an interrupt. #1 GTVE Guard Timer Violated Interrupt Enable 2 1 read-write 0 The assertion of IS7816[GTV] does not result in the generation of an interrupt. #0 1 The assertion of IS7816[GTV] results in the generation of an interrupt. #1 INITDE Initial Character Detected Interrupt Enable 4 1 read-write 0 The assertion of IS7816[INITD] does not result in the generation of an interrupt. #0 1 The assertion of IS7816[INITD] results in the generation of an interrupt. #1 RESERVED no description available 3 1 read-only RXTE Receive Threshold Exceeded Interrupt Enable 0 1 read-write 0 The assertion of IS7816[RXT] does not result in the generation of an interrupt. #0 1 The assertion of IS7816[RXT] results in the generation of an interrupt. #1 TXTE Transmit Threshold Exceeded Interrupt Enable 1 1 read-write 0 The assertion of IS7816[TXT] does not result in the generation of an interrupt. #0 1 The assertion of IS7816[TXT] results in the generation of an interrupt. #1 WTE Wait Timer Interrupt Enable 7 1 read-write 0 The assertion of IS7816[WT] does not result in the generation of an interrupt. #0 1 The assertion of IS7816[WT] results in the generation of an interrupt. #1 IR UART Infrared Register 0xE 8 read-write n 0x0 0x0 IREN Infrared enable 2 1 read-write 0 IR disabled. #0 1 IR enabled. #1 RESERVED no description available 3 5 read-only TNP Transmitter narrow pulse 0 2 read-write 00 3/16. #00 01 1/16. #01 10 1/32. #10 11 1/4. #11 IS7816 UART 7816 Interrupt Status Register 0x1A 8 read-write n 0x0 0x0 BWT Block Wait Timer Interrupt 5 1 read-write 0 Block wait time (BWT) has not been violated. #0 1 Block wait time (BWT) has been violated. #1 CWT Character Wait Timer Interrupt 6 1 read-write 0 Character wait time (CWT) has not been violated. #0 1 Character wait time (CWT) has been violated. #1 GTV Guard Timer Violated Interrupt 2 1 read-write 0 A guard time (GT, CGT, or BGT) has not been violated. #0 1 A guard time (GT, CGT, or BGT) has been violated. #1 INITD Initial Character Detected Interrupt 4 1 read-write 0 A valid initial character has not been received. #0 1 A valid initial character has been received. #1 RESERVED no description available 3 1 read-only RXT Receive Threshold Exceeded Interrupt 0 1 read-write 0 The number of consecutive NACKS generated as a result of parity errors and buffer overruns is less than or equal to the value in ET7816[RXTHRESHOLD]. #0 1 The number of consecutive NACKS generated as a result of parity errors and buffer overruns is greater than the value in ET7816[RXTHRESHOLD]. #1 TXT Transmit Threshold Exceeded Interrupt 1 1 read-write 0 The number of retries and corresponding NACKS does not exceed the value in ET7816[TXTHRESHOLD]. #0 1 The number of retries and corresponding NACKS exceeds the value in ET7816[TXTHRESHOLD]. #1 WT Wait Timer Interrupt 7 1 read-write 0 Wait time (WT) has not been violated. #0 1 Wait time (WT) has been violated. #1 MA1 UART Match Address Registers 1 0x8 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MA2 UART Match Address Registers 2 0x9 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MODEM UART Modem Register 0xD 8 read-write n 0x0 0x0 RESERVED no description available 4 4 read-only RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER]. #1 TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO) #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 PFIFO UART FIFO Parameters 0x10 8 read-write n 0x0 0x0 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 000 Receive FIFO/Buffer depth = 1 dataword. #000 001 Receive FIFO/Buffer depth = 4 datawords. #001 010 Receive FIFO/Buffer depth = 8 datawords. #010 011 Receive FIFO/Buffer depth = 16 datawords. #011 100 Receive FIFO/Buffer depth = 32 datawords. #100 101 Receive FIFO/Buffer depth = 64 datawords. #101 110 Receive FIFO/Buffer depth = 128 datawords. #110 111 Reserved. #111 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 000 Transmit FIFO/Buffer depth = 1 dataword. #000 001 Transmit FIFO/Buffer depth = 4 datawords. #001 010 Transmit FIFO/Buffer depth = 8 datawords. #010 011 Transmit FIFO/Buffer depth = 16 datawords. #011 100 Transmit FIFO/Buffer depth = 32 datawords. #100 101 Transmit FIFO/Buffer depth = 64 datawords. #101 110 Transmit FIFO/Buffer depth = 128 datawords. #110 111 Reserved. #111 RCFIFO UART FIFO Receive Count 0x16 8 read-only n 0x0 0x0 RXCOUNT Receive Counter 0 8 read-only RWFIFO UART FIFO Receive Watermark 0x15 8 read-write n 0x0 0x0 RXWATER Receive Watermark 0 8 read-write S1 UART Status Register 1 0x4 8 read-only n 0x0 0x0 FE Framing Error Flag 1 1 read-only 0 No framing error detected. #0 1 Framing error. #1 IDLE Idle Line Flag 4 1 read-only 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared. #0 1 Receiver input has become idle or the flag has not been cleared since it last asserted. #1 NF Noise Flag 2 1 read-only 0 No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise. #0 1 At least one dataword was received with noise detected since the last time the flag was cleared. #1 OR Receiver Overrun Flag 3 1 read-only 0 No overrun has occurred since the last time the flag was cleared. #0 1 Overrun has occurred or the overrun flag has not been cleared since the last overrun occured. #1 PF Parity Error Flag 0 1 read-only 0 No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error. #0 1 At least one dataword was received with a parity error since the last time this flag was cleared. #1 RDRF Receive Data Register Full Flag 5 1 read-only 0 The number of datawords in the receive buffer is less than the number indicated by RXWATER. #0 1 The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared. #1 TC Transmit Complete Flag 6 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 7 1 read-only 0 The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER]. #0 1 The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared. #1 S2 UART Status Register 2 0x5 8 read-write n 0x0 0x0 BRK13 Break Transmit Character Length 2 1 read-write 0 Break character is 10, 11, or 12 bits long. #0 1 Break character is 13 or 14 bits long. #1 LBKDE LIN Break Detection Enable 1 1 read-write 0 Break character is detected at one of the following lengths: 10 bit times if C1[M] = 0 11 bit times if C1[M] = 1 and C4[M10] = 0 12 bit times if C1[M] = 1, C4[M10] = 1, and S1[PE] = 1 #0 1 Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1. #1 LBKDIF LIN Break Detect Interrupt Flag 7 1 read-write 0 No LIN break character detected. #0 1 LIN break character detected. #1 MSBF Most Significant Bit First 5 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE]. #1 RAF Receiver Active Flag 0 1 read-only 0 UART receiver idle/inactive waiting for a start bit. #0 1 UART receiver active, RxD input not idle. #1 RWUID Receive Wakeup Idle Detect 3 1 read-write 0 S1[IDLE] is not set upon detection of an idle character. #0 1 S1[IDLE] is set upon detection of an idle character. #1 RXEDGIF RxD Pin Active Edge Interrupt Flag 6 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 RXINV Receive Data Inversion 4 1 read-write 0 Receive data is not inverted. #0 1 Receive data is inverted. #1 SFIFO UART FIFO Status Register 0x12 8 read-write n 0x0 0x0 RESERVED no description available 3 3 read-only RXEMPT Receive Buffer/FIFO Empty 6 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 RXOF Receiver Buffer Overflow Flag 2 1 read-write 0 No receive buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer overflow has occurred since the last time the flag was cleared. #1 RXUF Receiver Buffer Underflow Flag 0 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 TXEMPT Transmit Buffer/FIFO Empty 7 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 TXOF Transmitter Buffer Overflow Flag 1 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 TCFIFO UART FIFO Transmit Count 0x14 8 read-only n 0x0 0x0 TXCOUNT Transmit Counter 0 8 read-only TL7816 UART 7816 Transmit Length Register 0x1F 8 read-write n 0x0 0x0 TLEN Transmit Length 0 8 read-write TWFIFO UART FIFO Transmit Watermark 0x13 8 read-write n 0x0 0x0 TXWATER Transmit Watermark 0 8 read-write WF7816 UART 7816 Wait FD Register 0x1D 8 read-write n 0x0 0x0 GTFD FD Multiplier 0 8 read-write WN7816 UART 7816 Wait N Register 0x1C 8 read-write n 0x0 0x0 GTN Guard Band N 0 8 read-write WP7816T0 UART 7816 Wait Parameter Register UART1 0x1B 8 read-write n 0x0 0x0 WI Wait Timer Interrupt (C7816[TTYPE] = 0) 0 8 read-write WP7816T1 UART 7816 Wait Parameter Register UART1 0x1B 8 read-write n 0x0 0x0 BWI Block Wait Time Integer(C7816[TTYPE] = 1) 0 4 read-write CWI Character Wait Time Integer (C7816[TTYPE] = 1) 4 4 read-write UART2 Serial Communication Interface UART 0x0 0x0 0x17 registers n UART2_RX_TX 49 UART2_ERR 50 INT_UART2_RX_TX 65 INT_UART2_ERR 66 BDH UART Baud Rate Registers: High 0x0 8 read-write n 0x0 0x0 LBKDIE LIN Break Detect Interrupt Enable 7 1 read-write 0 LBKDIF interrupt requests disabled. #0 1 LBKDIF interrupt requests enabled. #1 RESERVED no description available 5 1 read-only RXEDGIE RxD Input Active Edge Interrupt Enable 6 1 read-write 0 Hardware interrupts from RXEDGIF disabled using polling. #0 1 RXEDGIF interrupt request enabled. #1 SBR UART Baud Rate Bits 0 5 read-write BDL UART Baud Rate Registers: Low 0x1 8 read-write n 0x0 0x0 SBR UART Baud Rate Bits 0 8 read-write C1 UART Control Register 1 0x2 8 read-write n 0x0 0x0 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation. #0 1 Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC. #1 M 9-bit or 8-bit Mode Select 4 1 read-write 0 Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. #0 1 Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. #1 PE Parity Enable 1 1 read-write 0 Parity function disabled. #0 1 Parity function enabled. #1 PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 RSRC Receiver Source Select 5 1 read-write 0 Selects internal loop back mode. The receiver input is internally connected to transmitter output. #0 1 Single wire UART mode where the receiver input is connected to the transmit pin input signal. #1 UARTSWAI UART Stops in Wait Mode 6 1 read-write 0 UART clock continues to run in Wait mode. #0 1 UART clock freezes while CPU is in Wait mode. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Idle line wakeup. #0 1 Address mark wakeup. #1 C2 UART Control Register 2 0x3 8 read-write n 0x0 0x0 ILIE Idle Line Interrupt Enable 4 1 read-write 0 IDLE interrupt requests disabled. #0 1 IDLE interrupt requests enabled. #1 RE Receiver Enable 2 1 read-write 0 Receiver off. #0 1 Receiver on. #1 RIE Receiver Full Interrupt or DMA Transfer Enable 5 1 read-write 0 RDRF interrupt and DMA transfer requests disabled. #0 1 RDRF interrupt or DMA transfer requests enabled. #1 RWU Receiver Wakeup Control 1 1 read-write 0 Normal operation. #0 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. #1 SBK Send Break 0 1 read-write 0 Normal transmitter operation. #0 1 Queue break characters to be sent. #1 TCIE Transmission Complete Interrupt Enable 6 1 read-write 0 TC interrupt requests disabled. #0 1 TC interrupt requests enabled. #1 TE Transmitter Enable 3 1 read-write 0 Transmitter off. #0 1 Transmitter on. #1 TIE Transmitter Interrupt or DMA Transfer Enable. 7 1 read-write 0 TDRE interrupt and DMA transfer requests disabled. #0 1 TDRE interrupt or DMA transfer requests enabled. #1 C3 UART Control Register 3 0x6 8 read-write n 0x0 0x0 FEIE Framing Error Interrupt Enable 1 1 read-write 0 FE interrupt requests are disabled. #0 1 FE interrupt requests are enabled. #1 NEIE Noise Error Interrupt Enable 2 1 read-write 0 NF interrupt requests are disabled. #0 1 NF interrupt requests are enabled. #1 ORIE Overrun Error Interrupt Enable 3 1 read-write 0 OR interrupts are disabled. #0 1 OR interrupt requests are enabled. #1 PEIE Parity Error Interrupt Enable 0 1 read-write 0 PF interrupt requests are disabled. #0 1 PF interrupt requests are enabled. #1 R8 Received Bit 8 7 1 read-only T8 Transmit Bit 8 6 1 read-write TXDIR Transmitter Pin Data Direction in Single-Wire mode 5 1 read-write 0 TXD pin is an input in single wire mode. #0 1 TXD pin is an output in single wire mode. #1 TXINV Transmit Data Inversion. 4 1 read-write 0 Transmit data is not inverted. #0 1 Transmit data is inverted. #1 C4 UART Control Register 4 0xA 8 read-write n 0x0 0x0 BRFA Baud Rate Fine Adjust 0 5 read-write M10 10-bit Mode select 5 1 read-write 0 The parity bit is the ninth bit in the serial transmission. #0 1 The parity bit is the tenth bit in the serial transmission. #1 MAEN1 Match Address Mode Enable 1 7 1 read-write 0 All data received is transferred to the data buffer if MAEN2 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled. #1 MAEN2 Match Address Mode Enable 2 6 1 read-write 0 All data received is transferred to the data buffer if MAEN1 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled. #1 C5 UART Control Register 5 0xB 8 read-write n 0x0 0x0 RDMAS Receiver Full DMA Select 5 1 read-write 0 If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service. #0 1 If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer. #1 RESERVED no description available 0 5 read-only RESERVED no description available 6 1 read-only TDMAS Transmitter DMA Select 7 1 read-write 0 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service. #0 1 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer. #1 CFIFO UART FIFO Control Register 0x11 8 read-write n 0x0 0x0 RESERVED no description available 3 3 read-only RXFLUSH Receive FIFO/Buffer Flush 6 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 RXOFE Receive FIFO Overflow Interrupt Enable 2 1 read-write 0 RXOF flag does not generate an interrupt to the host. #0 1 RXOF flag generates an interrupt to the host. #1 RXUFE Receive FIFO Underflow Interrupt Enable 0 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXFLUSH Transmit FIFO/Buffer Flush 7 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 1 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 D UART Data Register 0x7 8 read-write n 0x0 0x0 RT no description available 0 8 read-write ED UART Extended Data Register 0xC 8 read-only n 0x0 0x0 NOISY no description available 7 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 PARITYE no description available 6 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 RESERVED no description available 0 6 read-only IR UART Infrared Register 0xE 8 read-write n 0x0 0x0 IREN Infrared enable 2 1 read-write 0 IR disabled. #0 1 IR enabled. #1 RESERVED no description available 3 5 read-only TNP Transmitter narrow pulse 0 2 read-write 00 3/16. #00 01 1/16. #01 10 1/32. #10 11 1/4. #11 MA1 UART Match Address Registers 1 0x8 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MA2 UART Match Address Registers 2 0x9 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MODEM UART Modem Register 0xD 8 read-write n 0x0 0x0 RESERVED no description available 4 4 read-only RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER]. #1 TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO) #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 PFIFO UART FIFO Parameters 0x10 8 read-write n 0x0 0x0 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 000 Receive FIFO/Buffer depth = 1 dataword. #000 001 Receive FIFO/Buffer depth = 4 datawords. #001 010 Receive FIFO/Buffer depth = 8 datawords. #010 011 Receive FIFO/Buffer depth = 16 datawords. #011 100 Receive FIFO/Buffer depth = 32 datawords. #100 101 Receive FIFO/Buffer depth = 64 datawords. #101 110 Receive FIFO/Buffer depth = 128 datawords. #110 111 Reserved. #111 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 000 Transmit FIFO/Buffer depth = 1 dataword. #000 001 Transmit FIFO/Buffer depth = 4 datawords. #001 010 Transmit FIFO/Buffer depth = 8 datawords. #010 011 Transmit FIFO/Buffer depth = 16 datawords. #011 100 Transmit FIFO/Buffer depth = 32 datawords. #100 101 Transmit FIFO/Buffer depth = 64 datawords. #101 110 Transmit FIFO/Buffer depth = 128 datawords. #110 111 Reserved. #111 RCFIFO UART FIFO Receive Count 0x16 8 read-only n 0x0 0x0 RXCOUNT Receive Counter 0 8 read-only RWFIFO UART FIFO Receive Watermark 0x15 8 read-write n 0x0 0x0 RXWATER Receive Watermark 0 8 read-write S1 UART Status Register 1 0x4 8 read-only n 0x0 0x0 FE Framing Error Flag 1 1 read-only 0 No framing error detected. #0 1 Framing error. #1 IDLE Idle Line Flag 4 1 read-only 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared. #0 1 Receiver input has become idle or the flag has not been cleared since it last asserted. #1 NF Noise Flag 2 1 read-only 0 No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise. #0 1 At least one dataword was received with noise detected since the last time the flag was cleared. #1 OR Receiver Overrun Flag 3 1 read-only 0 No overrun has occurred since the last time the flag was cleared. #0 1 Overrun has occurred or the overrun flag has not been cleared since the last overrun occured. #1 PF Parity Error Flag 0 1 read-only 0 No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error. #0 1 At least one dataword was received with a parity error since the last time this flag was cleared. #1 RDRF Receive Data Register Full Flag 5 1 read-only 0 The number of datawords in the receive buffer is less than the number indicated by RXWATER. #0 1 The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared. #1 TC Transmit Complete Flag 6 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 7 1 read-only 0 The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER]. #0 1 The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared. #1 S2 UART Status Register 2 0x5 8 read-write n 0x0 0x0 BRK13 Break Transmit Character Length 2 1 read-write 0 Break character is 10, 11, or 12 bits long. #0 1 Break character is 13 or 14 bits long. #1 LBKDE LIN Break Detection Enable 1 1 read-write 0 Break character is detected at one of the following lengths: 10 bit times if C1[M] = 0 11 bit times if C1[M] = 1 and C4[M10] = 0 12 bit times if C1[M] = 1, C4[M10] = 1, and S1[PE] = 1 #0 1 Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1. #1 LBKDIF LIN Break Detect Interrupt Flag 7 1 read-write 0 No LIN break character detected. #0 1 LIN break character detected. #1 MSBF Most Significant Bit First 5 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE]. #1 RAF Receiver Active Flag 0 1 read-only 0 UART receiver idle/inactive waiting for a start bit. #0 1 UART receiver active, RxD input not idle. #1 RWUID Receive Wakeup Idle Detect 3 1 read-write 0 S1[IDLE] is not set upon detection of an idle character. #0 1 S1[IDLE] is set upon detection of an idle character. #1 RXEDGIF RxD Pin Active Edge Interrupt Flag 6 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 RXINV Receive Data Inversion 4 1 read-write 0 Receive data is not inverted. #0 1 Receive data is inverted. #1 SFIFO UART FIFO Status Register 0x12 8 read-write n 0x0 0x0 RESERVED no description available 3 3 read-only RXEMPT Receive Buffer/FIFO Empty 6 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 RXOF Receiver Buffer Overflow Flag 2 1 read-write 0 No receive buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer overflow has occurred since the last time the flag was cleared. #1 RXUF Receiver Buffer Underflow Flag 0 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 TXEMPT Transmit Buffer/FIFO Empty 7 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 TXOF Transmitter Buffer Overflow Flag 1 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 TCFIFO UART FIFO Transmit Count 0x14 8 read-only n 0x0 0x0 TXCOUNT Transmit Counter 0 8 read-only TWFIFO UART FIFO Transmit Watermark 0x13 8 read-write n 0x0 0x0 TXWATER Transmit Watermark 0 8 read-write UART3 Serial Communication Interface UART 0x0 0x0 0x17 registers n UART3_RX_TX 51 UART3_ERR 52 INT_UART3_RX_TX 67 INT_UART3_ERR 68 BDH UART Baud Rate Registers: High 0x0 8 read-write n 0x0 0x0 LBKDIE LIN Break Detect Interrupt Enable 7 1 read-write 0 LBKDIF interrupt requests disabled. #0 1 LBKDIF interrupt requests enabled. #1 RESERVED no description available 5 1 read-only RXEDGIE RxD Input Active Edge Interrupt Enable 6 1 read-write 0 Hardware interrupts from RXEDGIF disabled using polling. #0 1 RXEDGIF interrupt request enabled. #1 SBR UART Baud Rate Bits 0 5 read-write BDL UART Baud Rate Registers: Low 0x1 8 read-write n 0x0 0x0 SBR UART Baud Rate Bits 0 8 read-write C1 UART Control Register 1 0x2 8 read-write n 0x0 0x0 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation. #0 1 Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC. #1 M 9-bit or 8-bit Mode Select 4 1 read-write 0 Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. #0 1 Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. #1 PE Parity Enable 1 1 read-write 0 Parity function disabled. #0 1 Parity function enabled. #1 PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 RSRC Receiver Source Select 5 1 read-write 0 Selects internal loop back mode. The receiver input is internally connected to transmitter output. #0 1 Single wire UART mode where the receiver input is connected to the transmit pin input signal. #1 UARTSWAI UART Stops in Wait Mode 6 1 read-write 0 UART clock continues to run in Wait mode. #0 1 UART clock freezes while CPU is in Wait mode. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Idle line wakeup. #0 1 Address mark wakeup. #1 C2 UART Control Register 2 0x3 8 read-write n 0x0 0x0 ILIE Idle Line Interrupt Enable 4 1 read-write 0 IDLE interrupt requests disabled. #0 1 IDLE interrupt requests enabled. #1 RE Receiver Enable 2 1 read-write 0 Receiver off. #0 1 Receiver on. #1 RIE Receiver Full Interrupt or DMA Transfer Enable 5 1 read-write 0 RDRF interrupt and DMA transfer requests disabled. #0 1 RDRF interrupt or DMA transfer requests enabled. #1 RWU Receiver Wakeup Control 1 1 read-write 0 Normal operation. #0 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. #1 SBK Send Break 0 1 read-write 0 Normal transmitter operation. #0 1 Queue break characters to be sent. #1 TCIE Transmission Complete Interrupt Enable 6 1 read-write 0 TC interrupt requests disabled. #0 1 TC interrupt requests enabled. #1 TE Transmitter Enable 3 1 read-write 0 Transmitter off. #0 1 Transmitter on. #1 TIE Transmitter Interrupt or DMA Transfer Enable. 7 1 read-write 0 TDRE interrupt and DMA transfer requests disabled. #0 1 TDRE interrupt or DMA transfer requests enabled. #1 C3 UART Control Register 3 0x6 8 read-write n 0x0 0x0 FEIE Framing Error Interrupt Enable 1 1 read-write 0 FE interrupt requests are disabled. #0 1 FE interrupt requests are enabled. #1 NEIE Noise Error Interrupt Enable 2 1 read-write 0 NF interrupt requests are disabled. #0 1 NF interrupt requests are enabled. #1 ORIE Overrun Error Interrupt Enable 3 1 read-write 0 OR interrupts are disabled. #0 1 OR interrupt requests are enabled. #1 PEIE Parity Error Interrupt Enable 0 1 read-write 0 PF interrupt requests are disabled. #0 1 PF interrupt requests are enabled. #1 R8 Received Bit 8 7 1 read-only T8 Transmit Bit 8 6 1 read-write TXDIR Transmitter Pin Data Direction in Single-Wire mode 5 1 read-write 0 TXD pin is an input in single wire mode. #0 1 TXD pin is an output in single wire mode. #1 TXINV Transmit Data Inversion. 4 1 read-write 0 Transmit data is not inverted. #0 1 Transmit data is inverted. #1 C4 UART Control Register 4 0xA 8 read-write n 0x0 0x0 BRFA Baud Rate Fine Adjust 0 5 read-write M10 10-bit Mode select 5 1 read-write 0 The parity bit is the ninth bit in the serial transmission. #0 1 The parity bit is the tenth bit in the serial transmission. #1 MAEN1 Match Address Mode Enable 1 7 1 read-write 0 All data received is transferred to the data buffer if MAEN2 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled. #1 MAEN2 Match Address Mode Enable 2 6 1 read-write 0 All data received is transferred to the data buffer if MAEN1 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled. #1 C5 UART Control Register 5 0xB 8 read-write n 0x0 0x0 RDMAS Receiver Full DMA Select 5 1 read-write 0 If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service. #0 1 If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer. #1 RESERVED no description available 0 5 read-only RESERVED no description available 6 1 read-only TDMAS Transmitter DMA Select 7 1 read-write 0 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service. #0 1 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer. #1 CFIFO UART FIFO Control Register 0x11 8 read-write n 0x0 0x0 RESERVED no description available 3 3 read-only RXFLUSH Receive FIFO/Buffer Flush 6 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 RXOFE Receive FIFO Overflow Interrupt Enable 2 1 read-write 0 RXOF flag does not generate an interrupt to the host. #0 1 RXOF flag generates an interrupt to the host. #1 RXUFE Receive FIFO Underflow Interrupt Enable 0 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXFLUSH Transmit FIFO/Buffer Flush 7 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 1 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 D UART Data Register 0x7 8 read-write n 0x0 0x0 RT no description available 0 8 read-write ED UART Extended Data Register 0xC 8 read-only n 0x0 0x0 NOISY no description available 7 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 PARITYE no description available 6 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 RESERVED no description available 0 6 read-only IR UART Infrared Register 0xE 8 read-write n 0x0 0x0 IREN Infrared enable 2 1 read-write 0 IR disabled. #0 1 IR enabled. #1 RESERVED no description available 3 5 read-only TNP Transmitter narrow pulse 0 2 read-write 00 3/16. #00 01 1/16. #01 10 1/32. #10 11 1/4. #11 MA1 UART Match Address Registers 1 0x8 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MA2 UART Match Address Registers 2 0x9 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MODEM UART Modem Register 0xD 8 read-write n 0x0 0x0 RESERVED no description available 4 4 read-only RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER]. #1 TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO) #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 PFIFO UART FIFO Parameters 0x10 8 read-write n 0x0 0x0 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 000 Receive FIFO/Buffer depth = 1 dataword. #000 001 Receive FIFO/Buffer depth = 4 datawords. #001 010 Receive FIFO/Buffer depth = 8 datawords. #010 011 Receive FIFO/Buffer depth = 16 datawords. #011 100 Receive FIFO/Buffer depth = 32 datawords. #100 101 Receive FIFO/Buffer depth = 64 datawords. #101 110 Receive FIFO/Buffer depth = 128 datawords. #110 111 Reserved. #111 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 000 Transmit FIFO/Buffer depth = 1 dataword. #000 001 Transmit FIFO/Buffer depth = 4 datawords. #001 010 Transmit FIFO/Buffer depth = 8 datawords. #010 011 Transmit FIFO/Buffer depth = 16 datawords. #011 100 Transmit FIFO/Buffer depth = 32 datawords. #100 101 Transmit FIFO/Buffer depth = 64 datawords. #101 110 Transmit FIFO/Buffer depth = 128 datawords. #110 111 Reserved. #111 RCFIFO UART FIFO Receive Count 0x16 8 read-only n 0x0 0x0 RXCOUNT Receive Counter 0 8 read-only RWFIFO UART FIFO Receive Watermark 0x15 8 read-write n 0x0 0x0 RXWATER Receive Watermark 0 8 read-write S1 UART Status Register 1 0x4 8 read-only n 0x0 0x0 FE Framing Error Flag 1 1 read-only 0 No framing error detected. #0 1 Framing error. #1 IDLE Idle Line Flag 4 1 read-only 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared. #0 1 Receiver input has become idle or the flag has not been cleared since it last asserted. #1 NF Noise Flag 2 1 read-only 0 No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise. #0 1 At least one dataword was received with noise detected since the last time the flag was cleared. #1 OR Receiver Overrun Flag 3 1 read-only 0 No overrun has occurred since the last time the flag was cleared. #0 1 Overrun has occurred or the overrun flag has not been cleared since the last overrun occured. #1 PF Parity Error Flag 0 1 read-only 0 No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error. #0 1 At least one dataword was received with a parity error since the last time this flag was cleared. #1 RDRF Receive Data Register Full Flag 5 1 read-only 0 The number of datawords in the receive buffer is less than the number indicated by RXWATER. #0 1 The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared. #1 TC Transmit Complete Flag 6 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 7 1 read-only 0 The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER]. #0 1 The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared. #1 S2 UART Status Register 2 0x5 8 read-write n 0x0 0x0 BRK13 Break Transmit Character Length 2 1 read-write 0 Break character is 10, 11, or 12 bits long. #0 1 Break character is 13 or 14 bits long. #1 LBKDE LIN Break Detection Enable 1 1 read-write 0 Break character is detected at one of the following lengths: 10 bit times if C1[M] = 0 11 bit times if C1[M] = 1 and C4[M10] = 0 12 bit times if C1[M] = 1, C4[M10] = 1, and S1[PE] = 1 #0 1 Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1. #1 LBKDIF LIN Break Detect Interrupt Flag 7 1 read-write 0 No LIN break character detected. #0 1 LIN break character detected. #1 MSBF Most Significant Bit First 5 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE]. #1 RAF Receiver Active Flag 0 1 read-only 0 UART receiver idle/inactive waiting for a start bit. #0 1 UART receiver active, RxD input not idle. #1 RWUID Receive Wakeup Idle Detect 3 1 read-write 0 S1[IDLE] is not set upon detection of an idle character. #0 1 S1[IDLE] is set upon detection of an idle character. #1 RXEDGIF RxD Pin Active Edge Interrupt Flag 6 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 RXINV Receive Data Inversion 4 1 read-write 0 Receive data is not inverted. #0 1 Receive data is inverted. #1 SFIFO UART FIFO Status Register 0x12 8 read-write n 0x0 0x0 RESERVED no description available 3 3 read-only RXEMPT Receive Buffer/FIFO Empty 6 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 RXOF Receiver Buffer Overflow Flag 2 1 read-write 0 No receive buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer overflow has occurred since the last time the flag was cleared. #1 RXUF Receiver Buffer Underflow Flag 0 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 TXEMPT Transmit Buffer/FIFO Empty 7 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 TXOF Transmitter Buffer Overflow Flag 1 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 TCFIFO UART FIFO Transmit Count 0x14 8 read-only n 0x0 0x0 TXCOUNT Transmit Counter 0 8 read-only TWFIFO UART FIFO Transmit Watermark 0x13 8 read-write n 0x0 0x0 TXWATER Transmit Watermark 0 8 read-write UART4 Serial Communication Interface UART 0x0 0x0 0x17 registers n UART4_RX_TX 53 UART4_ERR 54 INT_UART4_RX_TX 69 INT_UART4_ERR 70 BDH UART Baud Rate Registers: High 0x0 8 read-write n 0x0 0x0 LBKDIE LIN Break Detect Interrupt Enable 7 1 read-write 0 LBKDIF interrupt requests disabled. #0 1 LBKDIF interrupt requests enabled. #1 RESERVED no description available 5 1 read-only RXEDGIE RxD Input Active Edge Interrupt Enable 6 1 read-write 0 Hardware interrupts from RXEDGIF disabled using polling. #0 1 RXEDGIF interrupt request enabled. #1 SBR UART Baud Rate Bits 0 5 read-write BDL UART Baud Rate Registers: Low 0x1 8 read-write n 0x0 0x0 SBR UART Baud Rate Bits 0 8 read-write C1 UART Control Register 1 0x2 8 read-write n 0x0 0x0 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation. #0 1 Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC. #1 M 9-bit or 8-bit Mode Select 4 1 read-write 0 Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. #0 1 Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. #1 PE Parity Enable 1 1 read-write 0 Parity function disabled. #0 1 Parity function enabled. #1 PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 RSRC Receiver Source Select 5 1 read-write 0 Selects internal loop back mode. The receiver input is internally connected to transmitter output. #0 1 Single wire UART mode where the receiver input is connected to the transmit pin input signal. #1 UARTSWAI UART Stops in Wait Mode 6 1 read-write 0 UART clock continues to run in Wait mode. #0 1 UART clock freezes while CPU is in Wait mode. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Idle line wakeup. #0 1 Address mark wakeup. #1 C2 UART Control Register 2 0x3 8 read-write n 0x0 0x0 ILIE Idle Line Interrupt Enable 4 1 read-write 0 IDLE interrupt requests disabled. #0 1 IDLE interrupt requests enabled. #1 RE Receiver Enable 2 1 read-write 0 Receiver off. #0 1 Receiver on. #1 RIE Receiver Full Interrupt or DMA Transfer Enable 5 1 read-write 0 RDRF interrupt and DMA transfer requests disabled. #0 1 RDRF interrupt or DMA transfer requests enabled. #1 RWU Receiver Wakeup Control 1 1 read-write 0 Normal operation. #0 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. #1 SBK Send Break 0 1 read-write 0 Normal transmitter operation. #0 1 Queue break characters to be sent. #1 TCIE Transmission Complete Interrupt Enable 6 1 read-write 0 TC interrupt requests disabled. #0 1 TC interrupt requests enabled. #1 TE Transmitter Enable 3 1 read-write 0 Transmitter off. #0 1 Transmitter on. #1 TIE Transmitter Interrupt or DMA Transfer Enable. 7 1 read-write 0 TDRE interrupt and DMA transfer requests disabled. #0 1 TDRE interrupt or DMA transfer requests enabled. #1 C3 UART Control Register 3 0x6 8 read-write n 0x0 0x0 FEIE Framing Error Interrupt Enable 1 1 read-write 0 FE interrupt requests are disabled. #0 1 FE interrupt requests are enabled. #1 NEIE Noise Error Interrupt Enable 2 1 read-write 0 NF interrupt requests are disabled. #0 1 NF interrupt requests are enabled. #1 ORIE Overrun Error Interrupt Enable 3 1 read-write 0 OR interrupts are disabled. #0 1 OR interrupt requests are enabled. #1 PEIE Parity Error Interrupt Enable 0 1 read-write 0 PF interrupt requests are disabled. #0 1 PF interrupt requests are enabled. #1 R8 Received Bit 8 7 1 read-only T8 Transmit Bit 8 6 1 read-write TXDIR Transmitter Pin Data Direction in Single-Wire mode 5 1 read-write 0 TXD pin is an input in single wire mode. #0 1 TXD pin is an output in single wire mode. #1 TXINV Transmit Data Inversion. 4 1 read-write 0 Transmit data is not inverted. #0 1 Transmit data is inverted. #1 C4 UART Control Register 4 0xA 8 read-write n 0x0 0x0 BRFA Baud Rate Fine Adjust 0 5 read-write M10 10-bit Mode select 5 1 read-write 0 The parity bit is the ninth bit in the serial transmission. #0 1 The parity bit is the tenth bit in the serial transmission. #1 MAEN1 Match Address Mode Enable 1 7 1 read-write 0 All data received is transferred to the data buffer if MAEN2 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled. #1 MAEN2 Match Address Mode Enable 2 6 1 read-write 0 All data received is transferred to the data buffer if MAEN1 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled. #1 C5 UART Control Register 5 0xB 8 read-write n 0x0 0x0 RDMAS Receiver Full DMA Select 5 1 read-write 0 If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service. #0 1 If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer. #1 RESERVED no description available 0 5 read-only RESERVED no description available 6 1 read-only TDMAS Transmitter DMA Select 7 1 read-write 0 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service. #0 1 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer. #1 CFIFO UART FIFO Control Register 0x11 8 read-write n 0x0 0x0 RESERVED no description available 3 3 read-only RXFLUSH Receive FIFO/Buffer Flush 6 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 RXOFE Receive FIFO Overflow Interrupt Enable 2 1 read-write 0 RXOF flag does not generate an interrupt to the host. #0 1 RXOF flag generates an interrupt to the host. #1 RXUFE Receive FIFO Underflow Interrupt Enable 0 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXFLUSH Transmit FIFO/Buffer Flush 7 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 1 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 D UART Data Register 0x7 8 read-write n 0x0 0x0 RT no description available 0 8 read-write ED UART Extended Data Register 0xC 8 read-only n 0x0 0x0 NOISY no description available 7 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 PARITYE no description available 6 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 RESERVED no description available 0 6 read-only IR UART Infrared Register 0xE 8 read-write n 0x0 0x0 IREN Infrared enable 2 1 read-write 0 IR disabled. #0 1 IR enabled. #1 RESERVED no description available 3 5 read-only TNP Transmitter narrow pulse 0 2 read-write 00 3/16. #00 01 1/16. #01 10 1/32. #10 11 1/4. #11 MA1 UART Match Address Registers 1 0x8 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MA2 UART Match Address Registers 2 0x9 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MODEM UART Modem Register 0xD 8 read-write n 0x0 0x0 RESERVED no description available 4 4 read-only RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER]. #1 TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO) #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 PFIFO UART FIFO Parameters 0x10 8 read-write n 0x0 0x0 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 000 Receive FIFO/Buffer depth = 1 dataword. #000 001 Receive FIFO/Buffer depth = 4 datawords. #001 010 Receive FIFO/Buffer depth = 8 datawords. #010 011 Receive FIFO/Buffer depth = 16 datawords. #011 100 Receive FIFO/Buffer depth = 32 datawords. #100 101 Receive FIFO/Buffer depth = 64 datawords. #101 110 Receive FIFO/Buffer depth = 128 datawords. #110 111 Reserved. #111 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 000 Transmit FIFO/Buffer depth = 1 dataword. #000 001 Transmit FIFO/Buffer depth = 4 datawords. #001 010 Transmit FIFO/Buffer depth = 8 datawords. #010 011 Transmit FIFO/Buffer depth = 16 datawords. #011 100 Transmit FIFO/Buffer depth = 32 datawords. #100 101 Transmit FIFO/Buffer depth = 64 datawords. #101 110 Transmit FIFO/Buffer depth = 128 datawords. #110 111 Reserved. #111 RCFIFO UART FIFO Receive Count 0x16 8 read-only n 0x0 0x0 RXCOUNT Receive Counter 0 8 read-only RWFIFO UART FIFO Receive Watermark 0x15 8 read-write n 0x0 0x0 RXWATER Receive Watermark 0 8 read-write S1 UART Status Register 1 0x4 8 read-only n 0x0 0x0 FE Framing Error Flag 1 1 read-only 0 No framing error detected. #0 1 Framing error. #1 IDLE Idle Line Flag 4 1 read-only 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared. #0 1 Receiver input has become idle or the flag has not been cleared since it last asserted. #1 NF Noise Flag 2 1 read-only 0 No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise. #0 1 At least one dataword was received with noise detected since the last time the flag was cleared. #1 OR Receiver Overrun Flag 3 1 read-only 0 No overrun has occurred since the last time the flag was cleared. #0 1 Overrun has occurred or the overrun flag has not been cleared since the last overrun occured. #1 PF Parity Error Flag 0 1 read-only 0 No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error. #0 1 At least one dataword was received with a parity error since the last time this flag was cleared. #1 RDRF Receive Data Register Full Flag 5 1 read-only 0 The number of datawords in the receive buffer is less than the number indicated by RXWATER. #0 1 The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared. #1 TC Transmit Complete Flag 6 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 7 1 read-only 0 The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER]. #0 1 The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared. #1 S2 UART Status Register 2 0x5 8 read-write n 0x0 0x0 BRK13 Break Transmit Character Length 2 1 read-write 0 Break character is 10, 11, or 12 bits long. #0 1 Break character is 13 or 14 bits long. #1 LBKDE LIN Break Detection Enable 1 1 read-write 0 Break character is detected at one of the following lengths: 10 bit times if C1[M] = 0 11 bit times if C1[M] = 1 and C4[M10] = 0 12 bit times if C1[M] = 1, C4[M10] = 1, and S1[PE] = 1 #0 1 Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1. #1 LBKDIF LIN Break Detect Interrupt Flag 7 1 read-write 0 No LIN break character detected. #0 1 LIN break character detected. #1 MSBF Most Significant Bit First 5 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE]. #1 RAF Receiver Active Flag 0 1 read-only 0 UART receiver idle/inactive waiting for a start bit. #0 1 UART receiver active, RxD input not idle. #1 RWUID Receive Wakeup Idle Detect 3 1 read-write 0 S1[IDLE] is not set upon detection of an idle character. #0 1 S1[IDLE] is set upon detection of an idle character. #1 RXEDGIF RxD Pin Active Edge Interrupt Flag 6 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 RXINV Receive Data Inversion 4 1 read-write 0 Receive data is not inverted. #0 1 Receive data is inverted. #1 SFIFO UART FIFO Status Register 0x12 8 read-write n 0x0 0x0 RESERVED no description available 3 3 read-only RXEMPT Receive Buffer/FIFO Empty 6 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 RXOF Receiver Buffer Overflow Flag 2 1 read-write 0 No receive buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer overflow has occurred since the last time the flag was cleared. #1 RXUF Receiver Buffer Underflow Flag 0 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 TXEMPT Transmit Buffer/FIFO Empty 7 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 TXOF Transmitter Buffer Overflow Flag 1 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 TCFIFO UART FIFO Transmit Count 0x14 8 read-only n 0x0 0x0 TXCOUNT Transmit Counter 0 8 read-only TWFIFO UART FIFO Transmit Watermark 0x13 8 read-write n 0x0 0x0 TXWATER Transmit Watermark 0 8 read-write UART5 Serial Communication Interface UART 0x0 0x0 0x17 registers n UART5_RX_TX 55 UART5_ERR 56 INT_UART5_RX_TX 71 INT_UART5_ERR 72 BDH UART Baud Rate Registers: High 0x0 8 read-write n 0x0 0x0 LBKDIE LIN Break Detect Interrupt Enable 7 1 read-write 0 LBKDIF interrupt requests disabled. #0 1 LBKDIF interrupt requests enabled. #1 RESERVED no description available 5 1 read-only RXEDGIE RxD Input Active Edge Interrupt Enable 6 1 read-write 0 Hardware interrupts from RXEDGIF disabled using polling. #0 1 RXEDGIF interrupt request enabled. #1 SBR UART Baud Rate Bits 0 5 read-write BDL UART Baud Rate Registers: Low 0x1 8 read-write n 0x0 0x0 SBR UART Baud Rate Bits 0 8 read-write C1 UART Control Register 1 0x2 8 read-write n 0x0 0x0 ILT Idle Line Type Select 2 1 read-write 0 Idle character bit count starts after start bit. #0 1 Idle character bit count starts after stop bit. #1 LOOPS Loop Mode Select 7 1 read-write 0 Normal operation. #0 1 Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC. #1 M 9-bit or 8-bit Mode Select 4 1 read-write 0 Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop. #0 1 Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop. #1 PE Parity Enable 1 1 read-write 0 Parity function disabled. #0 1 Parity function enabled. #1 PT Parity Type 0 1 read-write 0 Even parity. #0 1 Odd parity. #1 RSRC Receiver Source Select 5 1 read-write 0 Selects internal loop back mode. The receiver input is internally connected to transmitter output. #0 1 Single wire UART mode where the receiver input is connected to the transmit pin input signal. #1 UARTSWAI UART Stops in Wait Mode 6 1 read-write 0 UART clock continues to run in Wait mode. #0 1 UART clock freezes while CPU is in Wait mode. #1 WAKE Receiver Wakeup Method Select 3 1 read-write 0 Idle line wakeup. #0 1 Address mark wakeup. #1 C2 UART Control Register 2 0x3 8 read-write n 0x0 0x0 ILIE Idle Line Interrupt Enable 4 1 read-write 0 IDLE interrupt requests disabled. #0 1 IDLE interrupt requests enabled. #1 RE Receiver Enable 2 1 read-write 0 Receiver off. #0 1 Receiver on. #1 RIE Receiver Full Interrupt or DMA Transfer Enable 5 1 read-write 0 RDRF interrupt and DMA transfer requests disabled. #0 1 RDRF interrupt or DMA transfer requests enabled. #1 RWU Receiver Wakeup Control 1 1 read-write 0 Normal operation. #0 1 RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU. #1 SBK Send Break 0 1 read-write 0 Normal transmitter operation. #0 1 Queue break characters to be sent. #1 TCIE Transmission Complete Interrupt Enable 6 1 read-write 0 TC interrupt requests disabled. #0 1 TC interrupt requests enabled. #1 TE Transmitter Enable 3 1 read-write 0 Transmitter off. #0 1 Transmitter on. #1 TIE Transmitter Interrupt or DMA Transfer Enable. 7 1 read-write 0 TDRE interrupt and DMA transfer requests disabled. #0 1 TDRE interrupt or DMA transfer requests enabled. #1 C3 UART Control Register 3 0x6 8 read-write n 0x0 0x0 FEIE Framing Error Interrupt Enable 1 1 read-write 0 FE interrupt requests are disabled. #0 1 FE interrupt requests are enabled. #1 NEIE Noise Error Interrupt Enable 2 1 read-write 0 NF interrupt requests are disabled. #0 1 NF interrupt requests are enabled. #1 ORIE Overrun Error Interrupt Enable 3 1 read-write 0 OR interrupts are disabled. #0 1 OR interrupt requests are enabled. #1 PEIE Parity Error Interrupt Enable 0 1 read-write 0 PF interrupt requests are disabled. #0 1 PF interrupt requests are enabled. #1 R8 Received Bit 8 7 1 read-only T8 Transmit Bit 8 6 1 read-write TXDIR Transmitter Pin Data Direction in Single-Wire mode 5 1 read-write 0 TXD pin is an input in single wire mode. #0 1 TXD pin is an output in single wire mode. #1 TXINV Transmit Data Inversion. 4 1 read-write 0 Transmit data is not inverted. #0 1 Transmit data is inverted. #1 C4 UART Control Register 4 0xA 8 read-write n 0x0 0x0 BRFA Baud Rate Fine Adjust 0 5 read-write M10 10-bit Mode select 5 1 read-write 0 The parity bit is the ninth bit in the serial transmission. #0 1 The parity bit is the tenth bit in the serial transmission. #1 MAEN1 Match Address Mode Enable 1 7 1 read-write 0 All data received is transferred to the data buffer if MAEN2 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled. #1 MAEN2 Match Address Mode Enable 2 6 1 read-write 0 All data received is transferred to the data buffer if MAEN1 is cleared. #0 1 All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled. #1 C5 UART Control Register 5 0xB 8 read-write n 0x0 0x0 RDMAS Receiver Full DMA Select 5 1 read-write 0 If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service. #0 1 If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer. #1 RESERVED no description available 0 5 read-only RESERVED no description available 6 1 read-only TDMAS Transmitter DMA Select 7 1 read-write 0 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service. #0 1 If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer. #1 CFIFO UART FIFO Control Register 0x11 8 read-write n 0x0 0x0 RESERVED no description available 3 3 read-only RXFLUSH Receive FIFO/Buffer Flush 6 1 write-only 0 No flush operation occurs. #0 1 All data in the receive FIFO/buffer is cleared out. #1 RXOFE Receive FIFO Overflow Interrupt Enable 2 1 read-write 0 RXOF flag does not generate an interrupt to the host. #0 1 RXOF flag generates an interrupt to the host. #1 RXUFE Receive FIFO Underflow Interrupt Enable 0 1 read-write 0 RXUF flag does not generate an interrupt to the host. #0 1 RXUF flag generates an interrupt to the host. #1 TXFLUSH Transmit FIFO/Buffer Flush 7 1 write-only 0 No flush operation occurs. #0 1 All data in the transmit FIFO/Buffer is cleared out. #1 TXOFE Transmit FIFO Overflow Interrupt Enable 1 1 read-write 0 TXOF flag does not generate an interrupt to the host. #0 1 TXOF flag generates an interrupt to the host. #1 D UART Data Register 0x7 8 read-write n 0x0 0x0 RT no description available 0 8 read-write ED UART Extended Data Register 0xC 8 read-only n 0x0 0x0 NOISY no description available 7 1 read-only 0 The dataword was received without noise. #0 1 The data was received with noise. #1 PARITYE no description available 6 1 read-only 0 The dataword was received without a parity error. #0 1 The dataword was received with a parity error. #1 RESERVED no description available 0 6 read-only IR UART Infrared Register 0xE 8 read-write n 0x0 0x0 IREN Infrared enable 2 1 read-write 0 IR disabled. #0 1 IR enabled. #1 RESERVED no description available 3 5 read-only TNP Transmitter narrow pulse 0 2 read-write 00 3/16. #00 01 1/16. #01 10 1/32. #10 11 1/4. #11 MA1 UART Match Address Registers 1 0x8 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MA2 UART Match Address Registers 2 0x9 8 read-write n 0x0 0x0 MA Match Address 0 8 read-write MODEM UART Modem Register 0xD 8 read-write n 0x0 0x0 RESERVED no description available 4 4 read-only RXRTSE Receiver request-to-send enable 3 1 read-write 0 The receiver has no effect on RTS. #0 1 RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER]. #1 TXCTSE Transmitter clear-to-send enable 0 1 read-write 0 CTS has no effect on the transmitter. #0 1 Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission. #1 TXRTSE Transmitter request-to-send enable 1 1 read-write 0 The transmitter has no effect on RTS. #0 1 When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO) #1 TXRTSPOL Transmitter request-to-send polarity 2 1 read-write 0 Transmitter RTS is active low. #0 1 Transmitter RTS is active high. #1 PFIFO UART FIFO Parameters 0x10 8 read-write n 0x0 0x0 RXFE Receive FIFO Enable 3 1 read-write 0 Receive FIFO is not enabled. Buffer is depth 1. (Legacy support) #0 1 Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE. #1 RXFIFOSIZE Receive FIFO. Buffer Depth 0 3 read-only 000 Receive FIFO/Buffer depth = 1 dataword. #000 001 Receive FIFO/Buffer depth = 4 datawords. #001 010 Receive FIFO/Buffer depth = 8 datawords. #010 011 Receive FIFO/Buffer depth = 16 datawords. #011 100 Receive FIFO/Buffer depth = 32 datawords. #100 101 Receive FIFO/Buffer depth = 64 datawords. #101 110 Receive FIFO/Buffer depth = 128 datawords. #110 111 Reserved. #111 TXFE Transmit FIFO Enable 7 1 read-write 0 Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support). #0 1 Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE. #1 TXFIFOSIZE Transmit FIFO. Buffer Depth 4 3 read-only 000 Transmit FIFO/Buffer depth = 1 dataword. #000 001 Transmit FIFO/Buffer depth = 4 datawords. #001 010 Transmit FIFO/Buffer depth = 8 datawords. #010 011 Transmit FIFO/Buffer depth = 16 datawords. #011 100 Transmit FIFO/Buffer depth = 32 datawords. #100 101 Transmit FIFO/Buffer depth = 64 datawords. #101 110 Transmit FIFO/Buffer depth = 128 datawords. #110 111 Reserved. #111 RCFIFO UART FIFO Receive Count 0x16 8 read-only n 0x0 0x0 RXCOUNT Receive Counter 0 8 read-only RWFIFO UART FIFO Receive Watermark 0x15 8 read-write n 0x0 0x0 RXWATER Receive Watermark 0 8 read-write S1 UART Status Register 1 0x4 8 read-only n 0x0 0x0 FE Framing Error Flag 1 1 read-only 0 No framing error detected. #0 1 Framing error. #1 IDLE Idle Line Flag 4 1 read-only 0 Receiver input is either active now or has never become active since the IDLE flag was last cleared. #0 1 Receiver input has become idle or the flag has not been cleared since it last asserted. #1 NF Noise Flag 2 1 read-only 0 No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise. #0 1 At least one dataword was received with noise detected since the last time the flag was cleared. #1 OR Receiver Overrun Flag 3 1 read-only 0 No overrun has occurred since the last time the flag was cleared. #0 1 Overrun has occurred or the overrun flag has not been cleared since the last overrun occured. #1 PF Parity Error Flag 0 1 read-only 0 No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error. #0 1 At least one dataword was received with a parity error since the last time this flag was cleared. #1 RDRF Receive Data Register Full Flag 5 1 read-only 0 The number of datawords in the receive buffer is less than the number indicated by RXWATER. #0 1 The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared. #1 TC Transmit Complete Flag 6 1 read-only 0 Transmitter active (sending data, a preamble, or a break). #0 1 Transmitter idle (transmission activity complete). #1 TDRE Transmit Data Register Empty Flag 7 1 read-only 0 The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER]. #0 1 The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared. #1 S2 UART Status Register 2 0x5 8 read-write n 0x0 0x0 BRK13 Break Transmit Character Length 2 1 read-write 0 Break character is 10, 11, or 12 bits long. #0 1 Break character is 13 or 14 bits long. #1 LBKDE LIN Break Detection Enable 1 1 read-write 0 Break character is detected at one of the following lengths: 10 bit times if C1[M] = 0 11 bit times if C1[M] = 1 and C4[M10] = 0 12 bit times if C1[M] = 1, C4[M10] = 1, and S1[PE] = 1 #0 1 Break character is detected at length of 11 bit times if C1[M] = 0 or 12 bits time if C1[M] = 1. #1 LBKDIF LIN Break Detect Interrupt Flag 7 1 read-write 0 No LIN break character detected. #0 1 LIN break character detected. #1 MSBF Most Significant Bit First 5 1 read-write 0 LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0. #0 1 MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE]. #1 RAF Receiver Active Flag 0 1 read-only 0 UART receiver idle/inactive waiting for a start bit. #0 1 UART receiver active, RxD input not idle. #1 RWUID Receive Wakeup Idle Detect 3 1 read-write 0 S1[IDLE] is not set upon detection of an idle character. #0 1 S1[IDLE] is set upon detection of an idle character. #1 RXEDGIF RxD Pin Active Edge Interrupt Flag 6 1 read-write 0 No active edge on the receive pin has occurred. #0 1 An active edge on the receive pin has occurred. #1 RXINV Receive Data Inversion 4 1 read-write 0 Receive data is not inverted. #0 1 Receive data is inverted. #1 SFIFO UART FIFO Status Register 0x12 8 read-write n 0x0 0x0 RESERVED no description available 3 3 read-only RXEMPT Receive Buffer/FIFO Empty 6 1 read-only 0 Receive buffer is not empty. #0 1 Receive buffer is empty. #1 RXOF Receiver Buffer Overflow Flag 2 1 read-write 0 No receive buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer overflow has occurred since the last time the flag was cleared. #1 RXUF Receiver Buffer Underflow Flag 0 1 read-write 0 No receive buffer underflow has occurred since the last time the flag was cleared. #0 1 At least one receive buffer underflow has occurred since the last time the flag was cleared. #1 TXEMPT Transmit Buffer/FIFO Empty 7 1 read-only 0 Transmit buffer is not empty. #0 1 Transmit buffer is empty. #1 TXOF Transmitter Buffer Overflow Flag 1 1 read-write 0 No transmit buffer overflow has occurred since the last time the flag was cleared. #0 1 At least one transmit buffer overflow has occurred since the last time the flag was cleared. #1 TCFIFO UART FIFO Transmit Count 0x14 8 read-only n 0x0 0x0 TXCOUNT Transmit Counter 0 8 read-only TWFIFO UART FIFO Transmit Watermark 0x13 8 read-write n 0x0 0x0 TXWATER Transmit Watermark 0 8 read-write USB0 Universal Serial Bus, OTG Capable Controller USB0 0x0 0x0 0x115 registers n USB0 73 INT_USB0 89 ADDINFO Peripheral Additional Info Register 0xC 8 read-only n 0x0 0x0 IEHOST no description available 0 1 read-only IRQNUM Assigned Interrupt Request Number 3 5 read-only RESERVED no description available 1 2 read-only ADDR Address Register 0x98 8 read-write n 0x0 0x0 ADDR USB address 0 7 read-write LSEN Low Speed Enable bit 7 1 read-write BDTPAGE1 BDT Page Register 1 0x9C 8 read-write n 0x0 0x0 BDTBA no description available 1 7 read-write RESERVED no description available 0 1 read-only BDTPAGE2 BDT Page Register 2 0xB0 8 read-write n 0x0 0x0 BDTBA no description available 0 8 read-write BDTPAGE3 BDT Page Register 3 0xB4 8 read-write n 0x0 0x0 BDTBA no description available 0 8 read-write CONTROL USB OTG Control Register 0x108 8 read-write n 0x0 0x0 DPPULLUPNONOTG no description available 4 1 read-write 0 DP Pull up in non-OTG device mode is not enabled. #0 1 DP Pull up in non-OTG device mode is enabled. #1 RESERVED no description available 0 4 read-only RESERVED no description available 5 3 read-only CTL Control Register 0x94 8 read-write n 0x0 0x0 HOSTMODEEN no description available 3 1 read-write JSTATE Live USB differential receiver JSTATE signal 7 1 read-write ODDRST no description available 1 1 read-write RESET no description available 4 1 read-write RESUME no description available 2 1 read-write SE0 Live USB Single Ended Zero signal 6 1 read-write TXSUSPENDTOKENBUSY no description available 5 1 read-write USBENSOFEN USB Enable 0 1 read-write 0 The USB Module is disabled. #0 1 The USB Module is enabled. #1 ENDPT0 Endpoint Control Register 0x180 8 read-write n 0x0 0x0 EPCTLDIS no description available 4 1 read-write EPHSHK no description available 0 1 read-write EPRXEN no description available 3 1 read-write EPSTALL no description available 1 1 read-write EPTXEN no description available 2 1 read-write HOSTWOHUB no description available 7 1 read-write RESERVED no description available 5 1 read-only RETRYDIS no description available 6 1 read-write ENDPT1 Endpoint Control Register 0x244 8 read-write n 0x0 0x0 EPCTLDIS no description available 4 1 read-write EPHSHK no description available 0 1 read-write EPRXEN no description available 3 1 read-write EPSTALL no description available 1 1 read-write EPTXEN no description available 2 1 read-write HOSTWOHUB no description available 7 1 read-write RESERVED no description available 5 1 read-only RETRYDIS no description available 6 1 read-write ENDPT10 Endpoint Control Register 0x9DC 8 read-write n 0x0 0x0 EPCTLDIS no description available 4 1 read-write EPHSHK no description available 0 1 read-write EPRXEN no description available 3 1 read-write EPSTALL no description available 1 1 read-write EPTXEN no description available 2 1 read-write HOSTWOHUB no description available 7 1 read-write RESERVED no description available 5 1 read-only RETRYDIS no description available 6 1 read-write ENDPT11 Endpoint Control Register 0xAC8 8 read-write n 0x0 0x0 EPCTLDIS no description available 4 1 read-write EPHSHK no description available 0 1 read-write EPRXEN no description available 3 1 read-write EPSTALL no description available 1 1 read-write EPTXEN no description available 2 1 read-write HOSTWOHUB no description available 7 1 read-write RESERVED no description available 5 1 read-only RETRYDIS no description available 6 1 read-write ENDPT12 Endpoint Control Register 0xBB8 8 read-write n 0x0 0x0 EPCTLDIS no description available 4 1 read-write EPHSHK no description available 0 1 read-write EPRXEN no description available 3 1 read-write EPSTALL no description available 1 1 read-write EPTXEN no description available 2 1 read-write HOSTWOHUB no description available 7 1 read-write RESERVED no description available 5 1 read-only RETRYDIS no description available 6 1 read-write ENDPT13 Endpoint Control Register 0xCAC 8 read-write n 0x0 0x0 EPCTLDIS no description available 4 1 read-write EPHSHK no description available 0 1 read-write EPRXEN no description available 3 1 read-write EPSTALL no description available 1 1 read-write EPTXEN no description available 2 1 read-write HOSTWOHUB no description available 7 1 read-write RESERVED no description available 5 1 read-only RETRYDIS no description available 6 1 read-write ENDPT14 Endpoint Control Register 0xDA4 8 read-write n 0x0 0x0 EPCTLDIS no description available 4 1 read-write EPHSHK no description available 0 1 read-write EPRXEN no description available 3 1 read-write EPSTALL no description available 1 1 read-write EPTXEN no description available 2 1 read-write HOSTWOHUB no description available 7 1 read-write RESERVED no description available 5 1 read-only RETRYDIS no description available 6 1 read-write ENDPT15 Endpoint Control Register 0xEA0 8 read-write n 0x0 0x0 EPCTLDIS no description available 4 1 read-write EPHSHK no description available 0 1 read-write EPRXEN no description available 3 1 read-write EPSTALL no description available 1 1 read-write EPTXEN no description available 2 1 read-write HOSTWOHUB no description available 7 1 read-write RESERVED no description available 5 1 read-only RETRYDIS no description available 6 1 read-write ENDPT2 Endpoint Control Register 0x30C 8 read-write n 0x0 0x0 EPCTLDIS no description available 4 1 read-write EPHSHK no description available 0 1 read-write EPRXEN no description available 3 1 read-write EPSTALL no description available 1 1 read-write EPTXEN no description available 2 1 read-write HOSTWOHUB no description available 7 1 read-write RESERVED no description available 5 1 read-only RETRYDIS no description available 6 1 read-write ENDPT3 Endpoint Control Register 0x3D8 8 read-write n 0x0 0x0 EPCTLDIS no description available 4 1 read-write EPHSHK no description available 0 1 read-write EPRXEN no description available 3 1 read-write EPSTALL no description available 1 1 read-write EPTXEN no description available 2 1 read-write HOSTWOHUB no description available 7 1 read-write RESERVED no description available 5 1 read-only RETRYDIS no description available 6 1 read-write ENDPT4 Endpoint Control Register 0x4A8 8 read-write n 0x0 0x0 EPCTLDIS no description available 4 1 read-write EPHSHK no description available 0 1 read-write EPRXEN no description available 3 1 read-write EPSTALL no description available 1 1 read-write EPTXEN no description available 2 1 read-write HOSTWOHUB no description available 7 1 read-write RESERVED no description available 5 1 read-only RETRYDIS no description available 6 1 read-write ENDPT5 Endpoint Control Register 0x57C 8 read-write n 0x0 0x0 EPCTLDIS no description available 4 1 read-write EPHSHK no description available 0 1 read-write EPRXEN no description available 3 1 read-write EPSTALL no description available 1 1 read-write EPTXEN no description available 2 1 read-write HOSTWOHUB no description available 7 1 read-write RESERVED no description available 5 1 read-only RETRYDIS no description available 6 1 read-write ENDPT6 Endpoint Control Register 0x654 8 read-write n 0x0 0x0 EPCTLDIS no description available 4 1 read-write EPHSHK no description available 0 1 read-write EPRXEN no description available 3 1 read-write EPSTALL no description available 1 1 read-write EPTXEN no description available 2 1 read-write HOSTWOHUB no description available 7 1 read-write RESERVED no description available 5 1 read-only RETRYDIS no description available 6 1 read-write ENDPT7 Endpoint Control Register 0x730 8 read-write n 0x0 0x0 EPCTLDIS no description available 4 1 read-write EPHSHK no description available 0 1 read-write EPRXEN no description available 3 1 read-write EPSTALL no description available 1 1 read-write EPTXEN no description available 2 1 read-write HOSTWOHUB no description available 7 1 read-write RESERVED no description available 5 1 read-only RETRYDIS no description available 6 1 read-write ENDPT8 Endpoint Control Register 0x810 8 read-write n 0x0 0x0 EPCTLDIS no description available 4 1 read-write EPHSHK no description available 0 1 read-write EPRXEN no description available 3 1 read-write EPSTALL no description available 1 1 read-write EPTXEN no description available 2 1 read-write HOSTWOHUB no description available 7 1 read-write RESERVED no description available 5 1 read-only RETRYDIS no description available 6 1 read-write ENDPT9 Endpoint Control Register 0x8F4 8 read-write n 0x0 0x0 EPCTLDIS no description available 4 1 read-write EPHSHK no description available 0 1 read-write EPRXEN no description available 3 1 read-write EPSTALL no description available 1 1 read-write EPTXEN no description available 2 1 read-write HOSTWOHUB no description available 7 1 read-write RESERVED no description available 5 1 read-only RETRYDIS no description available 6 1 read-write ERREN Error Interrupt Enable Register 0x8C 8 read-write n 0x0 0x0 BTOERREN BTOERR Interrupt Enable 4 1 read-write 0 The BTOERR interrupt is not enabled. #0 1 The BTOERR interrupt is enabled. #1 BTSERREN BTSERR Interrupt Enable 7 1 read-write 0 The BTSERR interrupt is not enabled. #0 1 The BTSERR interrupt is enabled. #1 CRC16EN CRC16 Interrupt Enable 2 1 read-write 0 The CRC16 interrupt is not enabled. #0 1 The CRC16 interrupt is enabled. #1 CRC5EOFEN CRC5/EOF Interrupt Enable 1 1 read-write 0 The CRC5/EOF interrupt is not enabled. #0 1 The CRC5/EOF interrupt is enabled. #1 DFN8EN DFN8 Interrupt Enable 3 1 read-write 0 The DFN8 interrupt is not enabled. #0 1 The DFN8 interrupt is enabled. #1 DMAERREN DMAERR Interrupt Enable 5 1 read-write 0 The DMAERR interrupt is not enabled. #0 1 The DMAERR interrupt is enabled. #1 PIDERREN PIDERR Interrupt Enable 0 1 read-write 0 The PIDERR interrupt is not enabled. #0 1 The PIDERR interrupt is enabled. #1 RESERVED no description available 6 1 read-only ERRSTAT Error Interrupt Status Register 0x88 8 read-write n 0x0 0x0 BTOERR no description available 4 1 read-write BTSERR no description available 7 1 read-write CRC16 no description available 2 1 read-write CRC5EOF no description available 1 1 read-write DFN8 no description available 3 1 read-write DMAERR no description available 5 1 read-write PIDERR no description available 0 1 read-write RESERVED no description available 6 1 read-only FRMNUMH Frame Number Register High 0xA4 8 read-write n 0x0 0x0 FRM no description available 0 3 read-write RESERVED no description available 3 5 read-only FRMNUML Frame Number Register Low 0xA0 8 read-write n 0x0 0x0 FRM no description available 0 8 read-write IDCOMP Peripheral ID Complement Register 0x4 8 read-only n 0x0 0x0 NID no description available 0 6 read-only RESERVED no description available 6 2 read-only INTEN Interrupt Enable Register 0x84 8 read-write n 0x0 0x0 ATTACHEN ATTACH Interrupt Enable 6 1 read-write 0 The ATTACH interrupt is not enabled. #0 1 The ATTACH interrupt is enabled. #1 ERROREN ERROR Interrupt Enable 1 1 read-write 0 The ERROR interrupt is not enabled. #0 1 The ERROR interrupt is enabled. #1 RESUMEEN RESUME Interrupt Enable 5 1 read-write 0 The RESUME interrupt is not enabled. #0 1 The RESUME interrupt is enabled. #1 SLEEPEN SLEEP Interrupt Enable 4 1 read-write 0 The SLEEP interrupt is not enabled. #0 1 The SLEEP interrupt is enabled. #1 SOFTOKEN SOFTOK Interrupt Enable 2 1 read-write 0 The SOFTOK interrupt is not enabled. #0 1 The SOFTOK interrupt is enabled. #1 STALLEN STALL Interrupt Enable 7 1 read-write 0 The STALL interrupt is not enabled. #0 1 The STALL interrupt is enabled. #1 TOKDNEEN TOKDNE Interrupt Enable 3 1 read-write 0 The TOKDNE interrupt is not enabled. #0 1 The TOKDNE interrupt is enabled. #1 USBRSTEN USBRST Interrupt Enable 0 1 read-write 0 The USBRST interrupt is not enabled. #0 1 The USBRST interrupt is enabled. #1 ISTAT Interrupt Status Register 0x80 8 read-write n 0x0 0x0 ATTACH Attach Interrupt 6 1 read-write ERROR no description available 1 1 read-write RESUME no description available 5 1 read-write SLEEP no description available 4 1 read-write SOFTOK no description available 2 1 read-write STALL Stall Interrupt 7 1 read-write TOKDNE no description available 3 1 read-write USBRST no description available 0 1 read-write OBSERVE USB OTG Observe Register 0x104 8 read-only n 0x0 0x0 DMPD no description available 4 1 read-only 0 D- pulldown disabled. #0 1 D- pulldown enabled. #1 DPPD no description available 6 1 read-only 0 D+ pulldown disabled. #0 1 D+ pulldown enabled. #1 DPPU no description available 7 1 read-only 0 D+ pullup disabled. #0 1 D+ pullup enabled. #1 RESERVED no description available 0 1 read-only RESERVED no description available 1 3 read-only RESERVED no description available 5 1 read-only OTGCTL OTG Control Register 0x1C 8 read-write n 0x0 0x0 DMLOW D- Data Line pull-down resistor enable 4 1 read-write 0 D- pulldown resistor is not enabled. #0 1 D- pulldown resistor is enabled. #1 DPHIGH D+ Data Line pullup resistor enable 7 1 read-write 0 D+ pullup resistor is not enabled #0 1 D+ pullup resistor is enabled #1 DPLOW D+ Data Line pull-down resistor enable 5 1 read-write 0 D+ pulldown resistor is not enabled. #0 1 D+ pulldown resistor is enabled. #1 OTGEN On-The-Go pullup/pulldown resistor enable 2 1 read-write 0 If USB_EN is set and HOST_MODE is clear in the Control Register (CTL), then the D+ Data Line pull-up resistors are enabled. If HOST_MODE is set the D+ and D- Data Line pull-down resistors are engaged. #0 1 The pull-up and pull-down controls in this register are used. #1 RESERVED no description available 0 2 read-only RESERVED no description available 3 1 read-only RESERVED no description available 6 1 read-only OTGICR OTG Interrupt Control Register 0x14 8 read-write n 0x0 0x0 AVBUSEN A VBUS Valid interrupt enable 0 1 read-write 0 The AVBUSCHG interrupt is disabled #0 1 The AVBUSCHG interrupt is enabled #1 BSESSEN B Session END interrupt enable 2 1 read-write 0 The B_SESS_CHG interrupt is disabled #0 1 The B_SESS_CHG interrupt is enabled #1 IDEN ID interrupt enable 7 1 read-write 0 The ID interrupt is disabled #0 1 The ID interrupt is enabled #1 LINESTATEEN Line State change interrupt enable 5 1 read-write 0 The LINE_STAT_CHG interrupt is disabled. #0 1 The LINE_STAT_CHG interrupt is enabled #1 ONEMSECEN 1 millisecond interrupt enable 6 1 read-write 0 The 1msec timer interrupt is disabled. #0 1 The 1msec timer interrupt is enabled. #1 RESERVED no description available 1 1 read-only RESERVED no description available 4 1 read-only SESSVLDEN Session valid interrupt enable 3 1 read-write 0 The SESSVLDCHG interrupt is disabled. #0 1 The SESSVLDCHG interrupt is enabled. #1 OTGISTAT OTG Interrupt Status Register 0x10 8 read-write n 0x0 0x0 AVBUSCHG no description available 0 1 read-write B_SESS_CHG no description available 2 1 read-write IDCHG no description available 7 1 read-write LINE_STATE_CHG no description available 5 1 read-write ONEMSEC no description available 6 1 read-write RESERVED no description available 1 1 read-only RESERVED no description available 4 1 read-only SESSVLDCHG no description available 3 1 read-write OTGSTAT OTG Status Register 0x18 8 read-write n 0x0 0x0 AVBUSVLD A VBUS Valid 0 1 read-write 0 The VBUS voltage is below the A VBUS Valid threshold. #0 1 The VBUS voltage is above the A VBUS Valid threshold. #1 BSESSEND B Session END 2 1 read-write 0 The VBUS voltage is above the B session End threshold. #0 1 The VBUS voltage is below the B session End threshold. #1 ID no description available 7 1 read-write 0 Indicates a Type A cable has been plugged into the USB connector #0 1 Indicates no cable is attached or a Type B cable has been plugged into the USB connector #1 LINESTATESTABLE no description available 5 1 read-write 0 The LINE_STAT_CHG bit is not yet stable. #0 1 The LINE_STAT_CHG bit has been debounced and is stable. #1 ONEMSECEN no description available 6 1 read-write RESERVED no description available 1 1 read-only RESERVED no description available 4 1 read-only SESS_VLD Session valid 3 1 read-write 0 The VBUS voltage is below the B session Valid threshold #0 1 The VBUS voltage is above the B session Valid threshold. #1 PERID Peripheral ID Register 0x0 8 read-only n 0x0 0x0 ID Peripheral identification bits 0 6 read-only RESERVED no description available 6 2 read-only REV Peripheral Revision Register 0x8 8 read-only n 0x0 0x0 REV Revision 0 8 read-only SOFTHLD SOF Threshold Register 0xAC 8 read-write n 0x0 0x0 CNT no description available 0 8 read-write STAT Status Register 0x90 8 read-only n 0x0 0x0 ENDP no description available 4 4 read-only ODD no description available 2 1 read-only RESERVED no description available 0 2 read-only TX Transmit Indicator 3 1 read-only 0 The most recent transaction was a Receive operation. #0 1 The most recent transaction was a Transmit operation. #1 TOKEN Token Register 0xA8 8 read-write n 0x0 0x0 TOKENENDPT no description available 0 4 read-write TOKENPID no description available 4 4 read-write 0001 OUT Token. USB Module performs an OUT (TX) transaction. #0001 1001 IN Token. USB Module performs an In (RX) transaction. #1001 1101 SETUP Token. USB Module performs a SETUP (TX) transaction #1101 USBCTRL USB Control Register 0x100 8 read-write n 0x0 0x0 PDE no description available 6 1 read-write 0 Weak pulldowns are disabled on D+ and D- #0 1 Weak pulldowns are enabled on D+ and D-. #1 RESERVED no description available 0 6 read-only SUSP no description available 7 1 read-write 0 USB transceiver is not in suspend state. #0 1 USB transceiver is in suspend state. #1 USBFRMADJUST Frame Adjust Register 0x114 8 read-write n 0x0 0x0 ADJ Frame Adjustment 0 8 read-write USBTRC0 USB Transceiver Control Register 0 0x10C 8 read-write n 0x0 0x0 RESERVED no description available 2 3 read-only RESERVED no description available 6 1 read-only SYNC_DET Synchronous USB Interrupt Detect 1 1 read-only 0 Synchronous interrupt has not been detected. #0 1 Synchronous interrupt has been detected. #1 USBRESET USB reset 7 1 write-only 0 Normal USB module operation. #0 1 Returns the USB module to its reset state. #1 USBRESMEN Asynchronous Resume Interrupt Enable 5 1 read-write 0 USB asynchronous wakeup from suspend mode disabled. #0 1 USB asynchronous wakeup from suspend mode enabled. The asynchronous resume interrupt differs from the synchronous resume interrupt in that it asynchronously detects K-state using the unfiltered state of the D+ and D- pins. This interupt should only be enabled when the Transceiver is suspended. #1 USB_RESUME_INT USB Asynchronous Interrupt 0 1 read-only 0 No interrupt was generated. #0 1 Interrupt was generated because of the USB asynchronous interrupt. #1 USBDCD USB Device Charger Detection module USBDCD 0x0 0x0 0x1C registers n USBDCD 74 INT_USBDCD 90 CLOCK Clock Register 0x4 32 read-write n 0x0 0x0 CLOCK_SPEED Numerical Value of Clock Speed in Binary 2 10 read-write CLOCK_UNIT Unit of measurement encoding for Clock Speed 0 1 read-write 0 kHz Speed (between 1 kHz and 1023 kHz) #0 1 MHz Speed (between 1 MHz and 1023 MHz) #1 RESERVED no description available 1 1 read-only RESERVED no description available 12 20 read-only CONTROL Control Register 0x0 32 read-write n 0x0 0x0 IACK Interrupt Acknowledge 0 1 write-only 0 Do not clear the interrupt. #0 1 Clear the IF bit (interrupt flag). #1 IE Interrupt Enable 16 1 read-write 0 Disable interrupts to the system. #0 1 Enable interrupts to the system. #1 IF Interrupt Flag 8 1 read-only 0 No interrupt is pending. #0 1 An interrupt is pending. #1 RESERVED no description available 1 7 read-only RESERVED no description available 9 7 read-write RESERVED no description available 17 7 read-only RESERVED no description available 26 6 read-only SR Software Reset 25 1 write-only 0 Do not perform a software reset. #0 1 Perform a software reset. #1 START Start Change Detection Sequence 24 1 write-only 0 Do not start the sequence. Writes of this value have no effect. #0 1 Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect. #1 STATUS Status Register 0x8 32 read-only n 0x0 0x0 ACTIVE Active Status Indicator 22 1 read-only 0 The sequence is not running. #0 1 The sequence is running. #1 ERR Error Flag 20 1 read-only 0 No sequence errors. #0 1 Error in the detection sequence. See the SEQ_STAT field to determine the phase in which the error occurred. #1 RESERVED no description available 0 16 read-only RESERVED no description available 23 9 read-only SEQ_RES Charger Detection Sequence Results 16 2 read-only 00 No results to report. #00 01 Attached to a standard host. Must comply with USB Spec 2.0 by drawing only 2.5mA (max) until connected. #01 10 Attached to a charging port. The exact meaning depends on bit 18: 0: Attached to either a charging host or a dedicated charger (The charger type detection has not completed.) 1: Attached to a charging host (The charger type detection has completed.) #10 11 Attached to a dedicated charger. #11 SEQ_STAT Charger Detection Sequence Status 18 2 read-only 00 The module is either not enabled, or the module is enabled but the data pins have not yet been detected. #00 01 Data pin contact detection is complete. #01 10 Charger detection is complete. #10 11 Charger type detection is complete. #11 TO Timeout Flag 21 1 read-only 0 The detection sequence has not been running for over 1 s. #0 1 It has been over 1 s since the data pin contact was detected and debounced.{ #1 TIMER0 TIMER0 Register 0x10 32 read-write n 0x0 0x0 RESERVED no description available 12 4 read-only RESERVED no description available 26 6 read-only TSEQ_INIT Sequence Initiation Time 16 10 read-write TUNITCON Unit Connection Timer Elapse (in ms) 0 12 read-only TIMER1 no description available 0x14 32 read-write n 0x0 0x0 RESERVED no description available 10 6 read-only RESERVED no description available 26 6 read-only TDCD_DBNC Time Period to Debounce D+ Signal 16 10 read-write TVDPSRC_ON Time Period Comparator Enabled 0 10 read-write TIMER2 no description available 0x18 32 read-write n 0x0 0x0 CHECK_DM Time Before Check of D- Line 0 4 read-write RESERVED no description available 4 12 read-only RESERVED no description available 26 6 read-only TVDPSRC_CON Time Period Before Enabling D+ Pullup 16 10 read-write USBHS USB HS/FS/LS OTG Controller USBHS 0x0 0x0 0x204 registers n USBHS 96 INT_USBHS 112 ASYNCLISTADDR Current Asynchronous List Address Register USBHS 0x158 32 read-write n 0x0 0x0 ASYBASE Link pointer low (LPL) 5 27 read-write RESERVED Reserved 0 5 read-only BURSTSIZE Master Interface Data Burst Size Register 0x160 32 read-write n 0x0 0x0 RESERVED Reserved 16 16 read-only RXPBURST Programable RX Burst length 0 8 read-write TXPBURST Programable TX Burst length 8 8 read-write CONFIGFLAG Configure Flag Register 0x180 32 read-only n 0x0 0x0 RESERVED Reserved 0 1 read-only RESERVED Reserved 1 31 read-only DCCPARAMS Device Controller Capability Parameters 0x124 32 read-only n 0x0 0x0 DC Device Capable 7 1 read-only DEN Device Endpoint Number 0 5 read-only HC Host Capable 8 1 read-only RESERVED Reserved 5 2 read-only RESERVED Reserved 9 23 read-only DCIVERSION Device Controller Interface Version 0x122 16 read-only n 0x0 0x0 DCIVERSION no description available 0 16 read-only DEVICEADDR Device Address Register USBHS 0x154 32 read-write n 0x0 0x0 RESERVED Reserved 0 24 read-only USBADR Device Address 25 7 read-write USBADRA Device Address Advance 24 1 read-write 0 Writes to USBADR are instantaneous. #0 1 When this bit is written to a 1 at the same time or before USBADR is written, the write to the USBADR field is staged and held in a hidden register. After an IN occurs on endpoint 0 and is ACKed, USBADR is loaded from the holding register. #1 ENDPTNAK Endpoint NAK Register 0x178 32 read-write n 0x0 0x0 EPRN RX Endpoint NAK 0 4 read-write EPTN TX Endpoint NAK 16 4 read-write RESERVED Reserved 4 12 read-only RESERVED Reserved 20 12 read-only ENDPTNAKEN Endpoint NAK Enable Register 0x17C 32 read-write n 0x0 0x0 EPRNE RX Endpoint NAK 0 4 read-write EPTNE TX Endpoint NAK 16 4 read-write RESERVED Reserved 4 12 read-only RESERVED Reserved 20 12 read-only EPCOMPLETE Endpoint Complete Register 0x1BC 32 read-write n 0x0 0x0 ERCE Endpoint Receive Complete Event 0 4 read-write ETCE Endpoint Transmit Complete Event 16 4 read-write RESERVED Reserved 4 12 read-only RESERVED Reserved 20 12 read-only EPCR0 Endpoint Control Register 0 0x1C0 32 read-write n 0x0 0x0 RESERVED Reserved 1 1 read-only RESERVED Reserved 4 3 read-only RESERVED Reserved 8 8 read-only RESERVED Reserved 17 1 read-only RESERVED Reserved 20 3 read-only RESERVED This register is not defined in the EHCI specification. Every device implements endpoint 0 as a control endpoint. 24 8 read-only RXE RX endpoint Enable 7 1 read-only 1 Enabled #1 RXS RX endpoint Stall 0 1 read-write 0 Endpoint OK #0 1 Endpoint stalled #1 RXT RX endpoint Type 2 2 read-only 00 Control #00 TXE TX Endpoint Enable 23 1 read-only 1 Enable #1 TXS TX Endpoint Stall 16 1 read-write 0 Endpoint OK #0 1 Endpoint stalled #1 TXT TX Endpoint Type 18 2 read-only 00 Control #00 EPCR1 Endpoint Control Register n 0x388 32 read-write n 0x0 0x0 RESERVED Reserved 4 1 read-only RESERVED Reserved 8 8 read-only RESERVED Reserved 20 1 read-only RESERVED Reserved 24 8 read-only RXD RX endpoint Data sink 1 1 read-write RXE RX endpoint Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 RXI RX data toggle Inhibit 5 1 read-write 0 PID sequencing enabled #0 1 PID sequencing disabled #1 RXR RX data toggle Reset 6 1 write-only RXS RX endpoint Stall 0 1 read-write 0 Endpoint OK #0 1 Endpoint stalled #1 RXT RX endpoint Type 2 2 read-write 00 Control #00 01 Isochronous #01 10 Bulk #10 11 Interrupt #11 TXD TX endpoint Data source 17 1 read-write TXE TX endpoint Enable 23 1 read-write 0 Disabled #0 1 Enabled #1 TXI TX data toggle Inhibit 21 1 read-write 0 PID sequencing enabled #0 1 PID sequencing disabled #1 TXR TX data toggle Reset 22 1 write-only TXS TX endpoint Stall 16 1 read-write 0 Endpoint OK #0 1 Endpoint stalled #1 TXT TX endpoint Type 18 2 read-write 00 Control #00 01 Isochronous #01 10 Bulk #10 11 Interrupt #11 EPCR2 Endpoint Control Register n 0x550 32 read-write n 0x0 0x0 RESERVED Reserved 4 1 read-only RESERVED Reserved 8 8 read-only RESERVED Reserved 20 1 read-only RESERVED Reserved 24 8 read-only RXD RX endpoint Data sink 1 1 read-write RXE RX endpoint Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 RXI RX data toggle Inhibit 5 1 read-write 0 PID sequencing enabled #0 1 PID sequencing disabled #1 RXR RX data toggle Reset 6 1 write-only RXS RX endpoint Stall 0 1 read-write 0 Endpoint OK #0 1 Endpoint stalled #1 RXT RX endpoint Type 2 2 read-write 00 Control #00 01 Isochronous #01 10 Bulk #10 11 Interrupt #11 TXD TX endpoint Data source 17 1 read-write TXE TX endpoint Enable 23 1 read-write 0 Disabled #0 1 Enabled #1 TXI TX data toggle Inhibit 21 1 read-write 0 PID sequencing enabled #0 1 PID sequencing disabled #1 TXR TX data toggle Reset 22 1 write-only TXS TX endpoint Stall 16 1 read-write 0 Endpoint OK #0 1 Endpoint stalled #1 TXT TX endpoint Type 18 2 read-write 00 Control #00 01 Isochronous #01 10 Bulk #10 11 Interrupt #11 EPCR3 Endpoint Control Register n 0x71C 32 read-write n 0x0 0x0 RESERVED Reserved 4 1 read-only RESERVED Reserved 8 8 read-only RESERVED Reserved 20 1 read-only RESERVED Reserved 24 8 read-only RXD RX endpoint Data sink 1 1 read-write RXE RX endpoint Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 RXI RX data toggle Inhibit 5 1 read-write 0 PID sequencing enabled #0 1 PID sequencing disabled #1 RXR RX data toggle Reset 6 1 write-only RXS RX endpoint Stall 0 1 read-write 0 Endpoint OK #0 1 Endpoint stalled #1 RXT RX endpoint Type 2 2 read-write 00 Control #00 01 Isochronous #01 10 Bulk #10 11 Interrupt #11 TXD TX endpoint Data source 17 1 read-write TXE TX endpoint Enable 23 1 read-write 0 Disabled #0 1 Enabled #1 TXI TX data toggle Inhibit 21 1 read-write 0 PID sequencing enabled #0 1 PID sequencing disabled #1 TXR TX data toggle Reset 22 1 write-only TXS TX endpoint Stall 16 1 read-write 0 Endpoint OK #0 1 Endpoint stalled #1 TXT TX endpoint Type 18 2 read-write 00 Control #00 01 Isochronous #01 10 Bulk #10 11 Interrupt #11 EPFLUSH Endpoint Flush Register 0x1B4 32 read-write n 0x0 0x0 FERB Flush Endpoint Receive Buffer 0 4 read-write FETB Flush Endpoint Transmit Buffer 16 4 read-write RESERVED Reserved 4 12 read-only RESERVED Reserved 20 12 read-only EPLISTADDR Endpoint List Address Register USBHS 0x158 32 read-write n 0x0 0x0 EPBASE Endpoint list address 11 21 read-write RESERVED Reserved 0 11 read-only EPPRIME Endpoint Initialization Register 0x1B0 32 read-write n 0x0 0x0 PERB Prime Endpoint Receive Buffer 0 4 read-write PETB Prime Endpoint tTansmit Buffer 16 4 read-write RESERVED Reserved 4 12 read-only RESERVED Reserved 20 12 read-only EPSETUPSR Endpoint Setup Status Register 0x1AC 32 read-write n 0x0 0x0 EPSETUPSTAT Setup Endpoint Status 0 4 read-write RESERVED Reserved 4 28 read-only EPSR Endpoint Status Register 0x1B8 32 read-only n 0x0 0x0 ERBR Endpoint Receive Buffer Ready 0 4 read-only ETBR Endpoint Transmit Buffer Ready 16 4 read-only RESERVED Reserved 4 12 read-only RESERVED Reserved 20 12 read-only FRINDEX Frame Index Register 0x14C 32 read-write n 0x0 0x0 FRINDEX Frame Index 0 14 read-write Reerved Reserved 14 18 read-only GPTIMER0CTL General Purpose Timer n Control Register 0x108 32 read-write n 0x0 0x0 GPTCNT Timer Count 0 24 read-only MODE Timer Mode 24 1 read-write 0 One shot #0 1 Repeat #1 RESERVED Reserved 25 5 read-only RST Timer Reset 30 1 write-only 0 No action #0 1 Load counter value #1 RUN Timer Run 31 1 read-write 0 Timer stop #0 1 Timer run #1 GPTIMER0LD General Purpose Timer n Load Register 0x100 32 read-write n 0x0 0x0 GPTLD no description available 0 24 read-write RESERVED Reserved 24 8 read-only GPTIMER1CTL General Purpose Timer n Control Register 0x194 32 read-write n 0x0 0x0 GPTCNT Timer Count 0 24 read-only MODE Timer Mode 24 1 read-write 0 One shot #0 1 Repeat #1 RESERVED Reserved 25 5 read-only RST Timer Reset 30 1 write-only 0 No action #0 1 Load counter value #1 RUN Timer Run 31 1 read-write 0 Timer stop #0 1 Timer run #1 GPTIMER1LD General Purpose Timer n Load Register 0x188 32 read-write n 0x0 0x0 GPTLD no description available 0 24 read-write RESERVED Reserved 24 8 read-only HCCPARAMS Host Controller Capability Parameters Register 0x108 32 read-only n 0x0 0x0 ADC 64-bit addressing capability. 0 1 read-only ASP Asynchronous Schedule Park capability 2 1 read-only 0 Park not supported. #0 1 Park supported. #1 EECP EHCI Extended Capabilities Pointer 8 8 read-only 0 No extended capabilities are implemented #0 IST Isochronous Scheduling Threshold 4 4 read-only 0 The value of the least significant 3 bits indicates the number of microframes a host controller can hold a set of isochronous data structures (one or more) before flushing the state #0 PFL Programmable Frame List flag 1 1 read-only RESERVED Reserved 3 1 read-only RESERVED Reserved 16 16 read-only HCIVERSION Host Controller Interface Version and Capability Registers Length Register 0x100 32 read-only n 0x0 0x0 CAPLENGTH Capability registers length 0 8 read-only HCIVERSION EHCI revision number 16 16 read-only RESERVED Reserved 8 8 read-only HCSPARAMS Host Controller Structural Parameters Register 0x104 32 read-only n 0x0 0x0 N_CC Number of Companion Controllers 12 4 read-only N_PCC Number Ports per CC 8 4 read-only N_PORTS Number of Ports 0 4 read-only N_PTT Ports per Transaction Translator 20 4 read-only N_TT Number of Transaction Translators. 24 4 read-only PI Port Indicators 16 1 read-only 0 No port indicator fields #0 1 The port status and control registers include a R/W field for controlling the state of the port indicator #1 PPC Power Port Control 4 1 read-only 1 Ports have power port switches #1 RESERVED Reserved 5 3 read-only RESERVED Reserved 17 3 read-only RESERVED Reserved 28 4 read-only HWDEVICE Device Hardware Parameters Register 0xC 32 read-only n 0x0 0x0 DC Device Capable 0 1 read-only DEVEP Device endpoints. 1 5 read-only RESERVED Reserved 6 26 read-only HWGENERAL General Hardware Parameters Register 0x4 32 read-only n 0x0 0x0 PHYM PHY Mode 6 3 read-only RESERVED Reserved 0 1 read-only RESERVED Reserved 1 1 read-only RESERVED Reserved 2 1 read-only RESERVED Reserved 3 3 read-only RESERVED Reserved 11 21 read-only SM Serial mode 9 2 read-only HWHOST Host Hardware Parameters Register 0x8 32 read-only n 0x0 0x0 HC Host Capable 0 1 read-only NPORT Number of Ports 1 3 read-only RESERVED Reserved 4 12 read-only TTASY Transaction translator contexts. 16 8 read-only TTPER Transaction translator periodic contexts. 24 8 read-only HWRXBUF Receive Buffer Hardware Parameters Register 0x14 32 read-only n 0x0 0x0 RESERVED Reserved 16 16 read-only RXADD Receive Address. 8 8 read-only RXBURST Receive Burst. 0 8 read-only HWTXBUF Transmit Buffer Hardware Parameters Register 0x10 32 read-only n 0x0 0x0 RESERVED Reserved 24 7 read-only TXADD Transmit Address. 8 8 read-only TXBURST Transmit Burst. 0 8 read-only TXCHANADD Transmit Channel Address 16 8 read-only TXLC Transmit local Context Registers 31 1 read-only 0 Store device transmit contexts in the TX FIFO #0 1 Store device transmit contexts in a register file #1 ID Identification Register 0x0 32 read-only n 0x0 0x0 ID Configuration number 0 6 read-only NID no description available 8 6 read-only RESERVED Reserved 6 2 read-only RESERVED Reserved 14 2 read-only REVISION Revision 21 4 read-only TAG Tag 16 5 read-only VERSION Version 25 4 read-only VERSIONID Version ID 29 3 read-only OTGSC On-the-Go Status and Control Register 0x1A4 32 read-write n 0x0 0x0 ASV A Session Valid 10 1 read-only 0 VBus is below A session valid threshold #0 1 VBus is above A session valid threshold #1 ASVIE A Session Valid Interrupt Enable 26 1 read-write 0 Disable #0 1 Enable #1 ASVIS A Session Valid Interrupt Status 18 1 read-write AVV A VBus Valid 9 1 read-only 0 VBus is below A VBus valid threshold #0 1 VBus is above A VBus valid threshold #1 AVVIE A VBUS Valid Interrupt Enable 25 1 read-write 0 Disable #0 1 Enable #1 AVVIS A VBUS Valid Interrupt Status 17 1 read-write BSE B Session End 12 1 read-only 0 VBus is above B session end threshold #0 1 VBus is below B session end threshold #1 BSEIE B Session End Interrupt Enable 28 1 read-write 0 Disable #0 1 Enable #1 BSEIS B Session End Interrupt Status 20 1 read-write BSV B Session Valid 11 1 read-only 0 VBus is below B session valid threshold #0 1 VBus is above B session valid threshold #1 BSVIE B Session Valid Interrupt Enable 27 1 read-write 0 Disable #0 1 Enable #1 BSVIS B Session Valid Interrupt Status 19 1 read-write DP Data Pulsing 4 1 read-write 0 The pull-up on DP is not asserted #0 1 The pull-up on DP is asserted for data pulsing during SRP #1 DPIE Data Pulse Interrupt Enable 30 1 read-write 0 Disable #0 1 Enable #1 DPIS Data Pulse interrupt Status 22 1 read-write DPS Data bus Pulsing Status 14 1 read-only 0 No pulsing on port #0 1 Pulsing detected on port #1 HAAR Hardware Assist Auto-Reset 2 1 read-write 0 Disabled. #0 1 Enable automatic reset after connect on host port. #1 HABA Hardware Assist B-Disconnect to A-connect 7 1 read-write 0 Disabled. #0 1 Enable automatic B-disconnect to A-connect sequence. #1 ID USB ID 8 1 read-only 0 A device #0 1 B device #1 IDIE USB ID Interrupt Enable 24 1 read-write 0 Disable #0 1 Enable #1 IDIS USB ID Interrupt Status 16 1 read-write IDPU ID Pull-Up 5 1 read-write 0 Disable pull-up. ID input not sampled. #0 1 Enable pull-up #1 MSE 1 Milli-Second timer interrupt Enable 29 1 read-write 0 Disable #0 1 Enable #1 MSS 1 Milli-Second timer interrupt Status 21 1 read-write MST 1 Milli-Second timer Toggle 13 1 read-only OT OTG Termination 3 1 read-write 0 Disable pull-down on DM #0 1 Enable pull-down on DM #1 RESERVED Reserved 6 1 read-only RESERVED Reserved 15 1 read-only RESERVED Reserved 23 1 read-only RESERVED Reserved 31 1 read-only VC VBUS Charge 1 1 read-write VD VBUS Discharge 0 1 read-write PERIODICLISTBASE Periodic Frame List Base Address Register USBHS 0x154 32 read-write n 0x0 0x0 PERBASE Base address 12 20 read-write RESERVED Reserved 0 12 read-only PORTSC1 Port Status and Control Registers 0x184 32 read-write n 0x0 0x0 CCS Current Connect Status 0 1 read-only 0 No device present (host mode) or attached (device mode) #0 1 Device is present (host mode) or attached (device mode) #1 CSC Connect Change Status 1 1 read-write 0 No change #0 1 Connect status has changed #1 FPR Force Port Resume 6 1 read-write 0 No resume (K-state) detected/driven on port #0 1 Resume detected/driven on port #1 HSP High Speed Port. 9 1 read-only 0 FS or LS #0 1 HS #1 LS Line Status 10 2 read-only 00 SE0 #00 01 J-state #01 10 K-state #10 11 Undefined #11 OCA Over-current active 4 1 read-only 0 Port not in over-current condition #0 1 Port currently in over-current condition #1 OCC Over-Current Change 5 1 read-write 0 No over-current #0 1 Over-current detect #1 PE Port Enabled/disabled 2 1 read-write PEC Port Enable/disable Change 3 1 read-write 0 No change #0 1 Port disabled #1 PFSC Port force Full-Speed Connect 24 1 read-write 0 Allow the port to identify itself as high speed #0 1 Force the port to only connect at full speed #1 PHCD PHY low power suspend 23 1 read-write PIC Port Indicator Control 14 2 read-write PO Port Owner 13 1 read-write PP Port Power 12 1 read-write PR Port Reset 8 1 read-write 0 Port is not in reset #0 1 Port is in reset #1 PSPD Port Speed 26 2 read-only 00 Full speed #00 01 Low speed #01 10 High speed #10 11 Undefined #11 PTC Port Test Control 16 4 read-write 0000 Not enabled #0000 0001 J_STATE #0001 0010 K_STATE #0010 0011 SEQ_NAK #0011 0100 Packet #0100 0101 FORCE_ENABLE_HS #0101 0110 FORCE_ENABLE_FS #0110 0111 FORCE_ENABLE_LS #0111 PTS Port Transceiver Select 30 2 read-write RESERVED Reserved 25 1 read-only RESERVED Reserved 28 1 read-only RESERVED Reserved 29 1 read-only SUSP Suspend 7 1 read-write 0 Port not in suspend state #0 1 Port in suspend state #1 WKCN Wake on Connect enable 20 1 read-write WKDS Wake on Disconnect enable 21 1 read-write WKOC Wake on Over-Current enable 22 1 read-write TTCTRL Host TT Asynchronous Buffer Control 0x15C 32 read-only n 0x0 0x0 Reerved Reserved 31 1 read-only RESERVED Reserved 0 24 read-only TTHA TT Hub Address 24 7 read-only TXFILLTUNING Transmit FIFO Tuning Control Register 0x164 32 read-write n 0x0 0x0 RESERVED Reserved 7 1 read-only RESERVED Reserved 13 3 read-only RESERVED Reserved 22 10 read-only TXFIFOTHRES FIFO burst Threshold 16 6 read-write TXSCHHEALTH Scheduler Health counter 8 5 read-write TXSCHOH Scheduler Overhead 0 7 read-write ULPI_VIEWPORT ULPI Register Access 0x170 32 read-write n 0x0 0x0 RESERVED Reserved 28 1 read-only ULPI_ADDR ULPI data Address 16 8 read-write ULPI_DATRD ULPI Data Read 8 8 read-only ULPI_DATWR ULPI Data Write 0 8 read-write ULPI_PORT ULPI Port number 24 3 read-write ULPI_RUN ULPI Run 30 1 read-write ULPI_RW ULPI Read/Write 29 1 read-write 0 Read #0 1 Write #1 ULPI_SS ULPI Sync State 27 1 read-write 0 Any other state (that is, carkit, serial, low power) #0 1 Normal sync state #1 ULPI_WU ULPI Wake-Up 31 1 read-write USBCMD USB Command Register 0x140 32 read-write n 0x0 0x0 ASE Asynchronous Schedule Enable 5 1 read-write 0 Do not process asynchronous schedule. #0 1 Use the ASYNCLISTADDR register to access asynchronous schedule. #1 ASP Asynchronous Schedule Park mode count 8 2 read-write ASPE Asynchronous Schedule Park mode Enable 11 1 read-write 0 Park mode disabled #0 1 Park mode enabled #1 ATDTW Add dTD TripWire 14 1 read-write FS Frame list Size 2 2 read-write 00 When FS2 = 0, the size is 1024 elements (4096 bytes). When FS2 = 1, the size is 64 elements (256 bytes). #00 01 When FS2 = 0, the size is 512 elements (2048 bytes). When FS2 = 1, the size is 32 elements (128 bytes). #01 10 When FS2 = 0, the size is 256 elements (1024 bytes). When FS2 = 1, the size is 16 elements (64 bytes). #10 11 When FS2 = 0, the size is 128 elements (512 bytes). When FS2 = 1, the size is 8 elements (32 bytes). #11 FS2 Frame list Size 2 15 1 read-write IAA Interrupt on Async Advance doorbell 6 1 read-write ITC Interrupt Threshold Control 16 8 read-write 0 Immediate (no threshold) #0 1 1 microframe #1 10 2 microframes #10 100 4 microframes #100 1000 8 microframes #1000 10000 16 microframes #10000 100000 32 microframes #100000 1000000 64 microframes #1000000 PSE Periodic Schedule Enable 4 1 read-write 0 Do not process periodic schedule. #0 1 Use the PERIODICLISTBASE register to access the periodic schedule. #1 RESERVED Reserved 7 1 read-only RESERVED Reserved 10 1 read-only RESERVED Reserved 12 1 read-only RESERVED Reserved 24 8 read-only RS Run/Stop 0 1 read-write RST Controller Reset 1 1 read-write SUTW Setup TripWire 13 1 read-write USBGENCTRL USB General Control Register 0x200 32 read-write n 0x0 0x0 RESERVED Reserved 2 3 read-write RESERVED Reserved 6 26 read-only WU_IE Wakeup Interrupt Enable 0 1 read-write 0 Disabled #0 1 Enabled #1 WU_INT_CLR Wakeup Interrupt Clear 5 1 read-write 0 Default, no action. #0 1 Clear the wake-up interrupt. #1 WU_ULPI_EN Wakeup on ULPI Interrupt Event 1 1 read-write 0 Disabled #0 1 Enabled #1 USBINTR USB Interrupt Enable Register 0x148 32 read-write n 0x0 0x0 AAE Interrupt on Async advance Enable 5 1 read-write 0 Disabled #0 1 Enabled #1 FRE Frame list Rollover Enable 3 1 read-write 0 Disabled #0 1 Enabled #1 NAKE NAK Interrupt Enable 16 1 read-write 0 Disabled #0 1 Enabled #1 PCE Port Change detect Enable 2 1 read-write 0 Disabled #0 1 Enabled #1 RESERVED Reserved 9 1 read-only RESERVED Reserved 11 5 read-only RESERVED Reserved 17 1 read-only RESERVED Reserved 20 4 read-only RESERVED Reserved 26 6 read-only SEE System Error Enable 4 1 read-write 0 Disabled #0 1 Enabled #1 SLE Sleep (DC suspend) Enable 8 1 read-write 0 Disabled #0 1 Enabled #1 SRE SOF-Received Enable 7 1 read-write 0 Disabled #0 1 Enabled #1 TIE0 General purpose Timer 0 Interrupt Enable 24 1 read-write 0 Disabled #0 1 Enabled #1 TIE1 General purpose Timer 1 Interrupt Enable 25 1 read-write 0 Disabled #0 1 Enabled #1 UAIE USB host Asynchronous Interrupt Enable 18 1 read-write UE USB interrupt Enable 0 1 read-write 0 Disabled #0 1 Enabled #1 UEE USB Error interrupt Enable 1 1 read-write 0 Disabled #0 1 Enabled #1 ULPIE ULPI Enable 10 1 read-write UPIE USB host Periodic Interrupt Enable 19 1 read-write URE USB-Reset Enable 6 1 read-write 0 Disabled #0 1 Enabled #1 USBMODE USB Mode Register 0x1A8 32 read-write n 0x0 0x0 CM Controller Mode 0 2 read-write 00 Idle (default for the USBHS module) #00 01 Reserved #01 10 Device controller #10 11 Host controller #11 ES Endian Select 2 1 read-write 0 Little endian. First byte referenced in least significant byte of 32-bit word. #0 1 Big endian. First byte referenced in most significant byte of 32-bit word. #1 RESERVED Reserved 5 7 read-only RESERVED Reserved 15 17 read-only SDIS Stream DISable 4 1 read-write 0 Inactive #0 1 Active #1 SLOM Setup Lock-Out Mode 3 1 read-write TXHSD Tx to Tx HS Delay 12 3 read-write 000 10 #000 001 11 #001 010 12 #010 011 13 #011 100 14 #100 101 15 #101 110 16 #110 111 17 #111 USBSTS USB Status Register 0x144 32 read-write n 0x0 0x0 AAI Interrupt on Async Advance 5 1 read-write 0 No async advance interrupt #0 1 Async advance interrupt #1 AS Asynchronous schedule Status 15 1 read-only 0 Disabled #0 1 Enabled #1 FRI Frame-list Rollover 3 1 read-write HCH Host Controller Halted 12 1 read-only 0 Running #0 1 Halted #1 NAKI NAK Interrupt 16 1 read-only PCI Port Change detect 2 1 read-write PS Periodic schedule Status 14 1 read-only 0 Disabled #0 1 Enabled #1 RCL Reclamation 13 1 read-only 0 Non-empty asynchronous schedule #0 1 Empty asynchronous schedule #1 RESERVED Reserved 9 1 read-only RESERVED Reserved 11 1 read-only RESERVED Reserved 17 1 read-only RESERVED Reserved 20 4 read-only RESERVED Reserved 26 6 read-only SEI System Error 4 1 read-write 0 Normal operation #0 1 Error #1 SLI Device-controller suspend 8 1 read-write 0 Active #0 1 Suspended #1 SRI SOF Received 7 1 read-write TI0 General purpose Timer 0 Interrupt 24 1 read-write 0 No interrupt #0 1 Interrupt occurred #1 TI1 General purpose Timer 1 Interrupt 25 1 read-write 0 No interrupt #0 1 Interrupt occurred #1 UAI USB host Asynchronous Interrupt 18 1 read-write UEI USB Error Interrupt 1 1 read-write 0 No error #0 1 Error detected #1 UI USB Interrupt (USBINT) 0 1 read-write ULPII ULPI Interrupt 10 1 read-only UPI USB host Periodic Interrupt 19 1 read-write URI USB Reset received 6 1 read-write 0 No reset received #0 1 Reset received #1 USB_SBUSCFG System Bus Interface Configuration Register 0x90 32 read-write n 0x0 0x0 BURSTMODE Burst mode 0 3 read-write 000 INCR burst of unspecified length #000 001 INCR4, non-multiple transfers of INCR4 is decomposed into singles. #001 010 INCR8, non-multiple transfers of INCR8, is decomposed into INCR4 or singles. #010 011 INCR16, non-multiple transfers of INCR16, is decomposed into INCR8, INCR4 or singles. #011 100 Reserved, do not use. #100 101 INCR4, non-multiple transfers of INCR4 is decomposed into smaller unspecified length bursts. #101 110 INCR8, non-multiple transfers of INCR8 is decomposed into smaller unspecified length bursts. #110 111 INCR16, non-multiple transfers of INCR16 is decomposed into smaller unspecified length bursts. #111 RESERVED Reserved 3 29 read-only VREF Voltage Reference VREF 0x0 0x0 0x2 registers n SC VREF Status and Control Register 0x1 8 read-write n 0x0 0x0 MODE_LV Buffer Mode selection 0 2 read-write 00 Bandgap on only, for stabilization and startup #00 01 Reserved #01 10 Tight-regulation buffer enabled #10 11 Reserved #11 REGEN Regulator enable 6 1 read-write 0 Internal 1.75 V regulator is disabled. #0 1 Internal 1.75 V regulator is enabled. #1 RESERVED no description available 3 1 read-only RESERVED no description available 4 1 read-only RESERVED no description available 5 1 read-write VREFEN Internal Voltage Reference enable 7 1 read-write 0 The module is disabled. #0 1 The module is enabled. #1 VREFST Internal Voltage Reference has settled 2 1 read-only 0 The bandgap is disabled or not ready. #0 1 The bandgap is ready. #1 TRM VREF Trim Register 0x0 8 read-write n 0x0 0x0 RESERVED no description available 6 1 read-only RESERVED no description available 7 1 read-write TRIM Trim bits 0 6 read-write 000000 Min #000000 111111 Max #111111 WDOG Generation 2008 Watchdog Timer WDOG 0x0 0x0 0x18 registers n Watchdog 22 INT_Watchdog 38 PRESC Watchdog Prescaler Register 0x16 16 read-write n 0x0 0x0 PRESCVAL no description available 8 3 read-write RESERVED no description available 0 8 read-only RESERVED no description available 11 5 read-only REFRESH Watchdog Refresh Register 0xC 16 read-write n 0x0 0x0 WDOGREFRESH no description available 0 16 read-write RSTCNT Watchdog Reset Count Register 0x14 16 read-write n 0x0 0x0 RSTCNT no description available 0 16 read-write STCTRLH Watchdog Status and Control Register High 0x0 16 read-write n 0x0 0x0 ALLOWUPDATE no description available 4 1 read-write 0 No further updates allowed to WDOG write-once registers. #0 1 WDOG write-once registers can be unlocked for updating. #1 BYTESEL no description available 12 2 read-write 00 Byte 0 selected #00 01 Byte 1 selected #01 10 Byte 2 selected #10 11 Byte 3 selected #11 CLKSRC no description available 1 1 read-write 0 WDOG clock sourced from LPO . #0 1 WDOG clock sourced from alternate clock source. #1 DBGEN no description available 5 1 read-write 0 WDOG is disabled in CPU Debug mode. #0 1 WDOG is enabled in CPU Debug mode. #1 DISTESTWDOG no description available 14 1 read-write 0 WDOG functional test mode is not disabled. #0 1 WDOG functional test mode is disabled permanently until reset. #1 IRQRSTEN no description available 2 1 read-write 0 WDOG time-out generates reset only. #0 1 WDOG time-out initially generates an interrupt. After WCT, it generates a reset. #1 RESERVED no description available 8 1 read-write RESERVED no description available 9 1 read-only RESERVED no description available 15 1 read-only STOPEN no description available 6 1 read-write 0 WDOG is disabled in CPU Stop mode. #0 1 WDOG is enabled in CPU Stop mode. #1 TESTSEL no description available 11 1 read-write 0 Quick test. The timer runs in normal operation. You can load a small time-out value to do a quick test. #0 1 Byte test. Puts the timer in the byte test mode where individual bytes of the timer are enabled for operation and are compared for time-out against the corresponding byte of the programmed time-out value. Select the byte through BYTESEL[1:0] for testing. #1 TESTWDOG no description available 10 1 read-write WAITEN no description available 7 1 read-write 0 WDOG is disabled in CPU Wait mode. #0 1 WDOG is enabled in CPU Wait mode. #1 WDOGEN no description available 0 1 read-write 0 WDOG is disabled. #0 1 WDOG is enabled. #1 WINEN no description available 3 1 read-write 0 Windowing mode is disabled. #0 1 Windowing mode is enabled. #1 STCTRLL Watchdog Status and Control Register Low 0x2 16 read-write n 0x0 0x0 INTFLG no description available 15 1 read-write RESERVED no description available 0 15 read-write TMROUTH Watchdog Timer Output Register High 0x10 16 read-write n 0x0 0x0 TIMEROUTHIGH no description available 0 16 read-write TMROUTL Watchdog Timer Output Register Low 0x12 16 read-write n 0x0 0x0 TIMEROUTLOW no description available 0 16 read-write TOVALH Watchdog Time-out Value Register High 0x4 16 read-write n 0x0 0x0 TOVALHIGH no description available 0 16 read-write TOVALL Watchdog Time-out Value Register Low 0x6 16 read-write n 0x0 0x0 TOVALLOW no description available 0 16 read-write UNLOCK Watchdog Unlock Register 0xE 16 read-write n 0x0 0x0 WDOGUNLOCK no description available 0 16 read-write WINH Watchdog Window Register High 0x8 16 read-write n 0x0 0x0 WINHIGH no description available 0 16 read-write WINL Watchdog Window Register Low 0xA 16 read-write n 0x0 0x0 WINLOW no description available 0 16 read-write